def pageFaultHap(self, hap_cpu, third, forth, memory): cpu = SIM_current_processor() if cpu != hap_cpu: self.lgr.debug('pageFaultHap, wrong cpu %s %s' % (cpu.name, hap_cpu.name)) return cpu, comm, pid = self.task_utils.curProc() eip = self.exception_eip if cpu.architecture == 'arm': reg_num = cpu.iface.int_register.get_number("combined_data_far") else: reg_num = cpu.iface.int_register.get_number("cr2") cr2 = cpu.iface.int_register.read(reg_num) if pid not in self.faulted_pages: self.faulted_pages[pid] = [] if cr2 in self.faulted_pages[pid]: return self.faulted_pages[pid].append(cr2) self.lgr.debug( 'pageFaultHap for %d (%s) at 0x%x faulting address: 0x%x' % (pid, comm, eip, cr2)) if eip != cr2: instruct = SIM_disassemble_address(self.cpu, eip, 1, 0) #self.lgr.debug('faulting instruction %s' % instruct[1]) else: #self.lgr.debug('eip 0x%x not mapped' % eip) pass page_info = pageUtils.findPageTable(cpu, cr2, self.lgr) if not page_info.page_exists: prec = Prec(cpu, comm, pid, cr2, eip) list_addr = self.task_utils.getTaskListPtr() ''' if not, assume not yet in task list ''' if list_addr is not None: SIM_run_alone(self.watchExit, None) self.task_rec_break[pid] = SIM_breakpoint( self.cell, Sim_Break_Linear, Sim_Access_Write, list_addr, self.mem_utils.WORD_SIZE, 0) self.lgr.debug( 'pageFaultHap set list break %d at 0x%x cycle 0x%x' % (self.task_rec_break[pid], list_addr, prec.cycles)) self.task_rec_hap[pid] = SIM_hap_add_callback_index( "Core_Breakpoint_Memop", self.taskRecHap, prec, self.task_rec_break[pid]) #SIM_break_simulation('page fault page does not exist at 0x%x proc %d (%s)' % (cr2, pid, comm)) #self.lgr.debug('page fault page does not exist at 0x%x proc %d (%s)' % (cr2, pid, comm)) ##self.lgr.debug(page_info.valueString()) if not page_info.ptable_exists: self.lgr.debug('watch pdir address of 0x%x' % page_info.pdir_addr) self.watchPdir(page_info.pdir_addr, prec) else: self.lgr.debug('watch ptable address of 0x%x' % page_info.ptable_addr) self.watchPtable(page_info.ptable_addr, prec) else: self.lgr.debug('pageFaultHap proc %s (%d) gone?' % (comm, pid))
def pageFaultHap(self, compat32, third, forth, memory): if self.fault_hap is None: return #cpu, comm, pid = self.task_utils.curProc() #self.lgr.debug('pageFaultHap pid:%d third: %s forth: %s' % (pid, str(third), str(forth))) #cpu = SIM_current_processor() #if cpu != hap_cpu: # self.lgr.debug('pageFaultHap, wrong cpu %s %s' % (cpu.name, hap_cpu.name)) # return #use_cell = self.cell #if self.debugging_pid is not None: # use_cell = self.context_manager.getRESimContext() cpu, comm, pid = self.task_utils.curProc() eip = self.exception_eip cur_pc = self.mem_utils.getRegValue(cpu, 'pc') if self.cpu.architecture == 'arm': if cur_pc == self.param.page_fault: ''' prefetch abort ''' reg_num = None else: reg_num = self.cpu.iface.int_register.get_number( "combined_data_far") else: reg_num = self.cpu.iface.int_register.get_number("cr2") if reg_num is not None: cr2 = self.cpu.iface.int_register.read(reg_num) else: cr2 = eip if pid not in self.faulted_pages: self.faulted_pages[pid] = [] if cr2 in self.faulted_pages[pid]: self.lgr.debug( 'pageFaultHapAlone, addr 0x%x already handled for pid:%d cur_pc: 0x%x' % (cr2, pid, cur_pc)) return self.faulted_pages[pid].append(cr2) #self.lgr.debug('pageFaultHapAlone for %d (%s) faulting address: 0x%x' % (pid, comm, cr2)) #self.lgr.debug('pageFaultHap for %d (%s) at 0x%x faulting address: 0x%x' % (pid, comm, eip, cr2)) #self.lgr.debug('len of faulted pages is now %d' % len(self.faulted_pages)) if cpu.architecture == 'arm': page_info = pageUtils.findPageTableArm(self.cpu, cr2, self.lgr) elif pageUtils.isIA32E(cpu): page_info = pageUtils.findPageTableIA32E(self.cpu, cr2, self.lgr) else: page_info = pageUtils.findPageTable(self.cpu, cr2, self.lgr) prec = Prec(self.cpu, comm, pid, cr2, eip) if pid not in self.pending_faults: self.pending_faults[pid] = prec #self.lgr.debug('pageFaultHapAlone add pending fault for %d cycle 0x%x' % (pid, prec.cycles)) hack_rec = (compat32, page_info, prec) SIM_run_alone(self.pageFaultHapAlone, hack_rec)