def bench(): # Parameters AXIS_PCIE_DATA_WIDTH = 256 AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) AXIS_PCIE_CQ_USER_WIDTH = 85 AXIS_PCIE_CC_USER_WIDTH = 33 AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH AXI_ADDR_WIDTH = 64 AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8) AXI_ID_WIDTH = 8 AXI_MAX_BURST_LEN = 256 # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) s_axis_cq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]) s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_cq_tvalid = Signal(bool(0)) s_axis_cq_tlast = Signal(bool(0)) s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:]) m_axis_cc_tready = Signal(bool(0)) m_axi_awready = Signal(bool(0)) m_axi_wready = Signal(bool(0)) m_axi_bid = Signal(intbv(0)[AXI_ID_WIDTH:]) m_axi_bresp = Signal(intbv(0)[2:]) m_axi_bvalid = Signal(bool(0)) m_axi_arready = Signal(bool(0)) m_axi_rid = Signal(intbv(0)[AXI_ID_WIDTH:]) m_axi_rdata = Signal(intbv(0)[AXI_DATA_WIDTH:]) m_axi_rresp = Signal(intbv(0)[2:]) m_axi_rlast = Signal(bool(0)) m_axi_rvalid = Signal(bool(0)) completer_id = Signal(intbv(0)[16:]) completer_id_enable = Signal(bool(0)) max_payload_size = Signal(intbv(0)[3:]) # Outputs s_axis_cq_tready = Signal(bool(0)) m_axis_cc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]) m_axis_cc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) m_axis_cc_tvalid = Signal(bool(0)) m_axis_cc_tlast = Signal(bool(0)) m_axis_cc_tuser = Signal(intbv(0)[AXIS_PCIE_CC_USER_WIDTH:]) m_axi_awid = Signal(intbv(0)[AXI_ID_WIDTH:]) m_axi_awaddr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) m_axi_awlen = Signal(intbv(0)[8:]) m_axi_awsize = Signal(intbv(5)[3:]) m_axi_awburst = Signal(intbv(1)[2:]) m_axi_awlock = Signal(bool(0)) m_axi_awcache = Signal(intbv(3)[4:]) m_axi_awprot = Signal(intbv(2)[3:]) m_axi_awvalid = Signal(bool(0)) m_axi_wdata = Signal(intbv(0)[AXI_DATA_WIDTH:]) m_axi_wstrb = Signal(intbv(0)[AXI_STRB_WIDTH:]) m_axi_wlast = Signal(bool(0)) m_axi_wvalid = Signal(bool(0)) m_axi_bready = Signal(bool(0)) m_axi_arid = Signal(intbv(0)[AXI_ID_WIDTH:]) m_axi_araddr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) m_axi_arlen = Signal(intbv(0)[8:]) m_axi_arsize = Signal(intbv(5)[3:]) m_axi_arburst = Signal(intbv(1)[2:]) m_axi_arlock = Signal(bool(0)) m_axi_arcache = Signal(intbv(3)[4:]) m_axi_arprot = Signal(intbv(2)[3:]) m_axi_arvalid = Signal(bool(0)) m_axi_rready = Signal(bool(0)) status_error_cor = Signal(bool(0)) status_error_uncor = Signal(bool(0)) # Clock and Reset Interface user_clk=Signal(bool(0)) user_reset=Signal(bool(0)) sys_clk=Signal(bool(0)) sys_reset=Signal(bool(0)) # AXI4 RAM model axi_ram_inst = axi.AXIRam(2**16) axi_ram_port0 = axi_ram_inst.create_port( user_clk, s_axi_awid=m_axi_awid, s_axi_awaddr=m_axi_awaddr, s_axi_awlen=m_axi_awlen, s_axi_awsize=m_axi_awsize, s_axi_awburst=m_axi_awburst, s_axi_awlock=m_axi_awlock, s_axi_awcache=m_axi_awcache, s_axi_awprot=m_axi_awprot, s_axi_awvalid=m_axi_awvalid, s_axi_awready=m_axi_awready, s_axi_wdata=m_axi_wdata, s_axi_wstrb=m_axi_wstrb, s_axi_wlast=m_axi_wlast, s_axi_wvalid=m_axi_wvalid, s_axi_wready=m_axi_wready, s_axi_bid=m_axi_bid, s_axi_bresp=m_axi_bresp, s_axi_bvalid=m_axi_bvalid, s_axi_bready=m_axi_bready, s_axi_arid=m_axi_arid, s_axi_araddr=m_axi_araddr, s_axi_arlen=m_axi_arlen, s_axi_arsize=m_axi_arsize, s_axi_arburst=m_axi_arburst, s_axi_arlock=m_axi_arlock, s_axi_arcache=m_axi_arcache, s_axi_arprot=m_axi_arprot, s_axi_arvalid=m_axi_arvalid, s_axi_arready=m_axi_arready, s_axi_rid=m_axi_rid, s_axi_rdata=m_axi_rdata, s_axi_rresp=m_axi_rresp, s_axi_rlast=m_axi_rlast, s_axi_rvalid=m_axi_rvalid, s_axi_rready=m_axi_rready, name='port0' ) # PCIe devices rc = pcie.RootComplex() dev = pcie_us.UltrascalePCIe() dev.pcie_generation = 3 dev.pcie_link_width = 8 dev.user_clock_frequency = 250e6 dev.functions[0].configure_bar(0, 16*1024*1024) rc.make_port().connect(dev) pcie_logic = dev.create_logic( # Completer reQuest Interface m_axis_cq_tdata=s_axis_cq_tdata, m_axis_cq_tuser=s_axis_cq_tuser, m_axis_cq_tlast=s_axis_cq_tlast, m_axis_cq_tkeep=s_axis_cq_tkeep, m_axis_cq_tvalid=s_axis_cq_tvalid, m_axis_cq_tready=s_axis_cq_tready, #pcie_cq_np_req=pcie_cq_np_req, #pcie_cq_np_req_count=pcie_cq_np_req_count, # Completer Completion Interface s_axis_cc_tdata=m_axis_cc_tdata, s_axis_cc_tuser=m_axis_cc_tuser, s_axis_cc_tlast=m_axis_cc_tlast, s_axis_cc_tkeep=m_axis_cc_tkeep, s_axis_cc_tvalid=m_axis_cc_tvalid, s_axis_cc_tready=m_axis_cc_tready, # Requester reQuest Interface s_axis_rq_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]), s_axis_rq_tuser=Signal(intbv(0)[60:]), s_axis_rq_tlast=Signal(bool(0)), s_axis_rq_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]), s_axis_rq_tvalid=Signal(bool(0)), s_axis_rq_tready=Signal(bool(1)), # pcie_rq_seq_num=pcie_rq_seq_num, # pcie_rq_seq_num_vld=pcie_rq_seq_num_vld, # pcie_rq_tag=pcie_rq_tag, # pcie_rq_tag_av=pcie_rq_tag_av, # pcie_rq_tag_vld=pcie_rq_tag_vld, # Requester Completion Interface m_axis_rc_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]), m_axis_rc_tuser=Signal(intbv(0)[75:]), m_axis_rc_tlast=Signal(bool(0)), m_axis_rc_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]), m_axis_rc_tvalid=Signal(bool(0)), m_axis_rc_tready=Signal(bool(0)), # Transmit Flow Control Interface # pcie_tfc_nph_av=pcie_tfc_nph_av, # pcie_tfc_npd_av=pcie_tfc_npd_av, # Configuration Control Interface # cfg_hot_reset_in=cfg_hot_reset_in, # cfg_hot_reset_out=cfg_hot_reset_out, # cfg_config_space_enable=cfg_config_space_enable, # cfg_per_function_update_done=cfg_per_function_update_done, # cfg_per_function_number=cfg_per_function_number, # cfg_per_function_output_request=cfg_per_function_output_request, # cfg_dsn=cfg_dsn, # cfg_ds_bus_number=cfg_ds_bus_number, # cfg_ds_device_number=cfg_ds_device_number, # cfg_ds_function_number=cfg_ds_function_number, # cfg_power_state_change_ack=cfg_power_state_change_ack, # cfg_power_state_change_interrupt=cfg_power_state_change_interrupt, # cfg_err_cor_in=cfg_err_cor_in, # cfg_err_uncor_in=cfg_err_uncor_in, # cfg_flr_done=cfg_flr_done, # cfg_vf_flr_done=cfg_vf_flr_done, # cfg_flr_in_process=cfg_flr_in_process, # cfg_vf_flr_in_process=cfg_vf_flr_in_process, # cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready, # cfg_link_training_enable=cfg_link_training_enable, # Clock and Reset Interface user_clk=user_clk, user_reset=user_reset, #user_lnk_up=user_lnk_up, sys_clk=sys_clk, sys_clk_gt=sys_clk, sys_reset=sys_reset ) # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation( "vvp -m myhdl %s.vvp -lxt2" % testbench, clk=user_clk, rst=user_reset, current_test=current_test, s_axis_cq_tdata=s_axis_cq_tdata, s_axis_cq_tkeep=s_axis_cq_tkeep, s_axis_cq_tvalid=s_axis_cq_tvalid, s_axis_cq_tready=s_axis_cq_tready, s_axis_cq_tlast=s_axis_cq_tlast, s_axis_cq_tuser=s_axis_cq_tuser, m_axis_cc_tdata=m_axis_cc_tdata, m_axis_cc_tkeep=m_axis_cc_tkeep, m_axis_cc_tvalid=m_axis_cc_tvalid, m_axis_cc_tready=m_axis_cc_tready, m_axis_cc_tlast=m_axis_cc_tlast, m_axis_cc_tuser=m_axis_cc_tuser, m_axi_awid=m_axi_awid, m_axi_awaddr=m_axi_awaddr, m_axi_awlen=m_axi_awlen, m_axi_awsize=m_axi_awsize, m_axi_awburst=m_axi_awburst, m_axi_awlock=m_axi_awlock, m_axi_awcache=m_axi_awcache, m_axi_awprot=m_axi_awprot, m_axi_awvalid=m_axi_awvalid, m_axi_awready=m_axi_awready, m_axi_wdata=m_axi_wdata, m_axi_wstrb=m_axi_wstrb, m_axi_wlast=m_axi_wlast, m_axi_wvalid=m_axi_wvalid, m_axi_wready=m_axi_wready, m_axi_bid=m_axi_bid, m_axi_bresp=m_axi_bresp, m_axi_bvalid=m_axi_bvalid, m_axi_bready=m_axi_bready, m_axi_arid=m_axi_arid, m_axi_araddr=m_axi_araddr, m_axi_arlen=m_axi_arlen, m_axi_arsize=m_axi_arsize, m_axi_arburst=m_axi_arburst, m_axi_arlock=m_axi_arlock, m_axi_arcache=m_axi_arcache, m_axi_arprot=m_axi_arprot, m_axi_arvalid=m_axi_arvalid, m_axi_arready=m_axi_arready, m_axi_rid=m_axi_rid, m_axi_rdata=m_axi_rdata, m_axi_rresp=m_axi_rresp, m_axi_rlast=m_axi_rlast, m_axi_rvalid=m_axi_rvalid, m_axi_rready=m_axi_rready, completer_id=completer_id, completer_id_enable=completer_id_enable, max_payload_size=max_payload_size, status_error_cor=status_error_cor, status_error_uncor=status_error_uncor ) @always(delay(4)) def clkgen(): clk.next = not clk @always_comb def clk_logic(): sys_clk.next = clk sys_reset.next = not rst status_error_cor_asserted = Signal(bool(0)) status_error_uncor_asserted = Signal(bool(0)) @always(user_clk.posedge) def monitor(): if (status_error_cor): status_error_cor_asserted.next = 1 if (status_error_uncor): status_error_uncor_asserted.next = 1 @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus max_payload_size.next = 0 yield user_clk.posedge print("test 1: enumeration") current_test.next = 1 yield rc.enumerate() dev_bar0 = rc.tree[0][0].bar[0] yield delay(100) yield clk.posedge print("test 2: memory write") current_test.next = 2 pcie_addr = 0x00000000 test_data = b'\x11\x22\x33\x44' yield rc.mem_write(dev_bar0+pcie_addr, test_data) yield delay(300) data = axi_ram_inst.read_mem(pcie_addr, 32) for i in range(0, len(data), 16): print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16])))) assert axi_ram_inst.read_mem(pcie_addr, len(test_data)) == test_data assert not status_error_cor_asserted assert not status_error_uncor_asserted yield delay(100) yield clk.posedge print("test 3: memory read") current_test.next = 3 pcie_addr = 0x00000000 test_data = b'\x11\x22\x33\x44' axi_ram_inst.write_mem(pcie_addr, test_data) data = axi_ram_inst.read_mem(0, 32) for i in range(0, len(data), 16): print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16])))) val = yield from rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000) print(val) assert val == test_data assert not status_error_cor_asserted assert not status_error_uncor_asserted yield delay(100) raise StopSimulation return instances()
def bench(): # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) # Outputs # PCIe devices rc = pcie.RootComplex() ep = TestEP() dev = pcie.Device(ep) rc.make_port().connect(dev) sw = pcie.Switch() rc.make_port().connect(sw) ep2 = TestEP() dev2 = pcie.Device(ep2) sw.make_port().connect(dev2) ep3 = TestEP() dev3 = pcie.Device(ep3) sw.make_port().connect(dev3) ep4 = TestEP() dev4 = pcie.Device(ep4) rc.make_port().connect(dev4) @always(delay(2)) def clkgen(): clk.next = not clk @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge yield clk.posedge print("test 1: enumeration") current_test.next = 1 yield from rc.enumerate(enable_bus_mastering=True, configure_msi=True) # val = yield from rc.config_read((0, 1, 0), 0x000, 4) # print(val) # val = yield from rc.config_read((1, 0, 0), 0x000, 4) # print(val) # yield from rc.config_write((1, 0, 0), 0x010, b'\xff'*4*6) # val = yield from rc.config_read((1, 0, 0), 0x010, 4*6) # print(val) for k in range(6): print("0x%08x / 0x%08x" %(ep.bar[k], ep.bar_mask[k])) print(sw.upstream_bridge.pri_bus_num) print(sw.upstream_bridge.sec_bus_num) print(sw.upstream_bridge.sub_bus_num) print("0x%08x" % sw.upstream_bridge.io_base) print("0x%08x" % sw.upstream_bridge.io_limit) print("0x%08x" % sw.upstream_bridge.mem_base) print("0x%08x" % sw.upstream_bridge.mem_limit) print("0x%016x" % sw.upstream_bridge.prefetchable_mem_base) print("0x%016x" % sw.upstream_bridge.prefetchable_mem_limit) yield delay(100) yield clk.posedge print("test 2: IO and memory read/write") current_test.next = 2 yield from rc.io_write(0x80000000, bytearray(range(16)), 1000) assert ep.read_region(3, 0, 16) == bytearray(range(16)) val = yield from rc.io_read(0x80000000, 16, 1000) assert val == bytearray(range(16)) yield from rc.mem_write(0x80000000, bytearray(range(16)), 1000) yield delay(1000) assert ep.read_region(0, 0, 16) == bytearray(range(16)) val = yield from rc.mem_read(0x80000000, 16, 1000) assert val == bytearray(range(16)) yield from rc.mem_write(0x8000000000000000, bytearray(range(16)), 1000) yield delay(1000) assert ep.read_region(1, 0, 16) == bytearray(range(16)) val = yield from rc.mem_read(0x8000000000000000, 16, 1000) assert val == bytearray(range(16)) yield delay(100) # yield clk.posedge # print("test 3: Large read/write") # current_test.next = 3 # yield from rc.mem_write(0x8000000000000000, bytearray(range(256))*32, 100) # yield delay(1000) # assert ep.read_region(1, 0, 256*32) == bytearray(range(256))*32 # val = yield from rc.mem_read(0x8000000000000000, 256*32, 100) # assert val == bytearray(range(256))*32 # yield delay(100) yield clk.posedge print("test 4: Root complex memory") current_test.next = 4 mem_base, mem_data = rc.alloc_region(1024*1024) io_base, io_data = rc.alloc_io_region(1024) yield from rc.io_write(io_base, bytearray(range(16))) assert io_data[0:16] == bytearray(range(16)) val = yield from rc.io_read(io_base, 16) assert val == bytearray(range(16)) yield from rc.mem_write(mem_base, bytearray(range(16))) assert mem_data[0:16] == bytearray(range(16)) val = yield from rc.mem_read(mem_base, 16) assert val == bytearray(range(16)) yield delay(100) yield clk.posedge print("test 5: device-to-device DMA") current_test.next = 5 yield from ep.io_write(0x80001000, bytearray(range(16)), 10000) assert ep2.read_region(3, 0, 16) == bytearray(range(16)) val = yield from ep.io_read(0x80001000, 16, 10000) assert val == bytearray(range(16)) yield from ep.mem_write(0x80100000, bytearray(range(16)), 10000) yield delay(1000) assert ep2.read_region(0, 0, 16) == bytearray(range(16)) val = yield from ep.mem_read(0x80100000, 16, 10000) assert val == bytearray(range(16)) yield from ep.mem_write(0x8000000000100000, bytearray(range(16)), 10000) yield delay(1000) assert ep2.read_region(1, 0, 16) == bytearray(range(16)) val = yield from ep.mem_read(0x8000000000100000, 16, 10000) assert val == bytearray(range(16)) yield delay(100) yield clk.posedge print("test 6: device-to-root DMA") current_test.next = 6 yield from ep.io_write(io_base, bytearray(range(16)), 1000) assert io_data[0:16] == bytearray(range(16)) val = yield from ep.io_read(io_base, 16, 1000) assert val == bytearray(range(16)) yield from ep.mem_write(mem_base, bytearray(range(16)), 1000) yield delay(1000) assert mem_data[0:16] == bytearray(range(16)) val = yield from ep.mem_read(mem_base, 16, 1000) assert val == bytearray(range(16)) yield delay(100) yield clk.posedge print("test 7: MSI") current_test.next = 7 yield from ep.issue_msi_interrupt(4) yield rc.msi_get_signal(ep.get_id(), 4) yield delay(100) raise StopSimulation return instances()
def bench(): # Parameters AXIS_PCIE_DATA_WIDTH = 256 AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH / 32) AXIS_PCIE_RC_USER_WIDTH = 75 AXIS_PCIE_RQ_USER_WIDTH = 60 AXIS_PCIE_CQ_USER_WIDTH = 85 AXIS_PCIE_CC_USER_WIDTH = 33 # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) clk_156mhz = Signal(bool(0)) rst_156mhz = Signal(bool(0)) clk_250mhz = Signal(bool(0)) rst_250mhz = Signal(bool(0)) m_axis_rq_tready = Signal(bool(0)) s_axis_rc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]) s_axis_rc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_rc_tlast = Signal(bool(0)) s_axis_rc_tuser = Signal(intbv(0)[AXIS_PCIE_RC_USER_WIDTH:]) s_axis_rc_tvalid = Signal(bool(0)) s_axis_cq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]) s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_cq_tlast = Signal(bool(0)) s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:]) s_axis_cq_tvalid = Signal(bool(0)) m_axis_cc_tready = Signal(bool(0)) pcie_tfc_nph_av = Signal(intbv(0)[2:]) pcie_tfc_npd_av = Signal(intbv(0)[2:]) cfg_max_payload = Signal(intbv(0)[3:]) cfg_max_read_req = Signal(intbv(0)[3:]) cfg_mgmt_read_data = Signal(intbv(0)[32:]) cfg_mgmt_read_write_done = Signal(bool(0)) cfg_interrupt_msi_enable = Signal(intbv(0)[4:]) cfg_interrupt_msi_vf_enable = Signal(intbv(0)[8:]) cfg_interrupt_msi_mmenable = Signal(intbv(0)[12:]) cfg_interrupt_msi_mask_update = Signal(bool(0)) cfg_interrupt_msi_data = Signal(intbv(0)[32:]) cfg_interrupt_msi_sent = Signal(bool(0)) cfg_interrupt_msi_fail = Signal(bool(0)) sfp_1_tx_clk = Signal(bool(0)) sfp_1_tx_rst = Signal(bool(0)) sfp_1_rx_clk = Signal(bool(0)) sfp_1_rx_rst = Signal(bool(0)) sfp_1_rxd = Signal(intbv(0)[64:]) sfp_1_rxc = Signal(intbv(0)[8:]) sfp_2_tx_clk = Signal(bool(0)) sfp_2_tx_rst = Signal(bool(0)) sfp_2_rx_clk = Signal(bool(0)) sfp_2_rx_rst = Signal(bool(0)) sfp_2_rxd = Signal(intbv(0)[64:]) sfp_2_rxc = Signal(intbv(0)[8:]) sfp_i2c_scl_i = Signal(bool(1)) sfp_1_i2c_sda_i = Signal(bool(1)) sfp_2_i2c_sda_i = Signal(bool(1)) eeprom_i2c_scl_i = Signal(bool(1)) eeprom_i2c_sda_i = Signal(bool(1)) flash_dq_i = Signal(intbv(0)[16:]) # Outputs sfp_1_led = Signal(intbv(0)[2:]) sfp_2_led = Signal(intbv(0)[2:]) sma_led = Signal(intbv(0)[2:]) m_axis_rq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]) m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) m_axis_rq_tlast = Signal(bool(0)) m_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:]) m_axis_rq_tvalid = Signal(bool(0)) s_axis_rc_tready = Signal(bool(0)) s_axis_cq_tready = Signal(bool(0)) m_axis_cc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]) m_axis_cc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) m_axis_cc_tlast = Signal(bool(0)) m_axis_cc_tuser = Signal(intbv(0)[AXIS_PCIE_CC_USER_WIDTH:]) m_axis_cc_tvalid = Signal(bool(0)) status_error_cor = Signal(bool(0)) status_error_uncor = Signal(bool(0)) cfg_mgmt_addr = Signal(intbv(0)[19:]) cfg_mgmt_write = Signal(bool(0)) cfg_mgmt_write_data = Signal(intbv(0)[32:]) cfg_mgmt_byte_enable = Signal(intbv(0)[4:]) cfg_mgmt_read = Signal(bool(0)) cfg_interrupt_msi_int = Signal(intbv(0)[32:]) cfg_interrupt_msi_pending_status = Signal(intbv(0)[32:]) cfg_interrupt_msi_select = Signal(intbv(0)[4:]) cfg_interrupt_msi_pending_status_function_num = Signal(intbv(0)[4:]) cfg_interrupt_msi_pending_status_data_enable = Signal(bool(0)) cfg_interrupt_msi_attr = Signal(intbv(0)[3:]) cfg_interrupt_msi_tph_present = Signal(bool(0)) cfg_interrupt_msi_tph_type = Signal(intbv(0)[2:]) cfg_interrupt_msi_tph_st_tag = Signal(intbv(0)[9:]) cfg_interrupt_msi_function_number = Signal(intbv(0)[4:]) sfp_1_txd = Signal(intbv(0)[64:]) sfp_1_txc = Signal(intbv(0)[8:]) sfp_2_txd = Signal(intbv(0)[64:]) sfp_2_txc = Signal(intbv(0)[8:]) sfp_i2c_scl_o = Signal(bool(1)) sfp_i2c_scl_t = Signal(bool(1)) sfp_1_i2c_sda_o = Signal(bool(1)) sfp_1_i2c_sda_t = Signal(bool(1)) sfp_2_i2c_sda_o = Signal(bool(1)) sfp_2_i2c_sda_t = Signal(bool(1)) eeprom_i2c_scl_o = Signal(bool(1)) eeprom_i2c_scl_t = Signal(bool(1)) eeprom_i2c_sda_o = Signal(bool(1)) eeprom_i2c_sda_t = Signal(bool(1)) flash_dq_o = Signal(intbv(0)[16:]) flash_dq_oe = Signal(bool(0)) flash_addr = Signal(intbv(0)[23:]) flash_region = Signal(bool(0)) flash_region_oe = Signal(bool(0)) flash_ce_n = Signal(bool(1)) flash_oe_n = Signal(bool(1)) flash_we_n = Signal(bool(1)) flash_adv_n = Signal(bool(1)) # sources and sinks sfp_1_source = xgmii_ep.XGMIISource() sfp_1_source_logic = sfp_1_source.create_logic(sfp_1_rx_clk, sfp_1_rx_rst, txd=sfp_1_rxd, txc=sfp_1_rxc, name='sfp_1_source') sfp_1_sink = xgmii_ep.XGMIISink() sfp_1_sink_logic = sfp_1_sink.create_logic(sfp_1_tx_clk, sfp_1_tx_rst, rxd=sfp_1_txd, rxc=sfp_1_txc, name='sfp_1_sink') sfp_2_source = xgmii_ep.XGMIISource() sfp_2_source_logic = sfp_2_source.create_logic(sfp_2_rx_clk, sfp_2_rx_rst, txd=sfp_2_rxd, txc=sfp_2_rxc, name='sfp_2_source') sfp_2_sink = xgmii_ep.XGMIISink() sfp_2_sink_logic = sfp_2_sink.create_logic(sfp_2_tx_clk, sfp_2_tx_rst, rxd=sfp_2_txd, rxc=sfp_2_txc, name='sfp_2_sink') # Clock and Reset Interface user_clk = Signal(bool(0)) user_reset = Signal(bool(0)) sys_clk = Signal(bool(0)) sys_reset = Signal(bool(0)) # PCIe devices rc = pcie.RootComplex() rc.max_payload_size = 0x1 # 256 bytes rc.max_read_request_size = 0x5 # 4096 bytes driver = mqnic.Driver(rc) dev = pcie_us.UltrascalePCIe() dev.pcie_generation = 3 dev.pcie_link_width = 8 dev.user_clock_frequency = 256e6 dev.functions[0].msi_multiple_message_capable = 5 dev.functions[0].configure_bar(0, 16 * 1024 * 1024) dev.functions[0].configure_bar(1, 16 * 1024 * 1024) rc.make_port().connect(dev) pcie_logic = dev.create_logic( # Completer reQuest Interface m_axis_cq_tdata=s_axis_cq_tdata, m_axis_cq_tuser=s_axis_cq_tuser, m_axis_cq_tlast=s_axis_cq_tlast, m_axis_cq_tkeep=s_axis_cq_tkeep, m_axis_cq_tvalid=s_axis_cq_tvalid, m_axis_cq_tready=s_axis_cq_tready, #pcie_cq_np_req=pcie_cq_np_req, pcie_cq_np_req=Signal(bool(1)), #pcie_cq_np_req_count=pcie_cq_np_req_count, # Completer Completion Interface s_axis_cc_tdata=m_axis_cc_tdata, s_axis_cc_tuser=m_axis_cc_tuser, s_axis_cc_tlast=m_axis_cc_tlast, s_axis_cc_tkeep=m_axis_cc_tkeep, s_axis_cc_tvalid=m_axis_cc_tvalid, s_axis_cc_tready=m_axis_cc_tready, # Requester reQuest Interface s_axis_rq_tdata=m_axis_rq_tdata, s_axis_rq_tuser=m_axis_rq_tuser, s_axis_rq_tlast=m_axis_rq_tlast, s_axis_rq_tkeep=m_axis_rq_tkeep, s_axis_rq_tvalid=m_axis_rq_tvalid, s_axis_rq_tready=m_axis_rq_tready, #pcie_rq_seq_num=pcie_rq_seq_num, #pcie_rq_seq_num_vld=pcie_rq_seq_num_vld, #pcie_rq_tag=pcie_rq_tag, #pcie_rq_tag_vld=pcie_rq_tag_vld, # Requester Completion Interface m_axis_rc_tdata=s_axis_rc_tdata, m_axis_rc_tuser=s_axis_rc_tuser, m_axis_rc_tlast=s_axis_rc_tlast, m_axis_rc_tkeep=s_axis_rc_tkeep, m_axis_rc_tvalid=s_axis_rc_tvalid, m_axis_rc_tready=s_axis_rc_tready, # Transmit Flow Control Interface pcie_tfc_nph_av=pcie_tfc_nph_av, pcie_tfc_npd_av=pcie_tfc_npd_av, # Configuration Management Interface cfg_mgmt_addr=cfg_mgmt_addr, cfg_mgmt_write=cfg_mgmt_write, cfg_mgmt_write_data=cfg_mgmt_write_data, cfg_mgmt_byte_enable=cfg_mgmt_byte_enable, cfg_mgmt_read=cfg_mgmt_read, cfg_mgmt_read_data=cfg_mgmt_read_data, cfg_mgmt_read_write_done=cfg_mgmt_read_write_done, #cfg_mgmt_type1_cfg_reg_access=cfg_mgmt_type1_cfg_reg_access, # Configuration Status Interface #cfg_phy_link_down=cfg_phy_link_down, #cfg_phy_link_status=cfg_phy_link_status, #cfg_negotiated_width=cfg_negotiated_width, #cfg_current_speed=cfg_current_speed, cfg_max_payload=cfg_max_payload, cfg_max_read_req=cfg_max_read_req, #cfg_function_status=cfg_function_status, #cfg_vf_status=cfg_vf_status, #cfg_function_power_state=cfg_function_power_state, #cfg_vf_power_state=cfg_vf_power_state, #cfg_link_power_state=cfg_link_power_state, #cfg_err_cor_out=cfg_err_cor_out, #cfg_err_nonfatal_out=cfg_err_nonfatal_out, #cfg_err_fatal_out=cfg_err_fatal_out, #cfg_ltr_enable=cfg_ltr_enable, #cfg_ltssm_state=cfg_ltssm_state, #cfg_rcb_status=cfg_rcb_status, #cfg_dpa_substate_change=cfg_dpa_substate_change, #cfg_obff_enable=cfg_obff_enable, #cfg_pl_status_change=cfg_pl_status_change, #cfg_tph_requester_enable=cfg_tph_requester_enable, #cfg_tph_st_mode=cfg_tph_st_mode, #cfg_vf_tph_requester_enable=cfg_vf_tph_requester_enable, #cfg_vf_tph_st_mode=cfg_vf_tph_st_mode, # Configuration Received Message Interface #cfg_msg_received=cfg_msg_received, #cfg_msg_received_data=cfg_msg_received_data, #cfg_msg_received_type=cfg_msg_received_type, # Configuration Transmit Message Interface #cfg_msg_transmit=cfg_msg_transmit, #cfg_msg_transmit_type=cfg_msg_transmit_type, #cfg_msg_transmit_data=cfg_msg_transmit_data, #cfg_msg_transmit_done=cfg_msg_transmit_done, # Configuration Flow Control Interface #cfg_fc_ph=cfg_fc_ph, #cfg_fc_pd=cfg_fc_pd, #cfg_fc_nph=cfg_fc_nph, #cfg_fc_npd=cfg_fc_npd, #cfg_fc_cplh=cfg_fc_cplh, #cfg_fc_cpld=cfg_fc_cpld, #cfg_fc_sel=cfg_fc_sel, # Per-Function Status Interface #cfg_per_func_status_control=cfg_per_func_status_control, #cfg_per_func_status_data=cfg_per_func_status_data, # Configuration Control Interface #cfg_hot_reset_in=cfg_hot_reset_in, #cfg_hot_reset_out=cfg_hot_reset_out, #cfg_config_space_enable=cfg_config_space_enable, #cfg_per_function_update_done=cfg_per_function_update_done, #cfg_per_function_number=cfg_per_function_number, #cfg_per_function_output_request=cfg_per_function_output_request, #cfg_dsn=cfg_dsn, #cfg_ds_bus_number=cfg_ds_bus_number, #cfg_ds_device_number=cfg_ds_device_number, #cfg_ds_function_number=cfg_ds_function_number, #cfg_power_state_change_ack=cfg_power_state_change_ack, #cfg_power_state_change_interrupt=cfg_power_state_change_interrupt, cfg_err_cor_in=status_error_cor, cfg_err_uncor_in=status_error_uncor, #cfg_flr_done=cfg_flr_done, #cfg_vf_flr_done=cfg_vf_flr_done, #cfg_flr_in_process=cfg_flr_in_process, #cfg_vf_flr_in_process=cfg_vf_flr_in_process, #cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready, #cfg_link_training_enable=cfg_link_training_enable, # Configuration Interrupt Controller Interface #cfg_interrupt_int=cfg_interrupt_int, #cfg_interrupt_sent=cfg_interrupt_sent, #cfg_interrupt_pending=cfg_interrupt_pending, cfg_interrupt_msi_enable=cfg_interrupt_msi_enable, cfg_interrupt_msi_vf_enable=cfg_interrupt_msi_vf_enable, cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable, cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update, cfg_interrupt_msi_data=cfg_interrupt_msi_data, cfg_interrupt_msi_select=cfg_interrupt_msi_select, cfg_interrupt_msi_int=cfg_interrupt_msi_int, cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status, cfg_interrupt_msi_pending_status_data_enable= cfg_interrupt_msi_pending_status_data_enable, cfg_interrupt_msi_pending_status_function_num= cfg_interrupt_msi_pending_status_function_num, cfg_interrupt_msi_sent=cfg_interrupt_msi_sent, cfg_interrupt_msi_fail=cfg_interrupt_msi_fail, #cfg_interrupt_msix_enable=cfg_interrupt_msix_enable, #cfg_interrupt_msix_mask=cfg_interrupt_msix_mask, #cfg_interrupt_msix_vf_enable=cfg_interrupt_msix_vf_enable, #cfg_interrupt_msix_vf_mask=cfg_interrupt_msix_vf_mask, #cfg_interrupt_msix_address=cfg_interrupt_msix_address, #cfg_interrupt_msix_data=cfg_interrupt_msix_data, #cfg_interrupt_msix_int=cfg_interrupt_msix_int, #cfg_interrupt_msix_sent=cfg_interrupt_msix_sent, #cfg_interrupt_msix_fail=cfg_interrupt_msix_fail, cfg_interrupt_msi_attr=cfg_interrupt_msi_attr, cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag, cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number, # Configuration Extend Interface #cfg_ext_read_received=cfg_ext_read_received, #cfg_ext_write_received=cfg_ext_write_received, #cfg_ext_register_number=cfg_ext_register_number, #cfg_ext_function_number=cfg_ext_function_number, #cfg_ext_write_data=cfg_ext_write_data, #cfg_ext_write_byte_enable=cfg_ext_write_byte_enable, #cfg_ext_read_data=cfg_ext_read_data, #cfg_ext_read_data_valid=cfg_ext_read_data_valid, # Clock and Reset Interface user_clk=user_clk, user_reset=user_reset, sys_clk=sys_clk, sys_clk_gt=sys_clk, sys_reset=sys_reset, #pcie_perstn0_out=pcie_perstn0_out, #pcie_perstn1_in=pcie_perstn1_in, #pcie_perstn1_out=pcie_perstn1_out ) # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation( "vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, clk_156mhz=clk_156mhz, rst_156mhz=rst_156mhz, clk_250mhz=user_clk, rst_250mhz=user_reset, sfp_1_led=sfp_1_led, sfp_2_led=sfp_2_led, sma_led=sma_led, m_axis_rq_tdata=m_axis_rq_tdata, m_axis_rq_tkeep=m_axis_rq_tkeep, m_axis_rq_tlast=m_axis_rq_tlast, m_axis_rq_tready=m_axis_rq_tready, m_axis_rq_tuser=m_axis_rq_tuser, m_axis_rq_tvalid=m_axis_rq_tvalid, s_axis_rc_tdata=s_axis_rc_tdata, s_axis_rc_tkeep=s_axis_rc_tkeep, s_axis_rc_tlast=s_axis_rc_tlast, s_axis_rc_tready=s_axis_rc_tready, s_axis_rc_tuser=s_axis_rc_tuser, s_axis_rc_tvalid=s_axis_rc_tvalid, s_axis_cq_tdata=s_axis_cq_tdata, s_axis_cq_tkeep=s_axis_cq_tkeep, s_axis_cq_tlast=s_axis_cq_tlast, s_axis_cq_tready=s_axis_cq_tready, s_axis_cq_tuser=s_axis_cq_tuser, s_axis_cq_tvalid=s_axis_cq_tvalid, m_axis_cc_tdata=m_axis_cc_tdata, m_axis_cc_tkeep=m_axis_cc_tkeep, m_axis_cc_tlast=m_axis_cc_tlast, m_axis_cc_tready=m_axis_cc_tready, m_axis_cc_tuser=m_axis_cc_tuser, m_axis_cc_tvalid=m_axis_cc_tvalid, pcie_tfc_nph_av=pcie_tfc_nph_av, pcie_tfc_npd_av=pcie_tfc_npd_av, cfg_max_payload=cfg_max_payload, cfg_max_read_req=cfg_max_read_req, cfg_mgmt_addr=cfg_mgmt_addr, cfg_mgmt_write=cfg_mgmt_write, cfg_mgmt_write_data=cfg_mgmt_write_data, cfg_mgmt_byte_enable=cfg_mgmt_byte_enable, cfg_mgmt_read=cfg_mgmt_read, cfg_mgmt_read_data=cfg_mgmt_read_data, cfg_mgmt_read_write_done=cfg_mgmt_read_write_done, cfg_interrupt_msi_enable=cfg_interrupt_msi_enable, cfg_interrupt_msi_vf_enable=cfg_interrupt_msi_vf_enable, cfg_interrupt_msi_int=cfg_interrupt_msi_int, cfg_interrupt_msi_sent=cfg_interrupt_msi_sent, cfg_interrupt_msi_fail=cfg_interrupt_msi_fail, cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable, cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status, cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update, cfg_interrupt_msi_select=cfg_interrupt_msi_select, cfg_interrupt_msi_data=cfg_interrupt_msi_data, cfg_interrupt_msi_pending_status_function_num= cfg_interrupt_msi_pending_status_function_num, cfg_interrupt_msi_pending_status_data_enable= cfg_interrupt_msi_pending_status_data_enable, cfg_interrupt_msi_attr=cfg_interrupt_msi_attr, cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag, cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number, status_error_cor=status_error_cor, status_error_uncor=status_error_uncor, sfp_1_tx_clk=sfp_1_tx_clk, sfp_1_tx_rst=sfp_1_tx_rst, sfp_1_txd=sfp_1_txd, sfp_1_txc=sfp_1_txc, sfp_1_rx_clk=sfp_1_rx_clk, sfp_1_rx_rst=sfp_1_rx_rst, sfp_1_rxd=sfp_1_rxd, sfp_1_rxc=sfp_1_rxc, sfp_2_tx_clk=sfp_2_tx_clk, sfp_2_tx_rst=sfp_2_tx_rst, sfp_2_txd=sfp_2_txd, sfp_2_txc=sfp_2_txc, sfp_2_rx_clk=sfp_2_rx_clk, sfp_2_rx_rst=sfp_2_rx_rst, sfp_2_rxd=sfp_2_rxd, sfp_2_rxc=sfp_2_rxc, sfp_i2c_scl_i=sfp_i2c_scl_i, sfp_i2c_scl_o=sfp_i2c_scl_o, sfp_i2c_scl_t=sfp_i2c_scl_t, sfp_1_i2c_sda_i=sfp_1_i2c_sda_i, sfp_1_i2c_sda_o=sfp_1_i2c_sda_o, sfp_1_i2c_sda_t=sfp_1_i2c_sda_t, sfp_2_i2c_sda_i=sfp_2_i2c_sda_i, sfp_2_i2c_sda_o=sfp_2_i2c_sda_o, sfp_2_i2c_sda_t=sfp_2_i2c_sda_t, eeprom_i2c_scl_i=eeprom_i2c_scl_i, eeprom_i2c_scl_o=eeprom_i2c_scl_o, eeprom_i2c_scl_t=eeprom_i2c_scl_t, eeprom_i2c_sda_i=eeprom_i2c_sda_i, eeprom_i2c_sda_o=eeprom_i2c_sda_o, eeprom_i2c_sda_t=eeprom_i2c_sda_t, flash_dq_i=flash_dq_i, flash_dq_o=flash_dq_o, flash_dq_oe=flash_dq_oe, flash_addr=flash_addr, flash_region=flash_region, flash_region_oe=flash_region_oe, flash_ce_n=flash_ce_n, flash_oe_n=flash_oe_n, flash_we_n=flash_we_n, flash_adv_n=flash_adv_n) @always(delay(5)) def clkgen(): clk.next = not clk @always_comb def clk_logic(): sys_clk.next = clk sys_reset.next = not rst sfp_1_tx_clk.next = clk sfp_1_tx_rst.next = rst sfp_1_rx_clk.next = clk sfp_1_rx_rst.next = rst sfp_2_tx_clk.next = clk sfp_2_tx_rst.next = rst sfp_2_rx_clk.next = clk sfp_2_rx_rst.next = rst loopback_enable = Signal(bool(0)) @instance def loopback(): while True: yield clk.posedge if loopback_enable: if not sfp_1_sink.empty(): pkt = sfp_1_sink.recv() sfp_1_source.send(pkt) if not sfp_2_sink.empty(): pkt = sfp_2_sink.recv() sfp_2_source.send(pkt) @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus current_tag = 1 yield clk.posedge print("test 1: enumeration") current_test.next = 1 yield rc.enumerate(enable_bus_mastering=True, configure_msi=True) dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc yield from rc.mem_write_dword(dev_pf0_bar0 + 0x270, 0) yield from rc.mem_write_dword(dev_pf0_bar0 + 0x274, 0) yield from rc.mem_write_dword(dev_pf0_bar0 + 0x278, 0) yield from rc.mem_write_dword(dev_pf0_bar0 + 0x27C, 0) yield from rc.mem_write_dword(dev_pf0_bar0 + 0x290, 0) yield from rc.mem_write_dword(dev_pf0_bar0 + 0x294, 1000) yield from rc.mem_write_dword(dev_pf0_bar0 + 0x298, 0) yield from rc.mem_write_dword(dev_pf0_bar0 + 0x29C, 0) yield from rc.mem_write_dword(dev_pf0_bar0 + 0x280, 0) yield from rc.mem_write_dword(dev_pf0_bar0 + 0x284, 2000) yield from rc.mem_write_dword(dev_pf0_bar0 + 0x288, 0) yield from rc.mem_write_dword(dev_pf0_bar0 + 0x28C, 0) yield delay(100) yield clk.posedge print("test 2: init NIC") current_test.next = 2 yield from driver.init_dev(dev.functions[0].get_id()) yield from driver.interfaces[0].open() # enable queues yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0200, 0xffffffff) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0300, 0xffffffff) yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete yield delay(100) yield clk.posedge print("test 3: send and receive a packet") current_test.next = 3 data = bytearray([x % 256 for x in range(1024)]) yield from driver.interfaces[0].start_xmit(data, 0) yield sfp_1_sink.wait() pkt = sfp_1_sink.recv() print(pkt) sfp_1_source.send(pkt) yield driver.interfaces[0].wait() pkt = driver.interfaces[0].recv() print(pkt) yield delay(100) yield clk.posedge print("test 4: checksum tests") current_test.next = 4 test_frame = udp_ep.UDPFrame() test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame.eth_src_mac = 0x5A5152535455 test_frame.eth_type = 0x0800 test_frame.ip_version = 4 test_frame.ip_ihl = 5 test_frame.ip_length = None test_frame.ip_identification = 0 test_frame.ip_flags = 2 test_frame.ip_fragment_offset = 0 test_frame.ip_ttl = 64 test_frame.ip_protocol = 0x11 test_frame.ip_header_checksum = None test_frame.ip_source_ip = 0xc0a80164 test_frame.ip_dest_ip = 0xc0a80165 test_frame.udp_source_port = 1 test_frame.udp_dest_port = 2 test_frame.udp_length = None test_frame.udp_checksum = None test_frame.payload = bytearray((x % 256 for x in range(256))) test_frame.set_udp_pseudo_header_checksum() axis_frame = test_frame.build_axis() yield from driver.interfaces[0].start_xmit(axis_frame.data, 0, 34, 6) yield sfp_1_sink.wait() pkt = sfp_1_sink.recv() print(pkt) sfp_1_source.send(pkt) yield driver.interfaces[0].wait() pkt = driver.interfaces[0].recv() print(pkt) assert pkt.rx_checksum == frame_checksum(pkt.data) check_frame = udp_ep.UDPFrame() check_frame.parse_axis(pkt.data) assert check_frame.verify_checksums() yield delay(100) yield clk.posedge print("test 5: multiple small packets") current_test.next = 5 count = 64 pkts = [ bytearray([(x + k) % 256 for x in range(64)]) for k in range(count) ] loopback_enable.next = True for p in pkts: yield from driver.interfaces[0].start_xmit(p, 0) for k in range(count): pkt = driver.interfaces[0].recv() if not pkt: yield driver.interfaces[0].wait() pkt = driver.interfaces[0].recv() print(pkt) assert pkt.data == pkts[k] assert frame_checksum(pkt.data) == pkt.rx_checksum loopback_enable.next = False yield delay(100) yield clk.posedge print("test 6: multiple large packets") current_test.next = 6 count = 64 pkts = [ bytearray([(x + k) % 256 for x in range(1514)]) for k in range(count) ] loopback_enable.next = True for p in pkts: yield from driver.interfaces[0].start_xmit(p, 0) for k in range(count): pkt = driver.interfaces[0].recv() if not pkt: yield driver.interfaces[0].wait() pkt = driver.interfaces[0].recv() print(pkt) assert pkt.data == pkts[k] assert frame_checksum(pkt.data) == pkt.rx_checksum loopback_enable.next = False yield delay(1000) yield clk.posedge print("test 7: TDMA") current_test.next = 7 count = 16 pkts = [ bytearray([(x + k) % 256 for x in range(1514)]) for k in range(count) ] loopback_enable.next = True # configure TDMA # configure TDMA scheduler yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00120, 0) # schedule period fns yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00124, 40000) # schedule period ns yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00128, 0) # schedule period sec (low) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0012c, 0) # schedule period sec (high) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00130, 0) # timeslot period fns yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00134, 10000) # timeslot period ns yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00138, 0) # timeslot period sec (low) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0013c, 0) # timeslot period sec (high) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00140, 0) # active period fns yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00144, 5000) # active period ns yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00148, 0) # active period sec (low) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0014c, 0) # active period sec (high) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00110, 0) # schedule start fns yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00114, 200000) # schedule start ns yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00118, 0) # schedule start sec (low) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0011c, 0) # schedule start sec (high) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00100, 0x00000001) # enable queues yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00200, 0xffffffff) # disable global enable yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00300, 0x00000000) # configure slots yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x10000, 0x00000001) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x10100, 0x00000002) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x10200, 0x00000004) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x10300, 0x00000008) yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete # send packets for k in range(count): yield from driver.interfaces[0].start_xmit(pkts[k], k % 4) for k in range(count): pkt = driver.interfaces[0].recv() if not pkt: yield driver.interfaces[0].wait() pkt = driver.interfaces[0].recv() print(pkt) #assert pkt.data == pkts[k] #assert frame_checksum(pkt.data) == pkt.rx_checksum loopback_enable.next = False yield delay(100) raise StopSimulation return instances()
def bench(): # Parameters # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) clk_156mhz = Signal(bool(0)) rst_156mhz = Signal(bool(0)) clk_250mhz = Signal(bool(0)) rst_250mhz = Signal(bool(0)) user_sw = Signal(intbv(0)[2:]) m_axis_rq_tready = Signal(bool(0)) s_axis_rc_tdata = Signal(intbv(0)[256:]) s_axis_rc_tkeep = Signal(intbv(0)[8:]) s_axis_rc_tlast = Signal(bool(0)) s_axis_rc_tuser = Signal(intbv(0)[75:]) s_axis_rc_tvalid = Signal(bool(0)) s_axis_cq_tdata = Signal(intbv(0)[256:]) s_axis_cq_tkeep = Signal(intbv(0)[8:]) s_axis_cq_tlast = Signal(bool(0)) s_axis_cq_tuser = Signal(intbv(0)[88:]) s_axis_cq_tvalid = Signal(bool(0)) m_axis_cc_tready = Signal(bool(0)) pcie_tfc_nph_av = Signal(intbv(15)[4:]) pcie_tfc_npd_av = Signal(intbv(15)[4:]) cfg_max_payload = Signal(intbv(0)[2:]) cfg_max_read_req = Signal(intbv(0)[3:]) cfg_mgmt_read_data = Signal(intbv(0)[32:]) cfg_mgmt_read_write_done = Signal(bool(0)) cfg_interrupt_msi_enable = Signal(intbv(0)[4:]) cfg_interrupt_msi_mmenable = Signal(intbv(0)[12:]) cfg_interrupt_msi_mask_update = Signal(bool(0)) cfg_interrupt_msi_data = Signal(intbv(0)[32:]) cfg_interrupt_msi_sent = Signal(bool(0)) cfg_interrupt_msi_fail = Signal(bool(0)) qsfp_0_tx_clk_0 = Signal(bool(0)) qsfp_0_tx_rst_0 = Signal(bool(0)) qsfp_0_rx_clk_0 = Signal(bool(0)) qsfp_0_rx_rst_0 = Signal(bool(0)) qsfp_0_rxd_0 = Signal(intbv(0)[64:]) qsfp_0_rxc_0 = Signal(intbv(0)[8:]) qsfp_0_tx_clk_1 = Signal(bool(0)) qsfp_0_tx_rst_1 = Signal(bool(0)) qsfp_0_rx_clk_1 = Signal(bool(0)) qsfp_0_rx_rst_1 = Signal(bool(0)) qsfp_0_rxd_1 = Signal(intbv(0)[64:]) qsfp_0_rxc_1 = Signal(intbv(0)[8:]) qsfp_0_tx_clk_2 = Signal(bool(0)) qsfp_0_tx_rst_2 = Signal(bool(0)) qsfp_0_rx_clk_2 = Signal(bool(0)) qsfp_0_rx_rst_2 = Signal(bool(0)) qsfp_0_rxd_2 = Signal(intbv(0)[64:]) qsfp_0_rxc_2 = Signal(intbv(0)[8:]) qsfp_0_tx_clk_3 = Signal(bool(0)) qsfp_0_tx_rst_3 = Signal(bool(0)) qsfp_0_rx_clk_3 = Signal(bool(0)) qsfp_0_rx_rst_3 = Signal(bool(0)) qsfp_0_rxd_3 = Signal(intbv(0)[64:]) qsfp_0_rxc_3 = Signal(intbv(0)[8:]) qsfp_0_modprs_l = Signal(bool(0)) qsfp_1_tx_clk_0 = Signal(bool(0)) qsfp_1_tx_rst_0 = Signal(bool(0)) qsfp_1_rx_clk_0 = Signal(bool(0)) qsfp_1_rx_rst_0 = Signal(bool(0)) qsfp_1_rxd_0 = Signal(intbv(0)[64:]) qsfp_1_rxc_0 = Signal(intbv(0)[8:]) qsfp_1_tx_clk_1 = Signal(bool(0)) qsfp_1_tx_rst_1 = Signal(bool(0)) qsfp_1_rx_clk_1 = Signal(bool(0)) qsfp_1_rx_rst_1 = Signal(bool(0)) qsfp_1_rxd_1 = Signal(intbv(0)[64:]) qsfp_1_rxc_1 = Signal(intbv(0)[8:]) qsfp_1_tx_clk_2 = Signal(bool(0)) qsfp_1_tx_rst_2 = Signal(bool(0)) qsfp_1_rx_clk_2 = Signal(bool(0)) qsfp_1_rx_rst_2 = Signal(bool(0)) qsfp_1_rxd_2 = Signal(intbv(0)[64:]) qsfp_1_rxc_2 = Signal(intbv(0)[8:]) qsfp_1_tx_clk_3 = Signal(bool(0)) qsfp_1_tx_rst_3 = Signal(bool(0)) qsfp_1_rx_clk_3 = Signal(bool(0)) qsfp_1_rx_rst_3 = Signal(bool(0)) qsfp_1_rxd_3 = Signal(intbv(0)[64:]) qsfp_1_rxc_3 = Signal(intbv(0)[8:]) qsfp_1_modprs_l = Signal(bool(0)) qsfp_int_l = Signal(bool(0)) qsfp_i2c_scl_i = Signal(bool(1)) qsfp_i2c_sda_i = Signal(bool(1)) eeprom_i2c_scl_i = Signal(bool(1)) eeprom_i2c_sda_i = Signal(bool(1)) # Outputs user_led_g = Signal(intbv(0)[2:]) user_led_r = Signal(bool(0)) front_led = Signal(intbv(0)[2:]) m_axis_rq_tdata = Signal(intbv(0)[256:]) m_axis_rq_tkeep = Signal(intbv(0)[8:]) m_axis_rq_tlast = Signal(bool(0)) m_axis_rq_tuser = Signal(intbv(0)[62:]) m_axis_rq_tvalid = Signal(bool(0)) s_axis_rc_tready = Signal(bool(0)) s_axis_cq_tready = Signal(bool(0)) m_axis_cc_tdata = Signal(intbv(0)[256:]) m_axis_cc_tkeep = Signal(intbv(0)[8:]) m_axis_cc_tlast = Signal(bool(0)) m_axis_cc_tuser = Signal(intbv(0)[33:]) m_axis_cc_tvalid = Signal(bool(0)) status_error_cor = Signal(bool(0)) status_error_uncor = Signal(bool(0)) cfg_mgmt_addr = Signal(intbv(0)[10:]) cfg_mgmt_function_number = Signal(intbv(0)[8:]) cfg_mgmt_write = Signal(bool(0)) cfg_mgmt_write_data = Signal(intbv(0)[32:]) cfg_mgmt_byte_enable = Signal(intbv(0)[4:]) cfg_mgmt_read = Signal(bool(0)) cfg_interrupt_msi_int = Signal(intbv(0)[32:]) cfg_interrupt_msi_pending_status = Signal(intbv(0)[32:]) cfg_interrupt_msi_select = Signal(intbv(0)[2:]) cfg_interrupt_msi_pending_status_function_num = Signal(intbv(0)[2:]) cfg_interrupt_msi_pending_status_data_enable = Signal(bool(0)) cfg_interrupt_msi_attr = Signal(intbv(0)[3:]) cfg_interrupt_msi_tph_present = Signal(bool(0)) cfg_interrupt_msi_tph_type = Signal(intbv(0)[2:]) cfg_interrupt_msi_tph_st_tag = Signal(intbv(0)[8:]) cfg_interrupt_msi_function_number = Signal(intbv(0)[8:]) qsfp_0_txd_0 = Signal(intbv(0)[64:]) qsfp_0_txc_0 = Signal(intbv(0)[8:]) qsfp_0_txd_1 = Signal(intbv(0)[64:]) qsfp_0_txc_1 = Signal(intbv(0)[8:]) qsfp_0_txd_2 = Signal(intbv(0)[64:]) qsfp_0_txc_2 = Signal(intbv(0)[8:]) qsfp_0_txd_3 = Signal(intbv(0)[64:]) qsfp_0_txc_3 = Signal(intbv(0)[8:]) qsfp_0_sel_l = Signal(bool(1)) qsfp_1_txd_0 = Signal(intbv(0)[64:]) qsfp_1_txc_0 = Signal(intbv(0)[8:]) qsfp_1_txd_1 = Signal(intbv(0)[64:]) qsfp_1_txc_1 = Signal(intbv(0)[8:]) qsfp_1_txd_2 = Signal(intbv(0)[64:]) qsfp_1_txc_2 = Signal(intbv(0)[8:]) qsfp_1_txd_3 = Signal(intbv(0)[64:]) qsfp_1_txc_3 = Signal(intbv(0)[8:]) qsfp_1_sel_l = Signal(bool(1)) qsfp_reset_l = Signal(bool(1)) qsfp_i2c_scl_o = Signal(bool(1)) qsfp_i2c_scl_t = Signal(bool(1)) qsfp_i2c_sda_o = Signal(bool(1)) qsfp_i2c_sda_t = Signal(bool(1)) eeprom_i2c_scl_o = Signal(bool(1)) eeprom_i2c_scl_t = Signal(bool(1)) eeprom_i2c_sda_o = Signal(bool(1)) eeprom_i2c_sda_t = Signal(bool(1)) eeprom_wp = Signal(bool(1)) # sources and sinks qsfp_0_0_source = xgmii_ep.XGMIISource() qsfp_0_0_source_logic = qsfp_0_0_source.create_logic( qsfp_0_rx_clk_0, qsfp_0_rx_rst_0, txd=qsfp_0_rxd_0, txc=qsfp_0_rxc_0, name='qsfp_0_0_source') qsfp_0_0_sink = xgmii_ep.XGMIISink() qsfp_0_0_sink_logic = qsfp_0_0_sink.create_logic(qsfp_0_tx_clk_0, qsfp_0_tx_rst_0, rxd=qsfp_0_txd_0, rxc=qsfp_0_txc_0, name='qsfp_0_0_sink') qsfp_0_1_source = xgmii_ep.XGMIISource() qsfp_0_1_source_logic = qsfp_0_1_source.create_logic( qsfp_0_rx_clk_1, qsfp_0_rx_rst_1, txd=qsfp_0_rxd_1, txc=qsfp_0_rxc_1, name='qsfp_0_1_source') qsfp_0_1_sink = xgmii_ep.XGMIISink() qsfp_0_1_sink_logic = qsfp_0_1_sink.create_logic(qsfp_0_tx_clk_1, qsfp_0_tx_rst_1, rxd=qsfp_0_txd_1, rxc=qsfp_0_txc_1, name='qsfp_0_1_sink') qsfp_0_2_source = xgmii_ep.XGMIISource() qsfp_0_2_source_logic = qsfp_0_2_source.create_logic( qsfp_0_rx_clk_2, qsfp_0_rx_rst_2, txd=qsfp_0_rxd_2, txc=qsfp_0_rxc_2, name='qsfp_0_2_source') qsfp_0_2_sink = xgmii_ep.XGMIISink() qsfp_0_2_sink_logic = qsfp_0_2_sink.create_logic(qsfp_0_tx_clk_2, qsfp_0_tx_rst_2, rxd=qsfp_0_txd_2, rxc=qsfp_0_txc_2, name='qsfp_0_2_sink') qsfp_0_3_source = xgmii_ep.XGMIISource() qsfp_0_3_source_logic = qsfp_0_3_source.create_logic( qsfp_0_rx_clk_3, qsfp_0_rx_rst_3, txd=qsfp_0_rxd_3, txc=qsfp_0_rxc_3, name='qsfp_0_3_source') qsfp_0_3_sink = xgmii_ep.XGMIISink() qsfp_0_3_sink_logic = qsfp_0_3_sink.create_logic(qsfp_0_tx_clk_3, qsfp_0_tx_rst_3, rxd=qsfp_0_txd_3, rxc=qsfp_0_txc_3, name='qsfp_0_3_sink') qsfp_1_0_source = xgmii_ep.XGMIISource() qsfp_1_0_source_logic = qsfp_1_0_source.create_logic( qsfp_1_rx_clk_0, qsfp_1_rx_rst_0, txd=qsfp_1_rxd_0, txc=qsfp_1_rxc_0, name='qsfp_1_0_source') qsfp_1_0_sink = xgmii_ep.XGMIISink() qsfp_1_0_sink_logic = qsfp_1_0_sink.create_logic(qsfp_1_tx_clk_0, qsfp_1_tx_rst_0, rxd=qsfp_1_txd_0, rxc=qsfp_1_txc_0, name='qsfp_1_0_sink') qsfp_1_1_source = xgmii_ep.XGMIISource() qsfp_1_1_source_logic = qsfp_1_1_source.create_logic( qsfp_1_rx_clk_1, qsfp_1_rx_rst_1, txd=qsfp_1_rxd_1, txc=qsfp_1_rxc_1, name='qsfp_1_1_source') qsfp_1_1_sink = xgmii_ep.XGMIISink() qsfp_1_1_sink_logic = qsfp_1_1_sink.create_logic(qsfp_1_tx_clk_1, qsfp_1_tx_rst_1, rxd=qsfp_1_txd_1, rxc=qsfp_1_txc_1, name='qsfp_1_1_sink') qsfp_1_2_source = xgmii_ep.XGMIISource() qsfp_1_2_source_logic = qsfp_1_2_source.create_logic( qsfp_1_rx_clk_2, qsfp_1_rx_rst_2, txd=qsfp_1_rxd_2, txc=qsfp_1_rxc_2, name='qsfp_1_2_source') qsfp_1_2_sink = xgmii_ep.XGMIISink() qsfp_1_2_sink_logic = qsfp_1_2_sink.create_logic(qsfp_1_tx_clk_2, qsfp_1_tx_rst_2, rxd=qsfp_1_txd_2, rxc=qsfp_1_txc_2, name='qsfp_1_2_sink') qsfp_1_3_source = xgmii_ep.XGMIISource() qsfp_1_3_source_logic = qsfp_1_3_source.create_logic( qsfp_1_rx_clk_3, qsfp_1_rx_rst_3, txd=qsfp_1_rxd_3, txc=qsfp_1_rxc_3, name='qsfp_1_3_source') qsfp_1_3_sink = xgmii_ep.XGMIISink() qsfp_1_3_sink_logic = qsfp_1_3_sink.create_logic(qsfp_1_tx_clk_3, qsfp_1_tx_rst_3, rxd=qsfp_1_txd_3, rxc=qsfp_1_txc_3, name='qsfp_1_3_sink') # Clock and Reset Interface user_clk = Signal(bool(0)) user_reset = Signal(bool(0)) sys_clk = Signal(bool(0)) sys_reset = Signal(bool(0)) # PCIe devices rc = pcie.RootComplex() rc.max_payload_size = 0x1 # 256 bytes rc.max_read_request_size = 0x5 # 4096 bytes driver = mqnic.Driver(rc) dev = pcie_usp.UltrascalePlusPCIe() dev.pcie_generation = 3 dev.pcie_link_width = 8 dev.user_clock_frequency = 256e6 dev.functions[0].msi_multiple_message_capable = 5 dev.functions[0].configure_bar(0, 16 * 1024 * 1024) dev.functions[0].configure_bar(1, 16 * 1024 * 1024) rc.make_port().connect(dev) cq_pause = Signal(bool(0)) cc_pause = Signal(bool(0)) rq_pause = Signal(bool(0)) rc_pause = Signal(bool(0)) pcie_logic = dev.create_logic( # Completer reQuest Interface m_axis_cq_tdata=s_axis_cq_tdata, m_axis_cq_tuser=s_axis_cq_tuser, m_axis_cq_tlast=s_axis_cq_tlast, m_axis_cq_tkeep=s_axis_cq_tkeep, m_axis_cq_tvalid=s_axis_cq_tvalid, m_axis_cq_tready=s_axis_cq_tready, #pcie_cq_np_req=pcie_cq_np_req, pcie_cq_np_req=Signal(intbv(3)[2:]), #pcie_cq_np_req_count=pcie_cq_np_req_count, # Completer Completion Interface s_axis_cc_tdata=m_axis_cc_tdata, s_axis_cc_tuser=m_axis_cc_tuser, s_axis_cc_tlast=m_axis_cc_tlast, s_axis_cc_tkeep=m_axis_cc_tkeep, s_axis_cc_tvalid=m_axis_cc_tvalid, s_axis_cc_tready=m_axis_cc_tready, # Requester reQuest Interface s_axis_rq_tdata=m_axis_rq_tdata, s_axis_rq_tuser=m_axis_rq_tuser, s_axis_rq_tlast=m_axis_rq_tlast, s_axis_rq_tkeep=m_axis_rq_tkeep, s_axis_rq_tvalid=m_axis_rq_tvalid, s_axis_rq_tready=m_axis_rq_tready, #pcie_rq_seq_num0=pcie_rq_seq_num0, #pcie_rq_seq_num_vld0=pcie_rq_seq_num_vld0, #pcie_rq_seq_num1=pcie_rq_seq_num1, #pcie_rq_seq_num_vld1=pcie_rq_seq_num_vld1, #pcie_rq_tag0=pcie_rq_tag0, #pcie_rq_tag1=pcie_rq_tag1, #pcie_rq_tag_av=pcie_rq_tag_av, #pcie_rq_tag_vld0=pcie_rq_tag_vld0, #pcie_rq_tag_vld1=pcie_rq_tag_vld1, # Requester Completion Interface m_axis_rc_tdata=s_axis_rc_tdata, m_axis_rc_tuser=s_axis_rc_tuser, m_axis_rc_tlast=s_axis_rc_tlast, m_axis_rc_tkeep=s_axis_rc_tkeep, m_axis_rc_tvalid=s_axis_rc_tvalid, m_axis_rc_tready=s_axis_rc_tready, # Transmit Flow Control Interface #pcie_tfc_nph_av=pcie_tfc_nph_av, #pcie_tfc_npd_av=pcie_tfc_npd_av, # Configuration Management Interface cfg_mgmt_addr=cfg_mgmt_addr, cfg_mgmt_function_number=cfg_mgmt_function_number, cfg_mgmt_write=cfg_mgmt_write, cfg_mgmt_write_data=cfg_mgmt_write_data, cfg_mgmt_byte_enable=cfg_mgmt_byte_enable, cfg_mgmt_read=cfg_mgmt_read, cfg_mgmt_read_data=cfg_mgmt_read_data, cfg_mgmt_read_write_done=cfg_mgmt_read_write_done, #cfg_mgmt_debug_access=cfg_mgmt_debug_access, # Configuration Status Interface #cfg_phy_link_down=cfg_phy_link_down, #cfg_phy_link_status=cfg_phy_link_status, #cfg_negotiated_width=cfg_negotiated_width, #cfg_current_speed=cfg_current_speed, cfg_max_payload=cfg_max_payload, cfg_max_read_req=cfg_max_read_req, #cfg_function_status=cfg_function_status, #cfg_vf_status=cfg_vf_status, #cfg_function_power_state=cfg_function_power_state, #cfg_vf_power_state=cfg_vf_power_state, #cfg_link_power_state=cfg_link_power_state, #cfg_err_cor_out=cfg_err_cor_out, #cfg_err_nonfatal_out=cfg_err_nonfatal_out, #cfg_err_fatal_out=cfg_err_fatal_out, #cfg_local_err_out=cfg_local_err_out, #cfg_local_err_valid=cfg_local_err_valid, #cfg_rx_pm_state=cfg_rx_pm_state, #cfg_tx_pm_state=cfg_tx_pm_state, #cfg_ltssm_state=cfg_ltssm_state, #cfg_rcb_status=cfg_rcb_status, #cfg_obff_enable=cfg_obff_enable, #cfg_pl_status_change=cfg_pl_status_change, #cfg_tph_requester_enable=cfg_tph_requester_enable, #cfg_tph_st_mode=cfg_tph_st_mode, #cfg_vf_tph_requester_enable=cfg_vf_tph_requester_enable, #cfg_vf_tph_st_mode=cfg_vf_tph_st_mode, # Configuration Received Message Interface #cfg_msg_received=cfg_msg_received, #cfg_msg_received_data=cfg_msg_received_data, #cfg_msg_received_type=cfg_msg_received_type, # Configuration Transmit Message Interface #cfg_msg_transmit=cfg_msg_transmit, #cfg_msg_transmit_type=cfg_msg_transmit_type, #cfg_msg_transmit_data=cfg_msg_transmit_data, #cfg_msg_transmit_done=cfg_msg_transmit_done, # Configuration Flow Control Interface #cfg_fc_ph=cfg_fc_ph, #cfg_fc_pd=cfg_fc_pd, #cfg_fc_nph=cfg_fc_nph, #cfg_fc_npd=cfg_fc_npd, #cfg_fc_cplh=cfg_fc_cplh, #cfg_fc_cpld=cfg_fc_cpld, #cfg_fc_sel=cfg_fc_sel, # Configuration Control Interface #cfg_hot_reset_in=cfg_hot_reset_in, #cfg_hot_reset_out=cfg_hot_reset_out, #cfg_config_space_enable=cfg_config_space_enable, #cfg_dsn=cfg_dsn, #cfg_ds_port_number=cfg_ds_port_number, #cfg_ds_bus_number=cfg_ds_bus_number, #cfg_ds_device_number=cfg_ds_device_number, #cfg_ds_function_number=cfg_ds_function_number, #cfg_power_state_change_ack=cfg_power_state_change_ack, #cfg_power_state_change_interrupt=cfg_power_state_change_interrupt, cfg_err_cor_in=status_error_cor, cfg_err_uncor_in=status_error_uncor, #cfg_flr_done=cfg_flr_done, #cfg_vf_flr_done=cfg_vf_flr_done, #cfg_flr_in_process=cfg_flr_in_process, #cfg_vf_flr_in_process=cfg_vf_flr_in_process, #cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready, #cfg_link_training_enable=cfg_link_training_enable, # Configuration Interrupt Controller Interface #cfg_interrupt_int=cfg_interrupt_int, #cfg_interrupt_sent=cfg_interrupt_sent, #cfg_interrupt_pending=cfg_interrupt_pending, cfg_interrupt_msi_enable=cfg_interrupt_msi_enable, cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable, cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update, cfg_interrupt_msi_data=cfg_interrupt_msi_data, cfg_interrupt_msi_select=cfg_interrupt_msi_select, cfg_interrupt_msi_int=cfg_interrupt_msi_int, cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status, cfg_interrupt_msi_pending_status_data_enable= cfg_interrupt_msi_pending_status_data_enable, cfg_interrupt_msi_pending_status_function_num= cfg_interrupt_msi_pending_status_function_num, cfg_interrupt_msi_sent=cfg_interrupt_msi_sent, cfg_interrupt_msi_fail=cfg_interrupt_msi_fail, #cfg_interrupt_msix_enable=cfg_interrupt_msix_enable, #cfg_interrupt_msix_mask=cfg_interrupt_msix_mask, #cfg_interrupt_msix_vf_enable=cfg_interrupt_msix_vf_enable, #cfg_interrupt_msix_vf_mask=cfg_interrupt_msix_vf_mask, #cfg_interrupt_msix_address=cfg_interrupt_msix_address, #cfg_interrupt_msix_data=cfg_interrupt_msix_data, #cfg_interrupt_msix_int=cfg_interrupt_msix_int, #cfg_interrupt_msix_vec_pending=cfg_interrupt_msix_vec_pending, #cfg_interrupt_msix_vec_pending_status=cfg_interrupt_msix_vec_pending_status, cfg_interrupt_msi_attr=cfg_interrupt_msi_attr, cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag, cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number, # Configuration Extend Interface #cfg_ext_read_received=cfg_ext_read_received, #cfg_ext_write_received=cfg_ext_write_received, #cfg_ext_register_number=cfg_ext_register_number, #cfg_ext_function_number=cfg_ext_function_number, #cfg_ext_write_data=cfg_ext_write_data, #cfg_ext_write_byte_enable=cfg_ext_write_byte_enable, #cfg_ext_read_data=cfg_ext_read_data, #cfg_ext_read_data_valid=cfg_ext_read_data_valid, # Clock and Reset Interface user_clk=user_clk, user_reset=user_reset, sys_clk=sys_clk, sys_clk_gt=sys_clk, sys_reset=sys_reset, #phy_rdy_out=phy_rdy_out, cq_pause=cq_pause, cc_pause=cc_pause, rq_pause=rq_pause, rc_pause=rc_pause) # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation( "vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, clk_156mhz=clk_156mhz, rst_156mhz=rst_156mhz, clk_250mhz=user_clk, rst_250mhz=user_reset, user_led_g=user_led_g, user_led_r=user_led_r, front_led=front_led, user_sw=user_sw, m_axis_rq_tdata=m_axis_rq_tdata, m_axis_rq_tkeep=m_axis_rq_tkeep, m_axis_rq_tlast=m_axis_rq_tlast, m_axis_rq_tready=m_axis_rq_tready, m_axis_rq_tuser=m_axis_rq_tuser, m_axis_rq_tvalid=m_axis_rq_tvalid, s_axis_rc_tdata=s_axis_rc_tdata, s_axis_rc_tkeep=s_axis_rc_tkeep, s_axis_rc_tlast=s_axis_rc_tlast, s_axis_rc_tready=s_axis_rc_tready, s_axis_rc_tuser=s_axis_rc_tuser, s_axis_rc_tvalid=s_axis_rc_tvalid, s_axis_cq_tdata=s_axis_cq_tdata, s_axis_cq_tkeep=s_axis_cq_tkeep, s_axis_cq_tlast=s_axis_cq_tlast, s_axis_cq_tready=s_axis_cq_tready, s_axis_cq_tuser=s_axis_cq_tuser, s_axis_cq_tvalid=s_axis_cq_tvalid, m_axis_cc_tdata=m_axis_cc_tdata, m_axis_cc_tkeep=m_axis_cc_tkeep, m_axis_cc_tlast=m_axis_cc_tlast, m_axis_cc_tready=m_axis_cc_tready, m_axis_cc_tuser=m_axis_cc_tuser, m_axis_cc_tvalid=m_axis_cc_tvalid, pcie_tfc_nph_av=pcie_tfc_nph_av, pcie_tfc_npd_av=pcie_tfc_npd_av, cfg_max_payload=cfg_max_payload, cfg_max_read_req=cfg_max_read_req, cfg_mgmt_addr=cfg_mgmt_addr, cfg_mgmt_function_number=cfg_mgmt_function_number, cfg_mgmt_write=cfg_mgmt_write, cfg_mgmt_write_data=cfg_mgmt_write_data, cfg_mgmt_byte_enable=cfg_mgmt_byte_enable, cfg_mgmt_read=cfg_mgmt_read, cfg_mgmt_read_data=cfg_mgmt_read_data, cfg_mgmt_read_write_done=cfg_mgmt_read_write_done, cfg_interrupt_msi_enable=cfg_interrupt_msi_enable, cfg_interrupt_msi_int=cfg_interrupt_msi_int, cfg_interrupt_msi_sent=cfg_interrupt_msi_sent, cfg_interrupt_msi_fail=cfg_interrupt_msi_fail, cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable, cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status, cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update, cfg_interrupt_msi_select=cfg_interrupt_msi_select, cfg_interrupt_msi_data=cfg_interrupt_msi_data, cfg_interrupt_msi_pending_status_function_num= cfg_interrupt_msi_pending_status_function_num, cfg_interrupt_msi_pending_status_data_enable= cfg_interrupt_msi_pending_status_data_enable, cfg_interrupt_msi_attr=cfg_interrupt_msi_attr, cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag, cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number, status_error_cor=status_error_cor, status_error_uncor=status_error_uncor, qsfp_0_tx_clk_0=qsfp_0_tx_clk_0, qsfp_0_tx_rst_0=qsfp_0_tx_rst_0, qsfp_0_txd_0=qsfp_0_txd_0, qsfp_0_txc_0=qsfp_0_txc_0, qsfp_0_rx_clk_0=qsfp_0_rx_clk_0, qsfp_0_rx_rst_0=qsfp_0_rx_rst_0, qsfp_0_rxd_0=qsfp_0_rxd_0, qsfp_0_rxc_0=qsfp_0_rxc_0, qsfp_0_tx_clk_1=qsfp_0_tx_clk_1, qsfp_0_tx_rst_1=qsfp_0_tx_rst_1, qsfp_0_txd_1=qsfp_0_txd_1, qsfp_0_txc_1=qsfp_0_txc_1, qsfp_0_rx_clk_1=qsfp_0_rx_clk_1, qsfp_0_rx_rst_1=qsfp_0_rx_rst_1, qsfp_0_rxd_1=qsfp_0_rxd_1, qsfp_0_rxc_1=qsfp_0_rxc_1, qsfp_0_tx_clk_2=qsfp_0_tx_clk_2, qsfp_0_tx_rst_2=qsfp_0_tx_rst_2, qsfp_0_txd_2=qsfp_0_txd_2, qsfp_0_txc_2=qsfp_0_txc_2, qsfp_0_rx_clk_2=qsfp_0_rx_clk_2, qsfp_0_rx_rst_2=qsfp_0_rx_rst_2, qsfp_0_rxd_2=qsfp_0_rxd_2, qsfp_0_rxc_2=qsfp_0_rxc_2, qsfp_0_tx_clk_3=qsfp_0_tx_clk_3, qsfp_0_tx_rst_3=qsfp_0_tx_rst_3, qsfp_0_txd_3=qsfp_0_txd_3, qsfp_0_txc_3=qsfp_0_txc_3, qsfp_0_rx_clk_3=qsfp_0_rx_clk_3, qsfp_0_rx_rst_3=qsfp_0_rx_rst_3, qsfp_0_rxd_3=qsfp_0_rxd_3, qsfp_0_rxc_3=qsfp_0_rxc_3, qsfp_0_modprs_l=qsfp_0_modprs_l, qsfp_0_sel_l=qsfp_0_sel_l, qsfp_1_tx_clk_0=qsfp_1_tx_clk_0, qsfp_1_tx_rst_0=qsfp_1_tx_rst_0, qsfp_1_txd_0=qsfp_1_txd_0, qsfp_1_txc_0=qsfp_1_txc_0, qsfp_1_rx_clk_0=qsfp_1_rx_clk_0, qsfp_1_rx_rst_0=qsfp_1_rx_rst_0, qsfp_1_rxd_0=qsfp_1_rxd_0, qsfp_1_rxc_0=qsfp_1_rxc_0, qsfp_1_tx_clk_1=qsfp_1_tx_clk_1, qsfp_1_tx_rst_1=qsfp_1_tx_rst_1, qsfp_1_txd_1=qsfp_1_txd_1, qsfp_1_txc_1=qsfp_1_txc_1, qsfp_1_rx_clk_1=qsfp_1_rx_clk_1, qsfp_1_rx_rst_1=qsfp_1_rx_rst_1, qsfp_1_rxd_1=qsfp_1_rxd_1, qsfp_1_rxc_1=qsfp_1_rxc_1, qsfp_1_tx_clk_2=qsfp_1_tx_clk_2, qsfp_1_tx_rst_2=qsfp_1_tx_rst_2, qsfp_1_txd_2=qsfp_1_txd_2, qsfp_1_txc_2=qsfp_1_txc_2, qsfp_1_rx_clk_2=qsfp_1_rx_clk_2, qsfp_1_rx_rst_2=qsfp_1_rx_rst_2, qsfp_1_rxd_2=qsfp_1_rxd_2, qsfp_1_rxc_2=qsfp_1_rxc_2, qsfp_1_tx_clk_3=qsfp_1_tx_clk_3, qsfp_1_tx_rst_3=qsfp_1_tx_rst_3, qsfp_1_txd_3=qsfp_1_txd_3, qsfp_1_txc_3=qsfp_1_txc_3, qsfp_1_rx_clk_3=qsfp_1_rx_clk_3, qsfp_1_rx_rst_3=qsfp_1_rx_rst_3, qsfp_1_rxd_3=qsfp_1_rxd_3, qsfp_1_rxc_3=qsfp_1_rxc_3, qsfp_1_modprs_l=qsfp_1_modprs_l, qsfp_1_sel_l=qsfp_1_sel_l, qsfp_reset_l=qsfp_reset_l, qsfp_int_l=qsfp_int_l, qsfp_i2c_scl_i=qsfp_i2c_scl_i, qsfp_i2c_scl_o=qsfp_i2c_scl_o, qsfp_i2c_scl_t=qsfp_i2c_scl_t, qsfp_i2c_sda_i=qsfp_i2c_sda_i, qsfp_i2c_sda_o=qsfp_i2c_sda_o, qsfp_i2c_sda_t=qsfp_i2c_sda_t, eeprom_i2c_scl_i=eeprom_i2c_scl_i, eeprom_i2c_scl_o=eeprom_i2c_scl_o, eeprom_i2c_scl_t=eeprom_i2c_scl_t, eeprom_i2c_sda_i=eeprom_i2c_sda_i, eeprom_i2c_sda_o=eeprom_i2c_sda_o, eeprom_i2c_sda_t=eeprom_i2c_sda_t, eeprom_wp=eeprom_wp) @always(delay(5)) def clkgen(): clk.next = not clk @always(delay(3)) def qsfp_clkgen(): qsfp_0_tx_clk_0.next = not qsfp_0_tx_clk_0 qsfp_0_rx_clk_0.next = not qsfp_0_rx_clk_0 qsfp_0_tx_clk_1.next = not qsfp_0_tx_clk_1 qsfp_0_rx_clk_1.next = not qsfp_0_rx_clk_1 qsfp_0_tx_clk_2.next = not qsfp_0_tx_clk_2 qsfp_0_rx_clk_2.next = not qsfp_0_rx_clk_2 qsfp_0_tx_clk_3.next = not qsfp_0_tx_clk_3 qsfp_0_rx_clk_3.next = not qsfp_0_rx_clk_3 qsfp_1_tx_clk_0.next = not qsfp_1_tx_clk_0 qsfp_1_rx_clk_0.next = not qsfp_1_rx_clk_0 qsfp_1_tx_clk_1.next = not qsfp_1_tx_clk_1 qsfp_1_rx_clk_1.next = not qsfp_1_rx_clk_1 qsfp_1_tx_clk_2.next = not qsfp_1_tx_clk_2 qsfp_1_rx_clk_2.next = not qsfp_1_rx_clk_2 qsfp_1_tx_clk_3.next = not qsfp_1_tx_clk_3 qsfp_1_rx_clk_3.next = not qsfp_1_rx_clk_3 @always_comb def clk_logic(): sys_clk.next = clk sys_reset.next = not rst loopback_enable = Signal(bool(0)) @instance def loopback(): while True: yield clk.posedge if loopback_enable: if not qsfp_0_0_sink.empty(): pkt = qsfp_0_0_sink.recv() qsfp_0_0_source.send(pkt) if not qsfp_0_1_sink.empty(): pkt = qsfp_0_1_sink.recv() qsfp_0_1_source.send(pkt) if not qsfp_0_2_sink.empty(): pkt = qsfp_0_2_sink.recv() qsfp_0_2_source.send(pkt) if not qsfp_0_3_sink.empty(): pkt = qsfp_0_3_sink.recv() qsfp_0_3_source.send(pkt) if not qsfp_1_0_sink.empty(): pkt = qsfp_1_0_sink.recv() qsfp_1_0_source.send(pkt) if not qsfp_1_1_sink.empty(): pkt = qsfp_1_1_sink.recv() qsfp_1_1_source.send(pkt) if not qsfp_1_2_sink.empty(): pkt = qsfp_1_2_sink.recv() qsfp_1_2_source.send(pkt) if not qsfp_1_3_sink.empty(): pkt = qsfp_1_3_sink.recv() qsfp_1_3_source.send(pkt) @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 qsfp_0_tx_rst_0.next = 1 qsfp_0_rx_rst_0.next = 1 qsfp_0_tx_rst_1.next = 1 qsfp_0_rx_rst_1.next = 1 qsfp_0_tx_rst_2.next = 1 qsfp_0_rx_rst_2.next = 1 qsfp_0_tx_rst_3.next = 1 qsfp_0_rx_rst_3.next = 1 qsfp_1_tx_rst_0.next = 1 qsfp_1_rx_rst_0.next = 1 qsfp_1_tx_rst_1.next = 1 qsfp_1_rx_rst_1.next = 1 qsfp_1_tx_rst_2.next = 1 qsfp_1_rx_rst_2.next = 1 qsfp_1_tx_rst_3.next = 1 qsfp_1_rx_rst_3.next = 1 yield clk.posedge yield delay(100) rst.next = 0 qsfp_0_tx_rst_0.next = 0 qsfp_0_rx_rst_0.next = 0 qsfp_0_tx_rst_1.next = 0 qsfp_0_rx_rst_1.next = 0 qsfp_0_tx_rst_2.next = 0 qsfp_0_rx_rst_2.next = 0 qsfp_0_tx_rst_3.next = 0 qsfp_0_rx_rst_3.next = 0 qsfp_1_tx_rst_0.next = 0 qsfp_1_rx_rst_0.next = 0 qsfp_1_tx_rst_1.next = 0 qsfp_1_rx_rst_1.next = 0 qsfp_1_tx_rst_2.next = 0 qsfp_1_rx_rst_2.next = 0 qsfp_1_tx_rst_3.next = 0 qsfp_1_rx_rst_3.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus current_tag = 1 yield clk.posedge print("test 1: enumeration") current_test.next = 1 yield rc.enumerate(enable_bus_mastering=True, configure_msi=True) dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc yield delay(100) yield clk.posedge print("test 2: init NIC") current_test.next = 2 #data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4); #print(data) #yield delay(1000) #raise StopSimulation yield from driver.init_dev(dev.functions[0].get_id()) yield from driver.interfaces[0].open() #yield from driver.interfaces[1].open() # enable queues yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0200, 0xffffffff) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0300, 0xffffffff) yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete yield delay(100) yield clk.posedge print("test 3: send and receive a packet") current_test.next = 3 # test bad packet #qsfp_0_0_source.send(b'\x55\x55\x55\x55\x55\xd5'+bytearray(range(128))) data = bytearray([x % 256 for x in range(1024)]) yield from driver.interfaces[0].start_xmit(data, 0) yield qsfp_0_0_sink.wait() pkt = qsfp_0_0_sink.recv() print(pkt) qsfp_0_0_source.send(pkt) yield driver.interfaces[0].wait() pkt = driver.interfaces[0].recv() print(pkt) assert frame_checksum(pkt.data) == pkt.rx_checksum # yield from driver.interfaces[1].start_xmit(data, 0) # yield qsfp_1_0_sink.wait() # pkt = qsfp_1_0_sink.recv() # print(pkt) # qsfp_1_0_source.send(pkt) # yield driver.interfaces[1].wait() # pkt = driver.interfaces[1].recv() # print(pkt) # assert frame_checksum(pkt.data) == pkt.rx_checksum yield delay(100) yield clk.posedge print("test 4: multiple small packets") current_test.next = 4 count = 64 pkts = [ bytearray([(x + k) % 256 for x in range(64)]) for k in range(count) ] loopback_enable.next = True for p in pkts: yield from driver.interfaces[0].start_xmit(p, 0) for k in range(count): pkt = driver.interfaces[0].recv() if not pkt: yield driver.interfaces[0].wait() pkt = driver.interfaces[0].recv() print(pkt) assert pkt.data == pkts[k] assert frame_checksum(pkt.data) == pkt.rx_checksum loopback_enable.next = False yield delay(100) yield clk.posedge print("test 5: multiple large packets") current_test.next = 5 count = 64 pkts = [ bytearray([(x + k) % 256 for x in range(1514)]) for k in range(count) ] loopback_enable.next = True for p in pkts: yield from driver.interfaces[0].start_xmit(p, 0) for k in range(count): pkt = driver.interfaces[0].recv() if not pkt: yield driver.interfaces[0].wait() pkt = driver.interfaces[0].recv() print(pkt) assert pkt.data == pkts[k] assert frame_checksum(pkt.data) == pkt.rx_checksum loopback_enable.next = False yield delay(1000) yield clk.posedge print("test 6: TDMA") current_test.next = 6 count = 16 pkts = [ bytearray([(x + k) % 256 for x in range(1514)]) for k in range(count) ] loopback_enable.next = True # configure TDMA # configure TDMA scheduler yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00120, 0) # schedule period fns yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00124, 40000) # schedule period ns yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00128, 0) # schedule period sec (low) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0012c, 0) # schedule period sec (high) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00130, 0) # timeslot period fns yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00134, 10000) # timeslot period ns yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00138, 0) # timeslot period sec (low) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0013c, 0) # timeslot period sec (high) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00140, 0) # active period fns yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00144, 5000) # active period ns yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00148, 0) # active period sec (low) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0014c, 0) # active period sec (high) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00110, 0) # schedule start fns yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00114, 200000) # schedule start ns yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00118, 0) # schedule start sec (low) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0011c, 0) # schedule start sec (high) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00100, 0x00000001) # enable queues yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00200, 0xffffffff) # disable global enable yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00300, 0x00000000) # configure slots yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x10000, 0x00000001) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x10100, 0x00000002) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x10200, 0x00000004) yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x10300, 0x00000008) yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete # send packets for k in range(count): yield from driver.interfaces[0].start_xmit(pkts[k], k % 4) for k in range(count): pkt = driver.interfaces[0].recv() if not pkt: yield driver.interfaces[0].wait() pkt = driver.interfaces[0].recv() print(pkt) #assert pkt.data == pkts[k] #assert frame_checksum(pkt.data) == pkt.rx_checksum loopback_enable.next = False yield delay(100) raise StopSimulation return instances()
def bench(): # Parameters # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) clk_156mhz = Signal(bool(0)) rst_156mhz = Signal(bool(0)) clk_250mhz = Signal(bool(0)) rst_250mhz = Signal(bool(0)) btnu = Signal(bool(0)) btnl = Signal(bool(0)) btnd = Signal(bool(0)) btnr = Signal(bool(0)) btnc = Signal(bool(0)) sw = Signal(intbv(0)[4:]) i2c_scl_i = Signal(bool(1)) i2c_sda_i = Signal(bool(1)) m_axis_rq_tready = Signal(bool(0)) s_axis_rc_tdata = Signal(intbv(0)[256:]) s_axis_rc_tkeep = Signal(intbv(0)[8:]) s_axis_rc_tlast = Signal(bool(0)) s_axis_rc_tuser = Signal(intbv(0)[75:]) s_axis_rc_tvalid = Signal(bool(0)) s_axis_cq_tdata = Signal(intbv(0)[256:]) s_axis_cq_tkeep = Signal(intbv(0)[8:]) s_axis_cq_tlast = Signal(bool(0)) s_axis_cq_tuser = Signal(intbv(0)[85:]) s_axis_cq_tvalid = Signal(bool(0)) m_axis_cc_tready = Signal(bool(0)) pcie_tfc_nph_av = Signal(intbv(0)[2:]) pcie_tfc_npd_av = Signal(intbv(0)[2:]) cfg_max_payload = Signal(intbv(0)[3:]) cfg_max_read_req = Signal(intbv(0)[3:]) cfg_mgmt_read_data = Signal(intbv(0)[32:]) cfg_mgmt_read_write_done = Signal(bool(0)) cfg_interrupt_msi_enable = Signal(intbv(0)[4:]) cfg_interrupt_msi_vf_enable = Signal(intbv(0)[8:]) cfg_interrupt_msi_mmenable = Signal(intbv(0)[12:]) cfg_interrupt_msi_mask_update = Signal(bool(0)) cfg_interrupt_msi_data = Signal(intbv(0)[32:]) cfg_interrupt_msi_sent = Signal(bool(0)) cfg_interrupt_msi_fail = Signal(bool(0)) qsfp_tx_clk_1 = Signal(bool(0)) qsfp_tx_rst_1 = Signal(bool(0)) qsfp_rx_clk_1 = Signal(bool(0)) qsfp_rx_rst_1 = Signal(bool(0)) qsfp_rxd_1 = Signal(intbv(0)[64:]) qsfp_rxc_1 = Signal(intbv(0)[8:]) qsfp_tx_clk_2 = Signal(bool(0)) qsfp_tx_rst_2 = Signal(bool(0)) qsfp_rx_clk_2 = Signal(bool(0)) qsfp_rx_rst_2 = Signal(bool(0)) qsfp_rxd_2 = Signal(intbv(0)[64:]) qsfp_rxc_2 = Signal(intbv(0)[8:]) qsfp_tx_clk_3 = Signal(bool(0)) qsfp_tx_rst_3 = Signal(bool(0)) qsfp_rx_clk_3 = Signal(bool(0)) qsfp_rx_rst_3 = Signal(bool(0)) qsfp_rxd_3 = Signal(intbv(0)[64:]) qsfp_rxc_3 = Signal(intbv(0)[8:]) qsfp_tx_clk_4 = Signal(bool(0)) qsfp_tx_rst_4 = Signal(bool(0)) qsfp_rx_clk_4 = Signal(bool(0)) qsfp_rx_rst_4 = Signal(bool(0)) qsfp_rxd_4 = Signal(intbv(0)[64:]) qsfp_rxc_4 = Signal(intbv(0)[8:]) qsfp_modprsl = Signal(bool(1)) qsfp_intl = Signal(bool(1)) flash_dq_i = Signal(intbv(0)[16:]) # Outputs led = Signal(intbv(0)[8:]) i2c_scl_o = Signal(bool(1)) i2c_scl_t = Signal(bool(1)) i2c_sda_o = Signal(bool(1)) i2c_sda_t = Signal(bool(1)) m_axis_rq_tdata = Signal(intbv(0)[256:]) m_axis_rq_tkeep = Signal(intbv(0)[8:]) m_axis_rq_tlast = Signal(bool(0)) m_axis_rq_tuser = Signal(intbv(0)[60:]) m_axis_rq_tvalid = Signal(bool(0)) s_axis_rc_tready = Signal(bool(0)) s_axis_cq_tready = Signal(bool(0)) m_axis_cc_tdata = Signal(intbv(0)[256:]) m_axis_cc_tkeep = Signal(intbv(0)[8:]) m_axis_cc_tlast = Signal(bool(0)) m_axis_cc_tuser = Signal(intbv(0)[33:]) m_axis_cc_tvalid = Signal(bool(0)) status_error_cor = Signal(bool(0)) status_error_uncor = Signal(bool(0)) cfg_mgmt_addr = Signal(intbv(0)[19:]) cfg_mgmt_write = Signal(bool(0)) cfg_mgmt_write_data = Signal(intbv(0)[32:]) cfg_mgmt_byte_enable = Signal(intbv(0)[4:]) cfg_mgmt_read = Signal(bool(0)) cfg_interrupt_msi_int = Signal(intbv(0)[32:]) cfg_interrupt_msi_pending_status = Signal(intbv(0)[32:]) cfg_interrupt_msi_select = Signal(intbv(0)[4:]) cfg_interrupt_msi_pending_status_function_num = Signal(intbv(0)[4:]) cfg_interrupt_msi_pending_status_data_enable = Signal(bool(0)) cfg_interrupt_msi_attr = Signal(intbv(0)[3:]) cfg_interrupt_msi_tph_present = Signal(bool(0)) cfg_interrupt_msi_tph_type = Signal(intbv(0)[2:]) cfg_interrupt_msi_tph_st_tag = Signal(intbv(0)[9:]) cfg_interrupt_msi_function_number = Signal(intbv(0)[4:]) qsfp_txd_1 = Signal(intbv(0)[64:]) qsfp_txc_1 = Signal(intbv(0)[8:]) qsfp_txd_2 = Signal(intbv(0)[64:]) qsfp_txc_2 = Signal(intbv(0)[8:]) qsfp_txd_3 = Signal(intbv(0)[64:]) qsfp_txc_3 = Signal(intbv(0)[8:]) qsfp_txd_4 = Signal(intbv(0)[64:]) qsfp_txc_4 = Signal(intbv(0)[8:]) qsfp_modsell = Signal(bool(0)) qsfp_resetl = Signal(bool(1)) qsfp_lpmode = Signal(bool(0)) flash_dq_o = Signal(intbv(0)[16:]) flash_dq_oe = Signal(bool(0)) flash_addr = Signal(intbv(0)[23:]) flash_region = Signal(bool(0)) flash_region_oe = Signal(bool(0)) flash_ce_n = Signal(bool(1)) flash_oe_n = Signal(bool(1)) flash_we_n = Signal(bool(1)) flash_adv_n = Signal(bool(1)) # sources and sinks qsfp_1_source = xgmii_ep.XGMIISource() qsfp_1_source_logic = qsfp_1_source.create_logic(qsfp_rx_clk_1, qsfp_rx_rst_1, txd=qsfp_rxd_1, txc=qsfp_rxc_1, name='qsfp_1_source') qsfp_1_sink = xgmii_ep.XGMIISink() qsfp_1_sink_logic = qsfp_1_sink.create_logic(qsfp_tx_clk_1, qsfp_tx_rst_1, rxd=qsfp_txd_1, rxc=qsfp_txc_1, name='qsfp_1_sink') qsfp_2_source = xgmii_ep.XGMIISource() qsfp_2_source_logic = qsfp_2_source.create_logic(qsfp_rx_clk_2, qsfp_rx_rst_2, txd=qsfp_rxd_2, txc=qsfp_rxc_2, name='qsfp_2_source') qsfp_2_sink = xgmii_ep.XGMIISink() qsfp_2_sink_logic = qsfp_2_sink.create_logic(qsfp_tx_clk_2, qsfp_tx_rst_2, rxd=qsfp_txd_2, rxc=qsfp_txc_2, name='qsfp_2_sink') qsfp_3_source = xgmii_ep.XGMIISource() qsfp_3_source_logic = qsfp_3_source.create_logic(qsfp_rx_clk_3, qsfp_rx_rst_3, txd=qsfp_rxd_3, txc=qsfp_rxc_3, name='qsfp_3_source') qsfp_3_sink = xgmii_ep.XGMIISink() qsfp_3_sink_logic = qsfp_3_sink.create_logic(qsfp_tx_clk_3, qsfp_tx_rst_3, rxd=qsfp_txd_3, rxc=qsfp_txc_3, name='qsfp_3_sink') qsfp_4_source = xgmii_ep.XGMIISource() qsfp_4_source_logic = qsfp_4_source.create_logic(qsfp_rx_clk_4, qsfp_rx_rst_4, txd=qsfp_rxd_4, txc=qsfp_rxc_4, name='qsfp_4_source') qsfp_4_sink = xgmii_ep.XGMIISink() qsfp_4_sink_logic = qsfp_4_sink.create_logic(qsfp_tx_clk_4, qsfp_tx_rst_4, rxd=qsfp_txd_4, rxc=qsfp_txc_4, name='qsfp_4_sink') # Clock and Reset Interface user_clk = Signal(bool(0)) user_reset = Signal(bool(0)) sys_clk = Signal(bool(0)) sys_reset = Signal(bool(0)) # PCIe devices rc = pcie.RootComplex() rc.max_payload_size = 0x1 # 256 bytes rc.max_read_request_size = 0x5 # 4096 bytes driver = mqnic.Driver(rc) dev = pcie_us.UltrascalePCIe() dev.pcie_generation = 3 dev.pcie_link_width = 8 dev.user_clock_frequency = 256e6 dev.functions[0].msi_multiple_message_capable = 5 dev.functions[0].configure_bar(0, 16 * 1024 * 1024) dev.functions[0].configure_bar(1, 16 * 1024 * 1024) rc.make_port().connect(dev) pcie_logic = dev.create_logic( # Completer reQuest Interface m_axis_cq_tdata=s_axis_cq_tdata, m_axis_cq_tuser=s_axis_cq_tuser, m_axis_cq_tlast=s_axis_cq_tlast, m_axis_cq_tkeep=s_axis_cq_tkeep, m_axis_cq_tvalid=s_axis_cq_tvalid, m_axis_cq_tready=s_axis_cq_tready, #pcie_cq_np_req=pcie_cq_np_req, pcie_cq_np_req=Signal(bool(1)), #pcie_cq_np_req_count=pcie_cq_np_req_count, # Completer Completion Interface s_axis_cc_tdata=m_axis_cc_tdata, s_axis_cc_tuser=m_axis_cc_tuser, s_axis_cc_tlast=m_axis_cc_tlast, s_axis_cc_tkeep=m_axis_cc_tkeep, s_axis_cc_tvalid=m_axis_cc_tvalid, s_axis_cc_tready=m_axis_cc_tready, # Requester reQuest Interface s_axis_rq_tdata=m_axis_rq_tdata, s_axis_rq_tuser=m_axis_rq_tuser, s_axis_rq_tlast=m_axis_rq_tlast, s_axis_rq_tkeep=m_axis_rq_tkeep, s_axis_rq_tvalid=m_axis_rq_tvalid, s_axis_rq_tready=m_axis_rq_tready, #pcie_rq_seq_num=pcie_rq_seq_num, #pcie_rq_seq_num_vld=pcie_rq_seq_num_vld, #pcie_rq_tag=pcie_rq_tag, #pcie_rq_tag_vld=pcie_rq_tag_vld, # Requester Completion Interface m_axis_rc_tdata=s_axis_rc_tdata, m_axis_rc_tuser=s_axis_rc_tuser, m_axis_rc_tlast=s_axis_rc_tlast, m_axis_rc_tkeep=s_axis_rc_tkeep, m_axis_rc_tvalid=s_axis_rc_tvalid, m_axis_rc_tready=s_axis_rc_tready, # Transmit Flow Control Interface pcie_tfc_nph_av=pcie_tfc_nph_av, pcie_tfc_npd_av=pcie_tfc_npd_av, # Configuration Management Interface cfg_mgmt_addr=cfg_mgmt_addr, cfg_mgmt_write=cfg_mgmt_write, cfg_mgmt_write_data=cfg_mgmt_write_data, cfg_mgmt_byte_enable=cfg_mgmt_byte_enable, cfg_mgmt_read=cfg_mgmt_read, cfg_mgmt_read_data=cfg_mgmt_read_data, cfg_mgmt_read_write_done=cfg_mgmt_read_write_done, #cfg_mgmt_type1_cfg_reg_access=cfg_mgmt_type1_cfg_reg_access, # Configuration Status Interface #cfg_phy_link_down=cfg_phy_link_down, #cfg_phy_link_status=cfg_phy_link_status, #cfg_negotiated_width=cfg_negotiated_width, #cfg_current_speed=cfg_current_speed, cfg_max_payload=cfg_max_payload, cfg_max_read_req=cfg_max_read_req, #cfg_function_status=cfg_function_status, #cfg_vf_status=cfg_vf_status, #cfg_function_power_state=cfg_function_power_state, #cfg_vf_power_state=cfg_vf_power_state, #cfg_link_power_state=cfg_link_power_state, #cfg_err_cor_out=cfg_err_cor_out, #cfg_err_nonfatal_out=cfg_err_nonfatal_out, #cfg_err_fatal_out=cfg_err_fatal_out, #cfg_ltr_enable=cfg_ltr_enable, #cfg_ltssm_state=cfg_ltssm_state, #cfg_rcb_status=cfg_rcb_status, #cfg_dpa_substate_change=cfg_dpa_substate_change, #cfg_obff_enable=cfg_obff_enable, #cfg_pl_status_change=cfg_pl_status_change, #cfg_tph_requester_enable=cfg_tph_requester_enable, #cfg_tph_st_mode=cfg_tph_st_mode, #cfg_vf_tph_requester_enable=cfg_vf_tph_requester_enable, #cfg_vf_tph_st_mode=cfg_vf_tph_st_mode, # Configuration Received Message Interface #cfg_msg_received=cfg_msg_received, #cfg_msg_received_data=cfg_msg_received_data, #cfg_msg_received_type=cfg_msg_received_type, # Configuration Transmit Message Interface #cfg_msg_transmit=cfg_msg_transmit, #cfg_msg_transmit_type=cfg_msg_transmit_type, #cfg_msg_transmit_data=cfg_msg_transmit_data, #cfg_msg_transmit_done=cfg_msg_transmit_done, # Configuration Flow Control Interface #cfg_fc_ph=cfg_fc_ph, #cfg_fc_pd=cfg_fc_pd, #cfg_fc_nph=cfg_fc_nph, #cfg_fc_npd=cfg_fc_npd, #cfg_fc_cplh=cfg_fc_cplh, #cfg_fc_cpld=cfg_fc_cpld, #cfg_fc_sel=cfg_fc_sel, # Per-Function Status Interface #cfg_per_func_status_control=cfg_per_func_status_control, #cfg_per_func_status_data=cfg_per_func_status_data, # Configuration Control Interface #cfg_hot_reset_in=cfg_hot_reset_in, #cfg_hot_reset_out=cfg_hot_reset_out, #cfg_config_space_enable=cfg_config_space_enable, #cfg_per_function_update_done=cfg_per_function_update_done, #cfg_per_function_number=cfg_per_function_number, #cfg_per_function_output_request=cfg_per_function_output_request, #cfg_dsn=cfg_dsn, #cfg_ds_bus_number=cfg_ds_bus_number, #cfg_ds_device_number=cfg_ds_device_number, #cfg_ds_function_number=cfg_ds_function_number, #cfg_power_state_change_ack=cfg_power_state_change_ack, #cfg_power_state_change_interrupt=cfg_power_state_change_interrupt, cfg_err_cor_in=status_error_cor, cfg_err_uncor_in=status_error_uncor, #cfg_flr_done=cfg_flr_done, #cfg_vf_flr_done=cfg_vf_flr_done, #cfg_flr_in_process=cfg_flr_in_process, #cfg_vf_flr_in_process=cfg_vf_flr_in_process, #cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready, #cfg_link_training_enable=cfg_link_training_enable, # Configuration Interrupt Controller Interface #cfg_interrupt_int=cfg_interrupt_int, #cfg_interrupt_sent=cfg_interrupt_sent, #cfg_interrupt_pending=cfg_interrupt_pending, cfg_interrupt_msi_enable=cfg_interrupt_msi_enable, cfg_interrupt_msi_vf_enable=cfg_interrupt_msi_vf_enable, cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable, cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update, cfg_interrupt_msi_data=cfg_interrupt_msi_data, cfg_interrupt_msi_select=cfg_interrupt_msi_select, cfg_interrupt_msi_int=cfg_interrupt_msi_int, cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status, cfg_interrupt_msi_pending_status_data_enable= cfg_interrupt_msi_pending_status_data_enable, cfg_interrupt_msi_pending_status_function_num= cfg_interrupt_msi_pending_status_function_num, cfg_interrupt_msi_sent=cfg_interrupt_msi_sent, cfg_interrupt_msi_fail=cfg_interrupt_msi_fail, #cfg_interrupt_msix_enable=cfg_interrupt_msix_enable, #cfg_interrupt_msix_mask=cfg_interrupt_msix_mask, #cfg_interrupt_msix_vf_enable=cfg_interrupt_msix_vf_enable, #cfg_interrupt_msix_vf_mask=cfg_interrupt_msix_vf_mask, #cfg_interrupt_msix_address=cfg_interrupt_msix_address, #cfg_interrupt_msix_data=cfg_interrupt_msix_data, #cfg_interrupt_msix_int=cfg_interrupt_msix_int, #cfg_interrupt_msix_sent=cfg_interrupt_msix_sent, #cfg_interrupt_msix_fail=cfg_interrupt_msix_fail, cfg_interrupt_msi_attr=cfg_interrupt_msi_attr, cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag, cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number, # Configuration Extend Interface #cfg_ext_read_received=cfg_ext_read_received, #cfg_ext_write_received=cfg_ext_write_received, #cfg_ext_register_number=cfg_ext_register_number, #cfg_ext_function_number=cfg_ext_function_number, #cfg_ext_write_data=cfg_ext_write_data, #cfg_ext_write_byte_enable=cfg_ext_write_byte_enable, #cfg_ext_read_data=cfg_ext_read_data, #cfg_ext_read_data_valid=cfg_ext_read_data_valid, # Clock and Reset Interface user_clk=user_clk, user_reset=user_reset, sys_clk=sys_clk, sys_clk_gt=sys_clk, sys_reset=sys_reset, #pcie_perstn0_out=pcie_perstn0_out, #pcie_perstn1_in=pcie_perstn1_in, #pcie_perstn1_out=pcie_perstn1_out ) # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation( "vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, clk_156mhz=clk_156mhz, rst_156mhz=rst_156mhz, clk_250mhz=user_clk, rst_250mhz=user_reset, btnu=btnu, btnl=btnl, btnd=btnd, btnr=btnr, btnc=btnc, sw=sw, led=led, i2c_scl_i=i2c_scl_i, i2c_scl_o=i2c_scl_o, i2c_scl_t=i2c_scl_t, i2c_sda_i=i2c_sda_i, i2c_sda_o=i2c_sda_o, i2c_sda_t=i2c_sda_t, m_axis_rq_tdata=m_axis_rq_tdata, m_axis_rq_tkeep=m_axis_rq_tkeep, m_axis_rq_tlast=m_axis_rq_tlast, m_axis_rq_tready=m_axis_rq_tready, m_axis_rq_tuser=m_axis_rq_tuser, m_axis_rq_tvalid=m_axis_rq_tvalid, s_axis_rc_tdata=s_axis_rc_tdata, s_axis_rc_tkeep=s_axis_rc_tkeep, s_axis_rc_tlast=s_axis_rc_tlast, s_axis_rc_tready=s_axis_rc_tready, s_axis_rc_tuser=s_axis_rc_tuser, s_axis_rc_tvalid=s_axis_rc_tvalid, s_axis_cq_tdata=s_axis_cq_tdata, s_axis_cq_tkeep=s_axis_cq_tkeep, s_axis_cq_tlast=s_axis_cq_tlast, s_axis_cq_tready=s_axis_cq_tready, s_axis_cq_tuser=s_axis_cq_tuser, s_axis_cq_tvalid=s_axis_cq_tvalid, m_axis_cc_tdata=m_axis_cc_tdata, m_axis_cc_tkeep=m_axis_cc_tkeep, m_axis_cc_tlast=m_axis_cc_tlast, m_axis_cc_tready=m_axis_cc_tready, m_axis_cc_tuser=m_axis_cc_tuser, m_axis_cc_tvalid=m_axis_cc_tvalid, pcie_tfc_nph_av=pcie_tfc_nph_av, pcie_tfc_npd_av=pcie_tfc_npd_av, cfg_max_payload=cfg_max_payload, cfg_max_read_req=cfg_max_read_req, cfg_mgmt_addr=cfg_mgmt_addr, cfg_mgmt_write=cfg_mgmt_write, cfg_mgmt_write_data=cfg_mgmt_write_data, cfg_mgmt_byte_enable=cfg_mgmt_byte_enable, cfg_mgmt_read=cfg_mgmt_read, cfg_mgmt_read_data=cfg_mgmt_read_data, cfg_mgmt_read_write_done=cfg_mgmt_read_write_done, cfg_interrupt_msi_enable=cfg_interrupt_msi_enable, cfg_interrupt_msi_vf_enable=cfg_interrupt_msi_vf_enable, cfg_interrupt_msi_int=cfg_interrupt_msi_int, cfg_interrupt_msi_sent=cfg_interrupt_msi_sent, cfg_interrupt_msi_fail=cfg_interrupt_msi_fail, cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable, cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status, cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update, cfg_interrupt_msi_select=cfg_interrupt_msi_select, cfg_interrupt_msi_data=cfg_interrupt_msi_data, cfg_interrupt_msi_pending_status_function_num= cfg_interrupt_msi_pending_status_function_num, cfg_interrupt_msi_pending_status_data_enable= cfg_interrupt_msi_pending_status_data_enable, cfg_interrupt_msi_attr=cfg_interrupt_msi_attr, cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag, cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number, status_error_cor=status_error_cor, status_error_uncor=status_error_uncor, qsfp_tx_clk_1=qsfp_tx_clk_1, qsfp_tx_rst_1=qsfp_tx_rst_1, qsfp_txd_1=qsfp_txd_1, qsfp_txc_1=qsfp_txc_1, qsfp_rx_clk_1=qsfp_rx_clk_1, qsfp_rx_rst_1=qsfp_rx_rst_1, qsfp_rxd_1=qsfp_rxd_1, qsfp_rxc_1=qsfp_rxc_1, qsfp_tx_clk_2=qsfp_tx_clk_2, qsfp_tx_rst_2=qsfp_tx_rst_2, qsfp_txd_2=qsfp_txd_2, qsfp_txc_2=qsfp_txc_2, qsfp_rx_clk_2=qsfp_rx_clk_2, qsfp_rx_rst_2=qsfp_rx_rst_2, qsfp_rxd_2=qsfp_rxd_2, qsfp_rxc_2=qsfp_rxc_2, qsfp_tx_clk_3=qsfp_tx_clk_3, qsfp_tx_rst_3=qsfp_tx_rst_3, qsfp_txd_3=qsfp_txd_3, qsfp_txc_3=qsfp_txc_3, qsfp_rx_clk_3=qsfp_rx_clk_3, qsfp_rx_rst_3=qsfp_rx_rst_3, qsfp_rxd_3=qsfp_rxd_3, qsfp_rxc_3=qsfp_rxc_3, qsfp_tx_clk_4=qsfp_tx_clk_4, qsfp_tx_rst_4=qsfp_tx_rst_4, qsfp_txd_4=qsfp_txd_4, qsfp_txc_4=qsfp_txc_4, qsfp_rx_clk_4=qsfp_rx_clk_4, qsfp_rx_rst_4=qsfp_rx_rst_4, qsfp_rxd_4=qsfp_rxd_4, qsfp_rxc_4=qsfp_rxc_4, qsfp_modsell=qsfp_modsell, qsfp_resetl=qsfp_resetl, qsfp_modprsl=qsfp_modprsl, qsfp_intl=qsfp_intl, qsfp_lpmode=qsfp_lpmode, flash_dq_i=flash_dq_i, flash_dq_o=flash_dq_o, flash_dq_oe=flash_dq_oe, flash_addr=flash_addr, flash_region=flash_region, flash_region_oe=flash_region_oe, flash_ce_n=flash_ce_n, flash_oe_n=flash_oe_n, flash_we_n=flash_we_n, flash_adv_n=flash_adv_n) @always(delay(5)) def clkgen(): clk.next = not clk @always(delay(3)) def clkgen2(): qsfp_tx_clk_1.next = not qsfp_tx_clk_1 qsfp_rx_clk_1.next = not qsfp_rx_clk_1 qsfp_tx_clk_2.next = not qsfp_tx_clk_2 qsfp_rx_clk_2.next = not qsfp_rx_clk_2 qsfp_tx_clk_3.next = not qsfp_tx_clk_3 qsfp_rx_clk_3.next = not qsfp_rx_clk_3 qsfp_tx_clk_4.next = not qsfp_tx_clk_4 qsfp_rx_clk_4.next = not qsfp_rx_clk_4 @always_comb def clk_logic(): sys_clk.next = clk sys_reset.next = not rst loopback_enable = Signal(bool(0)) @instance def loopback(): while True: yield clk.posedge if loopback_enable: if not qsfp_1_sink.empty(): pkt = qsfp_1_sink.recv() qsfp_1_source.send(pkt) if not qsfp_2_sink.empty(): pkt = qsfp_2_sink.recv() qsfp_2_source.send(pkt) if not qsfp_3_sink.empty(): pkt = qsfp_3_sink.recv() qsfp_3_source.send(pkt) if not qsfp_4_sink.empty(): pkt = qsfp_4_sink.recv() qsfp_4_source.send(pkt) @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 qsfp_tx_rst_1.next = 1 qsfp_rx_rst_1.next = 1 qsfp_tx_rst_2.next = 1 qsfp_rx_rst_2.next = 1 qsfp_tx_rst_3.next = 1 qsfp_rx_rst_3.next = 1 qsfp_tx_rst_4.next = 1 qsfp_rx_rst_4.next = 1 yield clk.posedge rst.next = 0 qsfp_tx_rst_1.next = 0 qsfp_rx_rst_1.next = 0 qsfp_tx_rst_2.next = 0 qsfp_rx_rst_2.next = 0 qsfp_tx_rst_3.next = 0 qsfp_rx_rst_3.next = 0 qsfp_tx_rst_4.next = 0 qsfp_rx_rst_4.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus current_tag = 1 yield clk.posedge print("test 1: enumeration") current_test.next = 1 yield rc.enumerate(enable_bus_mastering=True, configure_msi=True) dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc yield from rc.mem_write_dword(dev_pf0_bar0 + 0x270, 0) yield from rc.mem_write_dword(dev_pf0_bar0 + 0x274, 0) yield from rc.mem_write_dword(dev_pf0_bar0 + 0x278, 0) yield from rc.mem_write_dword(dev_pf0_bar0 + 0x27C, 0) yield from rc.mem_write_dword(dev_pf0_bar0 + 0x290, 0) yield from rc.mem_write_dword(dev_pf0_bar0 + 0x294, 1000) yield from rc.mem_write_dword(dev_pf0_bar0 + 0x298, 0) yield from rc.mem_write_dword(dev_pf0_bar0 + 0x29C, 0) yield from rc.mem_write_dword(dev_pf0_bar0 + 0x280, 0) yield from rc.mem_write_dword(dev_pf0_bar0 + 0x284, 2000) yield from rc.mem_write_dword(dev_pf0_bar0 + 0x288, 0) yield from rc.mem_write_dword(dev_pf0_bar0 + 0x28C, 0) yield delay(100) yield clk.posedge print("test 2: init NIC") current_test.next = 2 yield from driver.init_dev(dev.functions[0].get_id()) yield from driver.interfaces[0].open() # enable queues yield from rc.mem_write_dword( driver.interfaces[0].ports[0].hw_addr + 0x0040, 0x00000001) for k in range(32): yield from rc.mem_write_dword( driver.interfaces[0].ports[0].schedulers[0].hw_addr + 4 * k, 0x00000001) yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete yield delay(100) yield clk.posedge print("test 3: send and receive a packet") current_test.next = 3 data = bytearray([x % 256 for x in range(1024)]) yield from driver.interfaces[0].start_xmit(data, 0) yield qsfp_1_sink.wait() pkt = qsfp_1_sink.recv() print(pkt) qsfp_1_source.send(pkt) yield driver.interfaces[0].wait() pkt = driver.interfaces[0].recv() print(pkt) yield delay(100) yield clk.posedge print("test 4: multiple small packets") current_test.next = 4 count = 64 pkts = [ bytearray([(x + k) % 256 for x in range(64)]) for k in range(count) ] loopback_enable.next = True for p in pkts: yield from driver.interfaces[0].start_xmit(p, 0) for k in range(count): pkt = driver.interfaces[0].recv() if not pkt: yield driver.interfaces[0].wait() pkt = driver.interfaces[0].recv() print(pkt) assert pkt.data == pkts[k] assert frame_checksum(pkt.data) == pkt.rx_checksum loopback_enable.next = False yield delay(100) yield clk.posedge print("test 5: multiple large packets") current_test.next = 5 count = 64 pkts = [ bytearray([(x + k) % 256 for x in range(1514)]) for k in range(count) ] loopback_enable.next = True for p in pkts: yield from driver.interfaces[0].start_xmit(p, 0) for k in range(count): pkt = driver.interfaces[0].recv() if not pkt: yield driver.interfaces[0].wait() pkt = driver.interfaces[0].recv() print(pkt) assert pkt.data == pkts[k] assert frame_checksum(pkt.data) == pkt.rx_checksum loopback_enable.next = False yield delay(100) raise StopSimulation return instances()
def bench(): # Parameters AXIS_PCIE_DATA_WIDTH = 256 AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) AXIS_PCIE_RC_USER_WIDTH = 75 AXIS_PCIE_RQ_USER_WIDTH = 60 AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH AXI_ADDR_WIDTH = 64 AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8) AXI_ID_WIDTH = 8 AXI_MAX_BURST_LEN = 256 PCIE_ADDR_WIDTH = 64 PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256 PCIE_TAG_WIDTH = (PCIE_TAG_COUNT-1).bit_length() PCIE_EXT_TAG_ENABLE = 1 LEN_WIDTH = 20 TAG_WIDTH = 8 # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) s_axis_rc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]) s_axis_rc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) s_axis_rc_tvalid = Signal(bool(0)) s_axis_rc_tlast = Signal(bool(0)) s_axis_rc_tuser = Signal(intbv(0)[AXIS_PCIE_RC_USER_WIDTH:]) m_axis_rq_tready = Signal(bool(0)) s_axis_read_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_read_desc_axi_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) s_axis_read_desc_len = Signal(intbv(0)[LEN_WIDTH:]) s_axis_read_desc_tag = Signal(intbv(0)[TAG_WIDTH:]) s_axis_read_desc_valid = Signal(bool(0)) s_axis_write_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_write_desc_axi_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) s_axis_write_desc_len = Signal(intbv(0)[LEN_WIDTH:]) s_axis_write_desc_tag = Signal(intbv(0)[TAG_WIDTH:]) s_axis_write_desc_valid = Signal(bool(0)) m_axi_awready = Signal(bool(0)) m_axi_wready = Signal(bool(0)) m_axi_bid = Signal(intbv(0)[AXI_ID_WIDTH:]) m_axi_bresp = Signal(intbv(0)[2:]) m_axi_bvalid = Signal(bool(0)) m_axi_arready = Signal(bool(0)) m_axi_rid = Signal(intbv(0)[AXI_ID_WIDTH:]) m_axi_rdata = Signal(intbv(0)[AXI_DATA_WIDTH:]) m_axi_rresp = Signal(intbv(0)[2:]) m_axi_rlast = Signal(bool(0)) m_axi_rvalid = Signal(bool(0)) read_enable = Signal(bool(0)) write_enable = Signal(bool(0)) ext_tag_enable = Signal(bool(0)) requester_id = Signal(intbv(0)[16:]) requester_id_enable = Signal(bool(0)) max_read_request_size = Signal(intbv(0)[3:]) max_payload_size = Signal(intbv(0)[3:]) # Outputs s_axis_rc_tready = Signal(bool(0)) m_axis_rq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]) m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]) m_axis_rq_tvalid = Signal(bool(0)) m_axis_rq_tlast = Signal(bool(0)) m_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:]) s_axis_read_desc_ready = Signal(bool(0)) m_axis_read_desc_status_tag = Signal(intbv(0)[TAG_WIDTH:]) m_axis_read_desc_status_valid = Signal(bool(0)) s_axis_write_desc_ready = Signal(bool(0)) m_axis_write_desc_status_tag = Signal(intbv(0)[TAG_WIDTH:]) m_axis_write_desc_status_valid = Signal(bool(0)) m_axi_awid = Signal(intbv(0)[AXI_ID_WIDTH:]) m_axi_awaddr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) m_axi_awlen = Signal(intbv(0)[8:]) m_axi_awsize = Signal(intbv(5)[3:]) m_axi_awburst = Signal(intbv(1)[2:]) m_axi_awlock = Signal(bool(0)) m_axi_awcache = Signal(intbv(3)[4:]) m_axi_awprot = Signal(intbv(2)[3:]) m_axi_awvalid = Signal(bool(0)) m_axi_wdata = Signal(intbv(0)[AXI_DATA_WIDTH:]) m_axi_wstrb = Signal(intbv(0)[AXI_STRB_WIDTH:]) m_axi_wlast = Signal(bool(0)) m_axi_wvalid = Signal(bool(0)) m_axi_bready = Signal(bool(0)) m_axi_arid = Signal(intbv(0)[AXI_ID_WIDTH:]) m_axi_araddr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) m_axi_arlen = Signal(intbv(0)[8:]) m_axi_arsize = Signal(intbv(5)[3:]) m_axi_arburst = Signal(intbv(1)[2:]) m_axi_arlock = Signal(bool(0)) m_axi_arcache = Signal(intbv(3)[4:]) m_axi_arprot = Signal(intbv(2)[3:]) m_axi_arvalid = Signal(bool(0)) m_axi_rready = Signal(bool(0)) status_error_cor = Signal(bool(0)) status_error_uncor = Signal(bool(0)) # Clock and Reset Interface user_clk=Signal(bool(0)) user_reset=Signal(bool(0)) sys_clk=Signal(bool(0)) sys_reset=Signal(bool(0)) # AXI4 RAM model axi_ram_inst = axi.AXIRam(2**16) axi_ram_port0 = axi_ram_inst.create_port( user_clk, s_axi_awid=m_axi_awid, s_axi_awaddr=m_axi_awaddr, s_axi_awlen=m_axi_awlen, s_axi_awsize=m_axi_awsize, s_axi_awburst=m_axi_awburst, s_axi_awlock=m_axi_awlock, s_axi_awcache=m_axi_awcache, s_axi_awprot=m_axi_awprot, s_axi_awvalid=m_axi_awvalid, s_axi_awready=m_axi_awready, s_axi_wdata=m_axi_wdata, s_axi_wstrb=m_axi_wstrb, s_axi_wlast=m_axi_wlast, s_axi_wvalid=m_axi_wvalid, s_axi_wready=m_axi_wready, s_axi_bid=m_axi_bid, s_axi_bresp=m_axi_bresp, s_axi_bvalid=m_axi_bvalid, s_axi_bready=m_axi_bready, s_axi_arid=m_axi_arid, s_axi_araddr=m_axi_araddr, s_axi_arlen=m_axi_arlen, s_axi_arsize=m_axi_arsize, s_axi_arburst=m_axi_arburst, s_axi_arlock=m_axi_arlock, s_axi_arcache=m_axi_arcache, s_axi_arprot=m_axi_arprot, s_axi_arvalid=m_axi_arvalid, s_axi_arready=m_axi_arready, s_axi_rid=m_axi_rid, s_axi_rdata=m_axi_rdata, s_axi_rresp=m_axi_rresp, s_axi_rlast=m_axi_rlast, s_axi_rvalid=m_axi_rvalid, s_axi_rready=m_axi_rready, name='port0' ) # sources and sinks read_desc_source = axis_ep.AXIStreamSource() read_desc_source_logic = read_desc_source.create_logic( user_clk, user_reset, tdata=(s_axis_read_desc_pcie_addr, s_axis_read_desc_axi_addr, s_axis_read_desc_len, s_axis_read_desc_tag), tvalid=s_axis_read_desc_valid, tready=s_axis_read_desc_ready, name='read_desc_source' ) read_desc_status_sink = axis_ep.AXIStreamSink() read_desc_status_sink_logic = read_desc_status_sink.create_logic( user_clk, user_reset, tdata=(m_axis_read_desc_status_tag,), tvalid=m_axis_read_desc_status_valid, name='read_desc_status_sink' ) write_desc_source = axis_ep.AXIStreamSource() write_desc_source_logic = write_desc_source.create_logic( user_clk, user_reset, tdata=(s_axis_write_desc_pcie_addr, s_axis_write_desc_axi_addr, s_axis_write_desc_len, s_axis_write_desc_tag), tvalid=s_axis_write_desc_valid, tready=s_axis_write_desc_ready, name='write_desc_source' ) write_desc_status_sink = axis_ep.AXIStreamSink() write_desc_status_sink_logic = write_desc_status_sink.create_logic( user_clk, user_reset, tdata=(m_axis_write_desc_status_tag,), tvalid=m_axis_write_desc_status_valid, name='write_desc_status_sink' ) # PCIe devices rc = pcie.RootComplex() mem_base, mem_data = rc.alloc_region(16*1024*1024) dev = pcie_us.UltrascalePCIe() dev.pcie_generation = 3 dev.pcie_link_width = 8 dev.user_clock_frequency = 256e6 rc.make_port().connect(dev) pcie_logic = dev.create_logic( # Completer reQuest Interface m_axis_cq_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]), m_axis_cq_tuser=Signal(intbv(0)[85:]), m_axis_cq_tlast=Signal(bool(0)), m_axis_cq_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]), m_axis_cq_tvalid=Signal(bool(0)), m_axis_cq_tready=Signal(bool(1)), pcie_cq_np_req=Signal(bool(1)), pcie_cq_np_req_count=Signal(intbv(0)[6:]), # Completer Completion Interface s_axis_cc_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]), s_axis_cc_tuser=Signal(intbv(0)[33:]), s_axis_cc_tlast=Signal(bool(0)), s_axis_cc_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]), s_axis_cc_tvalid=Signal(bool(0)), s_axis_cc_tready=Signal(bool(0)), # Requester reQuest Interface s_axis_rq_tdata=m_axis_rq_tdata, s_axis_rq_tuser=m_axis_rq_tuser, s_axis_rq_tlast=m_axis_rq_tlast, s_axis_rq_tkeep=m_axis_rq_tkeep, s_axis_rq_tvalid=m_axis_rq_tvalid, s_axis_rq_tready=m_axis_rq_tready, # pcie_rq_seq_num=pcie_rq_seq_num, # pcie_rq_seq_num_vld=pcie_rq_seq_num_vld, # pcie_rq_tag=pcie_rq_tag, # pcie_rq_tag_av=pcie_rq_tag_av, # pcie_rq_tag_vld=pcie_rq_tag_vld, # Requester Completion Interface m_axis_rc_tdata=s_axis_rc_tdata, m_axis_rc_tuser=s_axis_rc_tuser, m_axis_rc_tlast=s_axis_rc_tlast, m_axis_rc_tkeep=s_axis_rc_tkeep, m_axis_rc_tvalid=s_axis_rc_tvalid, m_axis_rc_tready=s_axis_rc_tready, # Transmit Flow Control Interface # pcie_tfc_nph_av=pcie_tfc_nph_av, # pcie_tfc_npd_av=pcie_tfc_npd_av, # Configuration Control Interface # cfg_hot_reset_in=cfg_hot_reset_in, # cfg_hot_reset_out=cfg_hot_reset_out, # cfg_config_space_enable=cfg_config_space_enable, # cfg_per_function_update_done=cfg_per_function_update_done, # cfg_per_function_number=cfg_per_function_number, # cfg_per_function_output_request=cfg_per_function_output_request, # cfg_dsn=cfg_dsn, # cfg_ds_bus_number=cfg_ds_bus_number, # cfg_ds_device_number=cfg_ds_device_number, # cfg_ds_function_number=cfg_ds_function_number, # cfg_power_state_change_ack=cfg_power_state_change_ack, # cfg_power_state_change_interrupt=cfg_power_state_change_interrupt, # cfg_err_cor_in=cfg_err_cor_in, # cfg_err_uncor_in=cfg_err_uncor_in, # cfg_flr_done=cfg_flr_done, # cfg_vf_flr_done=cfg_vf_flr_done, # cfg_flr_in_process=cfg_flr_in_process, # cfg_vf_flr_in_process=cfg_vf_flr_in_process, # cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready, # cfg_link_training_enable=cfg_link_training_enable, # Clock and Reset Interface user_clk=user_clk, user_reset=user_reset, #user_lnk_up=user_lnk_up, sys_clk=sys_clk, sys_clk_gt=sys_clk, sys_reset=sys_reset ) # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation( "vvp -m myhdl %s.vvp -lxt2" % testbench, clk=user_clk, rst=user_reset, current_test=current_test, s_axis_rc_tdata=s_axis_rc_tdata, s_axis_rc_tkeep=s_axis_rc_tkeep, s_axis_rc_tvalid=s_axis_rc_tvalid, s_axis_rc_tready=s_axis_rc_tready, s_axis_rc_tlast=s_axis_rc_tlast, s_axis_rc_tuser=s_axis_rc_tuser, m_axis_rq_tdata=m_axis_rq_tdata, m_axis_rq_tkeep=m_axis_rq_tkeep, m_axis_rq_tvalid=m_axis_rq_tvalid, m_axis_rq_tready=m_axis_rq_tready, m_axis_rq_tlast=m_axis_rq_tlast, m_axis_rq_tuser=m_axis_rq_tuser, s_axis_read_desc_pcie_addr=s_axis_read_desc_pcie_addr, s_axis_read_desc_axi_addr=s_axis_read_desc_axi_addr, s_axis_read_desc_len=s_axis_read_desc_len, s_axis_read_desc_tag=s_axis_read_desc_tag, s_axis_read_desc_valid=s_axis_read_desc_valid, s_axis_read_desc_ready=s_axis_read_desc_ready, m_axis_read_desc_status_tag=m_axis_read_desc_status_tag, m_axis_read_desc_status_valid=m_axis_read_desc_status_valid, s_axis_write_desc_pcie_addr=s_axis_write_desc_pcie_addr, s_axis_write_desc_axi_addr=s_axis_write_desc_axi_addr, s_axis_write_desc_len=s_axis_write_desc_len, s_axis_write_desc_tag=s_axis_write_desc_tag, s_axis_write_desc_valid=s_axis_write_desc_valid, s_axis_write_desc_ready=s_axis_write_desc_ready, m_axis_write_desc_status_tag=m_axis_write_desc_status_tag, m_axis_write_desc_status_valid=m_axis_write_desc_status_valid, m_axi_awid=m_axi_awid, m_axi_awaddr=m_axi_awaddr, m_axi_awlen=m_axi_awlen, m_axi_awsize=m_axi_awsize, m_axi_awburst=m_axi_awburst, m_axi_awlock=m_axi_awlock, m_axi_awcache=m_axi_awcache, m_axi_awprot=m_axi_awprot, m_axi_awvalid=m_axi_awvalid, m_axi_awready=m_axi_awready, m_axi_wdata=m_axi_wdata, m_axi_wstrb=m_axi_wstrb, m_axi_wlast=m_axi_wlast, m_axi_wvalid=m_axi_wvalid, m_axi_wready=m_axi_wready, m_axi_bid=m_axi_bid, m_axi_bresp=m_axi_bresp, m_axi_bvalid=m_axi_bvalid, m_axi_bready=m_axi_bready, m_axi_arid=m_axi_arid, m_axi_araddr=m_axi_araddr, m_axi_arlen=m_axi_arlen, m_axi_arsize=m_axi_arsize, m_axi_arburst=m_axi_arburst, m_axi_arlock=m_axi_arlock, m_axi_arcache=m_axi_arcache, m_axi_arprot=m_axi_arprot, m_axi_arvalid=m_axi_arvalid, m_axi_arready=m_axi_arready, m_axi_rid=m_axi_rid, m_axi_rdata=m_axi_rdata, m_axi_rresp=m_axi_rresp, m_axi_rlast=m_axi_rlast, m_axi_rvalid=m_axi_rvalid, m_axi_rready=m_axi_rready, read_enable=read_enable, write_enable=write_enable, ext_tag_enable=ext_tag_enable, requester_id=requester_id, requester_id_enable=requester_id_enable, max_read_request_size=max_read_request_size, max_payload_size=max_payload_size, status_error_cor=status_error_cor, status_error_uncor=status_error_uncor ) @always(delay(4)) def clkgen(): clk.next = not clk @always_comb def clk_logic(): sys_clk.next = clk sys_reset.next = not rst @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus cur_tag = 1 max_payload_size.next = 0 max_read_request_size.next = 2 read_enable.next = 1 write_enable.next = 1 yield user_clk.posedge print("test 1: enumeration") current_test.next = 1 yield rc.enumerate(enable_bus_mastering=True) yield delay(100) yield user_clk.posedge print("test 2: PCIe write") current_test.next = 2 pcie_addr = 0x00000000 axi_addr = 0x00000000 test_data = b'\x11\x22\x33\x44' axi_ram_inst.write_mem(axi_addr, test_data) mem_data[pcie_addr:pcie_addr+len(test_data)] = b'\x00'*len(test_data) data = axi_ram_inst.read_mem(axi_addr, 32) for i in range(0, len(data), 16): print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16])))) write_desc_source.send([(mem_base+pcie_addr, axi_addr, len(test_data), cur_tag)]) yield write_desc_status_sink.wait(1000) yield delay(50) status = write_desc_status_sink.recv() print(status) assert status.data[0][0] == cur_tag data = mem_data[pcie_addr:pcie_addr+32] for i in range(0, len(data), 16): print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16])))) assert mem_data[pcie_addr:pcie_addr+len(test_data)] == test_data cur_tag = (cur_tag + 1) % 256 yield delay(100) yield user_clk.posedge print("test 3: PCIe read") current_test.next = 3 pcie_addr = 0x00000000 axi_addr = 0x00000000 test_data = b'\x11\x22\x33\x44' axi_ram_inst.write_mem(axi_addr, b'\x00'*len(test_data)) mem_data[pcie_addr:pcie_addr+len(test_data)] = test_data data = mem_data[pcie_addr:pcie_addr+32] for i in range(0, len(data), 16): print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16])))) read_desc_source.send([(pcie_addr, axi_addr, len(test_data), cur_tag)]) yield read_desc_status_sink.wait(2000) status = read_desc_status_sink.recv() print(status) assert status.data[0][0] == cur_tag data = axi_ram_inst.read_mem(axi_addr, 32) for i in range(0, len(data), 16): print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16])))) assert axi_ram_inst.read_mem(axi_addr, len(test_data)) == test_data cur_tag = (cur_tag + 1) % 256 yield delay(100) raise StopSimulation return instances()