def CONSTANT(destination, source):
from peachpy.arm.function import active_function
origin = inspect.stack() if active_function.collect_origin else None
instruction = LoadConstantPseudoInstruction(Operand(destination),
Operand(source),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ONCE(register_class, constant, register=None):
if register is None:
origin = inspect.stack(
) if peachpy.arm.function.active_function.collect_origin else None
register = register_class()
instruction = LoadConstantPseudoInstruction(Operand(register),
Operand(constant),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return register
else:
return register
def INITIALIZED(destination):
from peachpy.arm.function import active_function
origin = inspect.stack() if active_function.collect_origin else None
instruction = AssumeInitializedPseudoInstruction(Operand(destination),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ELEMENT(destination, source, ctype, increment_pointer=False):
from peachpy.arm.function import active_function
from peachpy.arm.instructions import Operand
from peachpy.arm.registers import GeneralPurposeRegister, SRegister, DRegister
from peachpy.arm.generic import STR, STRH, STRB, ADD
from peachpy.arm.vfpneon import VSTR
if isinstance(ctype, peachpy.c.Type):
if Operand(destination).is_memory_address():
if Operand(source).is_register():
memory_size = ctype.get_size(active_function.abi)
if isinstance(source, GeneralPurposeRegister):
if ctype.is_integer():
if memory_size == 4:
if increment_pointer:
STR(source, destination, memory_size)
else:
STR(source, destination)
elif memory_size == 2:
if increment_pointer:
STRH(source, destination, memory_size)
else:
STRH(source, destination)
elif memory_size == 1:
if increment_pointer:
STRB(source, destination, memory_size)
else:
STRB(source, destination)
else:
raise ValueError(
"Invalid memory operand size {0}".format(
memory_size))
else:
raise TypeError("Invalid memory operand type")
elif isinstance(source, SRegister):
if ctype.is_floating_point():
if memory_size == 4:
VSTR(source, destination)
if increment_pointer:
address_register = Operand(
destination).get_registers_list()[0]
ADD(address_register, memory_size)
else:
raise ValueError(
"Invalid memory operand size {0}".format(
memory_size))
else:
raise TypeError("Invalid memory operand type")
elif isinstance(source, DRegister):
if ctype.is_floating_point():
if memory_size == 8:
VSTR(source, destination)
if increment_pointer:
address_register = Operand(
destination).get_registers_list()[0]
ADD(address_register, memory_size)
else:
raise ValueError(
"Invalid memory operand size {0}".format(
memory_size))
else:
raise TypeError("Invalid memory operand type")
else:
raise TypeError(
"Source must be a general-purpose register")
else:
raise TypeError("Source must be a register")
else:
raise TypeError("Destination must be a memory operand")
else:
raise TypeError("Type must be a C type")
def ELEMENT(destination, source, ctype, increment_pointer=False):
from peachpy.arm.function import active_function
from peachpy.arm.instructions import Operand
from peachpy.arm.registers import Register, GeneralPurposeRegister, SRegister, DRegister
from peachpy.arm.generic import LDR, LDRH, LDRSH, LDRB, LDRSB, ADD
from peachpy.arm.vfpneon import VLDR
from peachpy import Type
if not isinstance(ctype, Type):
raise TypeError("Type must be a C type")
if isinstance(destination, Register):
raise TypeError("Destination must be a register")
if not Operand(source).is_memory_address():
raise TypeError("Source must be a memory operand")
memory_size = ctype.get_size(active_function.abi)
if isinstance(destination, GeneralPurposeRegister):
if ctype.is_unsigned_integer:
if memory_size == 4:
if increment_pointer:
LDR(destination, source, memory_size)
else:
LDR(destination, source)
elif memory_size == 2:
if increment_pointer:
LDRH(destination, source, memory_size)
else:
LDRH(destination, source)
elif memory_size == 1:
if increment_pointer:
LDRB(destination, source, memory_size)
else:
LDRB(destination, source)
else:
raise ValueError(
"Invalid memory operand size {0}".format(memory_size))
elif ctype.is_signed_integer:
if memory_size == 4:
if increment_pointer:
LDR(destination, source, memory_size)
else:
LDR(destination, source)
elif memory_size == 2:
if increment_pointer:
LDRSH(destination, source, memory_size)
else:
LDRSH(destination, source)
elif memory_size == 1:
if increment_pointer:
LDRSB(destination, source, memory_size)
else:
LDRSB(destination, source)
else:
raise ValueError(
"Invalid memory operand size {0}".format(memory_size))
else:
raise TypeError("Invalid memory operand type")
elif isinstance(destination, SRegister):
if ctype.is_floating_point:
if memory_size == 4:
VLDR(destination, source)
if increment_pointer:
address_register = Operand(
source).get_registers_list()[0]
ADD(address_register, memory_size)
else:
raise ValueError(
"Invalid memory operand size {0}".format(memory_size))
else:
raise TypeError("Invalid memory operand type")
elif isinstance(destination, DRegister):
if ctype.is_floating_point:
if memory_size == 8:
VLDR(destination, source)
if increment_pointer:
address_register = Operand(
source).get_registers_list()[0]
ADD(address_register, memory_size)
else:
raise ValueError(
"Invalid memory operand size {0}".format(memory_size))
else:
raise TypeError("Invalid memory operand type")
else:
raise TypeError("Unsupported destination type")
def RETURN(return_value=None):
instruction = ReturnInstruction(Operand(return_value))
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def LABEL(name):
instruction = LabelQuasiInstruction(Operand(name))
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction