def perform_setup(dut):
'''
Performs the set up of the system.
'''
clkdrv = ClockDriver(interface=Interface(clk=dut.clk),
param_namespace=Namespace(clk=Namespace(period=(5,"ns"))))
rstdrv = ResetDriver(interface=Interface(rst=dut.rst),
param_namespace=Namespace(rst=Namespace(associated_clock=dut.clk)))
regdrv = RegisterDriver(interface=Interface(clk=dut.clk,rst=dut.rst,d=dut.d,vld=dut.vld))
regmon = RegisterMonitor(interface=Interface(clk=dut.clk,rst=dut.rst,q=dut.q))
srcblk = SourceBlock()
ffblk = FlipFlopBlock(init=int(dut.INIT.value),evld=int(dut.EVLD.value),width=int(dut.W.value))
scrblk = ScoreBlock()
astblk = AssertBlock()
srcblk.outport.connect(regdrv.inport)
srcblk.outport.connect(ffblk.inport).outport.connect(scrblk.inports(1)).outport.connect(astblk.inport)
regmon.outport.connect(scrblk.inports(0))
te = Namespace(srcblk=srcblk,width=int(dut.W.value),wait=regmon._synchronize)
yield rstdrv.wait()
raise ReturnValue(te)
def __init__(self, dut):
'''
Constructor. dut is the device-under-test that consists of all the cocotb
SimHandles.
'''
# Create the system agent. The system agent handles setting up the clocks
# and resets.
clkdrv = ClockDriver(
interface=Interface(clk=dut.clk),
param_namespace=Namespace(clk=Namespace(period=(5, "ns"))))
rstdrv = ResetDriver(
interface=Interface(rst=dut.rst),
param_namespace=Namespace(rst=Namespace(
active_mode=1, associated_clock=dut.clk, wait_cycles=32)))
# Create the BusAgents.
getBusInterface = lambda dir, idx: HandshakeInterface(
clk=dut.clk,
rst=dut.rst,
vld=getattr(dut, "{}vldscc".format(dir))[idx],
rdy=getattr(dut, "{}rdyscc".format(dir))[idx],
addr=getattr(dut, "{}addrs".format(dir))[idx],
data=getattr(dut, "{}datascc".format(dir))[idx],
be=getattr(dut, "{}bescc".format(dir))[idx],
op=getattr(dut, "{}opscc".format(dir))[idx])
getBusAgent = lambda idx, passive=False: BusAgent(
baseAddr=int(dut.rdbasescc[idx].value),
wrInterface=getBusInterface(dir="wr", idx=idx),
rdInterface=getBusInterface(dir="rd", idx=idx),
passive=passive)
ccbus = getBusAgent(idx=int(dut.CC_IDX.value))
simrambus = getBusAgent(idx=int(dut.SIMRAM_IDX.value))
simramblk = RamBlock(bpd=int(dut.B_BPD.value))
simramcvt = BusRamConvertBlock(bpd=int(dut.B_BPD.value))
scoreblk = ScoreBlock(name="score")
assertblk = AssertBlock()
# Perform the connections.
simrambus.outport.connect(simramcvt.busInport).ramOutport.connect(
simramblk.inport)
simramblk.outport.connect(simramcvt.ramInport).busOutport.connect(
simrambus.inport)
scoreblk.outport.connect(assertblk.inport)
self.__dut = dut
self.__rstdrv = rstdrv
self.__ccbus = ccbus
self.__log = SimLog("cocotb.te")
self.__scoreblk = scoreblk
def perform_setup(dut, total):
'''
Generates the testbench environment.
'''
T = 4 # Total number of duts.
# Create source block.
srcblk = SourceBlock()
# Create simulation end blocks.
failblk = AssertBlock()
passblk = SucceedBlock()
cntblk = CountBlock(total=total, inputs=T + 1)
# Connect the source block, count block, and pass block.
srcblk.outport.connect(cntblk.inports(0)).outport.connect(passblk.inport)
# Create the agents for each dut.
rst_dict = {}
rstparams_dict = {}
clk_dict = {}
clkparams_dict = {}
wrdrvs = []
rddrvs = []
for each_agent in range(T):
# Get sim handle of fifo.
fifo = getattr(dut, "dut{}".format(each_agent))
# If the FIFO is asynchronous, only the writing
# clock and reset are used.
if int(fifo.EASYNC.value) != 0:
rdclk = fifo.rdclk
rdrst = fifo.rdrst
else:
rdclk = fifo.wrclk
rdrst = fifo.wrrst
# Construct the components.
wrdrv = HandshakeWriteDriver(interface=Interface(clk=fifo.wrclk,
rst=fifo.wrrst,
vld=fifo.wrvld,
rdy=fifo.wrrdy,
data=fifo.wrdata))
wrdatamon = HandshakeMonitor(interface=Interface(clk=fifo.wrclk,
rst=fifo.wrrst,
vld=fifo.wrvld,
rdy=fifo.wrrdy,
data=fifo.wrdata))
rddrv = HandshakeReadDriver(interface=Interface(clk=rdclk,
rst=rdrst,
vld=fifo.rdvld,
rdy=fifo.rdrdy,
data=fifo.rddata))
rdmon = HandshakeMonitor(interface=Interface(clk=rdclk,
rst=rdrst,
vld=fifo.rdvld,
rdy=fifo.rdrdy,
data=fifo.rddata))
# Create the scoreboards.
datscrblk = ScoreBlock(name="dut{}.data".format(each_agent))
# Connect the source block to driver.
srcblk.outport.connect(wrdrv.inport)
# Connect the data scoreboard.
wrdatamon.outport.connect(datscrblk.inports(0)).outport.connect(
failblk.inport)
rdmon.outport.connect(datscrblk.inports(1))
# Connect the read monitor to the count block as well.
rdmon.outport.connect(cntblk.inports(1 + each_agent))
# Pack the reset and clock.
for oper in ["wr", "rd"]:
rst = getattr(fifo, "{}rst".format(oper))
clk = getattr(fifo, "{}clk".format(oper))
rst_name = "dut{}{}rst".format(each_agent, oper)
clk_name = "dut{}{}clk".format(each_agent, oper)
rst_dict[rst_name] = rst
rstparams_dict[rst_name] = Namespace(associated_clock=clk)
clk_dict[clk_name] = clk
clkparams_dict[clk_name] = Namespace(period=(randint(2, 8), "ns"))
# Pack the set allows.
wrdrvs.append(wrdrv)
rddrvs.append(rddrv)
# Generate the system agents.
clkdrv = ClockDriver(interface=Interface(**clk_dict),
param_namespace=Namespace(**clkparams_dict))
rstdrv = ResetDriver(interface=Interface(**rst_dict),
param_namespace=Namespace(**rstparams_dict))
# Create the testbench environment namespace.
te = Namespace(
source=srcblk,
setwrallow=lambda x: [setattr(wrdrv, "allow", x) for wrdrv in wrdrvs],
setrdallow=lambda x: [setattr(rddrv, "allow", x) for rddrv in rddrvs])
# Yield until all reset have been de-asserted.
yield rstdrv.wait()
# Returnthe testbench environment for the tests.
raise ReturnValue(te)
def __init__(self,
dut,
wrStartAllow=AlwaysAllow,
rdStartAllow=AlwaysAllow):
'''
Constructor. dut is the device-under-test that consists of all the cocotb
SimHandles.
'''
# Create the agents and models.
DUT_TOTAL = int(dut.DUT_TOTAL.value)
wrdrvs = []
rddrvs = []
rdmons = []
modelblks = []
scoreblks = []
clkintrs = {}
clkparams = {}
rstintrs = {}
rstparams = {}
for eachDut in range(DUT_TOTAL):
# Acquire useful values.
specificDut = getattr(dut, "dut{}".format(eachDut))
EASYNC = int(specificDut.EASYNC.value)
wrPeriod = (randint(3, 10), "ns")
rdPeriod = wrPeriod if EASYNC == 0 else (randint(3, 10), "ns")
W = int(specificDut.W.value)
MULT = int(specificDut.MULT.value)
# Collect system parameters.
clkintrs["wrclk{}".format(eachDut)] = specificDut.wrclk
clkintrs["rdclk{}".format(eachDut)] = specificDut.rdclk
clkparams["wrclk{}".format(eachDut)] = Namespace(period=wrPeriod)
clkparams["rdclk{}".format(eachDut)] = Namespace(period=rdPeriod)
rstintrs["wrrst{}".format(eachDut)] = specificDut.wrrst
rstintrs["rdrst{}".format(eachDut)] = specificDut.rdrst
rstparams["wrrst{}".format(eachDut)] = Namespace(
active_mode=1,
associated_clock=specificDut.wrclk,
wait_cycles=32)
rstparams["rdrst{}".format(eachDut)] = Namespace(
active_mode=1,
associated_clock=specificDut.rdclk,
wait_cycles=32)
# Create the agents.
wrdrv = HandshakeWriteDriver(interface=HandshakeInterface(
data=specificDut.wrdata,
vld=specificDut.wrvld,
rdy=specificDut.wrrdy,
clk=specificDut.wrclk,
rst=specificDut.wrrst),
allow=wrStartAllow)
rddrv = HandshakeReadDriver(interface=HandshakeInterface(
data=specificDut.rddata,
vld=specificDut.rdvld,
rdy=specificDut.rdrdy,
clk=specificDut.rdclk,
rst=specificDut.rdrst),
allow=rdStartAllow)
rdmon = HandshakeMonitor(interface=rddrv._interface)
# Create the blocks.
modelblk = UpFifoModel(width=W, mult=MULT)
scoreblk = ScoreBlock(name="score.dut{}".format(eachDut))
# Store blocks.
wrdrvs.append(wrdrv)
rddrvs.append(rddrv)
rdmons.append(rdmon)
scoreblks.append(scoreblk)
modelblks.append(modelblk)
# Create the system agents.
clkdrv = ClockDriver(interface=Interface(**clkintrs),
param_namespace=Namespace(**clkparams))
rstdrv = ResetDriver(interface=Interface(**rstintrs),
param_namespace=Namespace(**rstparams))
# Create the blocks.
sourceblk = SourceBlock()
assertblk = AssertBlock(inputs=DUT_TOTAL)
# Perform the connections.
for eachDut, (wrdrv, modelblk, rdmon, scoreblk) in enumerate(
zip(wrdrvs, modelblks, rdmons, scoreblks)):
sourceblk.outport.connect(wrdrv.inport)
sourceblk.outport.connect(modelblk.inport)
rdmon.outport.connect(scoreblk.inports(0))
modelblk.outport.connect(scoreblk.inports(1))
scoreblk.outport.connect(assertblk.inports(eachDut))
self.__dut = dut
self.__rstdrv = rstdrv
self.__wrdrvs = wrdrvs
self.__rddrvs = rddrvs
self.__sourceblk = sourceblk
self.__log = SimLog("cocotb.te")
def __init__(self, dut):
'''
Constructor. dut is the device-under-test that consists of all the cocotb
SimHandles.
'''
self.__rstDrvs = []
self.__log = SimLog("cocotb.log")
#---------------------------------------------------------------------#
# Configure ipmaxi_full_inst
ipmaxiFullInst = dut.ipmaxi_full_inst
# Create the agents and blocks...
ClockDriver(interface=Interface(clk=ipmaxiFullInst.clk),
param_namespace=Namespace(clk=Namespace(period=(10,
"ns"))),
name="ipmaxiFullInst")
rstDrv = ResetDriver(interface=Interface(rst=ipmaxiFullInst.rst),
param_namespace=Namespace(
active_mode=1,
associated_clock=ipmaxiFullInst.clk,
wait_cycles=32))
self.__rstDrvs.append(rstDrv)
busAgts = []
respMons = []
respScrBlks = []
TOTAL_CCTBPLBS = int(ipmaxiFullInst.TOTAL_CCTBPLBS.value)
B_AW = int(ipmaxiFullInst.B_AW.value)
for eachBusAgt in range(TOTAL_CCTBPLBS):
baseAddr = (int(ipmaxiFullInst.B_BASES.value) >>
(eachBusAgt * B_AW)) & ((1 << B_AW) - 1)
busAgt = BusAgent(baseAddr=baseAddr,
wrInterface=HandshakeInterface(
addr=ipmaxiFullInst.wraddr[eachBusAgt],
data=ipmaxiFullInst.wrdata[eachBusAgt],
be=ipmaxiFullInst.wrbe[eachBusAgt],
op=ipmaxiFullInst.wrop[eachBusAgt],
vld=ipmaxiFullInst.wrvld[eachBusAgt],
rdy=ipmaxiFullInst.wrrdy[eachBusAgt],
clk=ipmaxiFullInst.clk,
rst=ipmaxiFullInst.rst),
rdInterface=HandshakeInterface(
addr=ipmaxiFullInst.rdaddr[eachBusAgt],
data=ipmaxiFullInst.rddata[eachBusAgt],
be=ipmaxiFullInst.rdbe[eachBusAgt],
op=ipmaxiFullInst.rdop[eachBusAgt],
vld=ipmaxiFullInst.rdvld[eachBusAgt],
rdy=ipmaxiFullInst.rdrdy[eachBusAgt],
clk=ipmaxiFullInst.clk,
rst=ipmaxiFullInst.rst))
respMon = HandshakeMonitor(interface=HandshakeInterface(
resp=ipmaxiFullInst.respresp[eachBusAgt],
op=ipmaxiFullInst.respop[eachBusAgt],
vld=ipmaxiFullInst.respvld[eachBusAgt],
rdy=ipmaxiFullInst.resprdy[eachBusAgt],
clk=ipmaxiFullInst.clk,
rst=ipmaxiFullInst.rst))
respScrBlk = ScoreBlock(name="resp{}".format(eachBusAgt))
busAgts.append(busAgt)
respMons.append(respMon)
respScrBlks.append(respScrBlk)
respScrBlk = ScoreBlock(name="resp")
busScrBlk = ScoreBlock(name="bus")
assertBlk = AssertBlock()
# Peform the connections...
for respMon, respScrBlk in zip(respMons, respScrBlks):
respMon.outport.connect(
SwissBlock(lambda trans: int(trans.resp.value)).inport
).outport.connect(respScrBlk.inports(0))
respMon.outport.connect(
SwissBlock(lambda trans: 0).inport).outport.connect(
respScrBlk.inports(1))
respScrBlk.outport.connect(assertBlk.inport)
busScrBlk.outport.connect(assertBlk.inport)
# Assign the private members...
self.__ipmaxiFullInstBusAgts = busAgts
self.__ipmaxiFullInstBusScrBlk = busScrBlk
#---------------------------------------------------------------------#
# Configure ipmaxi_wr_inst
ipmaxiWrInst = dut.ipmaxi_wr_inst
ClockDriver(interface=Interface(clk=ipmaxiWrInst.clk),
param_namespace=Namespace(clk=Namespace(period=(10,
"ns"))),
name="ipmaxiWrInst")
rstDrv = ResetDriver(interface=Interface(rst=ipmaxiWrInst.rst),
param_namespace=Namespace(
active_mode=1,
associated_clock=ipmaxiWrInst.clk,
wait_cycles=32))
self.__rstDrvs.append(rstDrv)
wrDrv = HandshakeWriteDriver(
interface=HandshakeInterface(addr=ipmaxiWrInst.wraddr,
data=ipmaxiWrInst.wrdata,
be=ipmaxiWrInst.wrbe,
vld=ipmaxiWrInst.wrvld,
rdy=ipmaxiWrInst.wrrdy,
clk=ipmaxiWrInst.clk,
rst=ipmaxiWrInst.rst))
HandshakeReadDriver(
interface=HandshakeInterface(resp=ipmaxiWrInst.bresp,
vld=ipmaxiWrInst.bvalid,
rdy=ipmaxiWrInst.bready,
clk=ipmaxiWrInst.clk,
rst=ipmaxiWrInst.rst))
self.__ipmaxiWrInstWrDrv = wrDrv
#---------------------------------------------------------------------#
# Configure ipmaxi_rdwr_inst
ipmaxiRdWrInst = dut.ipmaxi_rdwr_inst
ClockDriver(interface=Interface(clk=ipmaxiRdWrInst.clk),
param_namespace=Namespace(clk=Namespace(period=(10,
"ns"))),
name="ipmaxiRdWrInst")
rstDrv = ResetDriver(interface=Interface(rst=ipmaxiRdWrInst.rst),
param_namespace=Namespace(
active_mode=1,
associated_clock=ipmaxiRdWrInst.clk,
wait_cycles=32))
self.__rstDrvs.append(rstDrv)
wrWrDrv = HandshakeWriteDriver(
interface=HandshakeInterface(addr=ipmaxiRdWrInst.wr_wraddr,
data=ipmaxiRdWrInst.wr_wrdata,
be=ipmaxiRdWrInst.wr_wrbe,
vld=ipmaxiRdWrInst.wr_wrvld,
rdy=ipmaxiRdWrInst.wr_wrrdy,
clk=ipmaxiRdWrInst.clk,
rst=ipmaxiRdWrInst.rst))
rdWrDrv = HandshakeWriteDriver(
interface=HandshakeInterface(addr=ipmaxiRdWrInst.rd_wraddr,
data=ipmaxiRdWrInst.rd_wrdata,
vld=ipmaxiRdWrInst.rd_wrvld,
rdy=ipmaxiRdWrInst.rd_wrrdy,
clk=ipmaxiRdWrInst.clk,
rst=ipmaxiRdWrInst.rst))
rdRdDrv = HandshakeReadDriver(
interface=HandshakeInterface(addr=ipmaxiRdWrInst.rd_rdaddr,
data=ipmaxiRdWrInst.rd_rddata,
resp=ipmaxiRdWrInst.rd_rdresp,
vld=ipmaxiRdWrInst.rd_rdvld,
rdy=ipmaxiRdWrInst.rd_rdrdy,
clk=ipmaxiRdWrInst.clk,
rst=ipmaxiRdWrInst.rst))
HandshakeReadDriver(
interface=HandshakeInterface(resp=ipmaxiRdWrInst.bresp,
vld=ipmaxiRdWrInst.bvalid,
rdy=ipmaxiRdWrInst.bready,
clk=ipmaxiRdWrInst.clk,
rst=ipmaxiRdWrInst.rst))
rdRdMon = HandshakeMonitor(interface=rdRdDrv._interface)
rdPrBlk = PrintBlock(name="ipmaxiRdWrInst")
rdRdMon.outport.connect(rdPrBlk.inport)
self.__ipmaxiRdWrInstWrWrDrv = wrWrDrv
self.__ipmaxiRdWrInstRdWrDrv = rdWrDrv
#---------------------------------------------------------------------#
# Configure ipmaxi_single_inst
ipmaxiSingleInst = dut.ipmaxi_single_inst
ClockDriver(interface=Interface(clk=ipmaxiSingleInst.clk),
param_namespace=Namespace(clk=Namespace(period=(10,
"ns"))),
name="ipmaxiSingleInst")
rstDrv = ResetDriver(interface=Interface(rst=ipmaxiSingleInst.rst),
param_namespace=Namespace(
active_mode=1,
associated_clock=ipmaxiSingleInst.clk,
wait_cycles=32))
self.__rstDrvs.append(rstDrv)
busAgt = BusAgent(
baseAddr=0x00000000,
wrInterface=HandshakeInterface(addr=ipmaxiSingleInst.wraddr,
data=ipmaxiSingleInst.wrdata,
be=ipmaxiSingleInst.wrbe,
op=ipmaxiSingleInst.wrop,
vld=ipmaxiSingleInst.wrvld,
rdy=ipmaxiSingleInst.wrrdy,
clk=ipmaxiSingleInst.clk,
rst=ipmaxiSingleInst.rst),
rdInterface=HandshakeInterface(addr=ipmaxiSingleInst.rdaddr,
data=ipmaxiSingleInst.rddata,
be=ipmaxiSingleInst.rdbe,
op=ipmaxiSingleInst.rdop,
vld=ipmaxiSingleInst.rdvld,
rdy=ipmaxiSingleInst.rdrdy,
clk=ipmaxiSingleInst.clk,
rst=ipmaxiSingleInst.rst))
self.__ipmaxiSingleInstBusAgt = busAgt
#---------------------------------------------------------------------#
# Other assignments
self.__dut = dut
def perform_setup(dut):
# Create clock and reset drivers.
fifo = dut.dut
clkdrv = ClockDriver(interface=Interface(wrclk=fifo.wrclk,
rdclk=fifo.rdclk),
param_namespace=Namespace(wrclk=Namespace(period=(randint(1,10),"ns")),
rdclk=Namespace(period=(randint(1,10),"ns"))))
rstdrv = ResetDriver(interface=Interface(wrrst=fifo.wrrst,
rdrst=fifo.rdrst),
param_namespace=Namespace(wrrst=Namespace(associated_clock=fifo.wrclk),
rdrst=Namespace(associated_clock=fifo.rdclk)))
# Create the components.
wrdrv = HandshakeWriteDriver(interface=Interface(clk=fifo.wrclk,
rst=fifo.wrrst,
vld=fifo.wrvld,
rdy=fifo.wrrdy,
data=fifo.wrdata))
rdintr = Interface(clk=fifo.rdclk,
rst=fifo.rdrst,
vld=fifo.rdvld,
rdy=fifo.rdrdy,
data=fifo.rddata)
rddrv = HandshakeReadDriver(interface=rdintr)
rdmon = HandshakeMonitor(interface=rdintr)
# Create the block that determines the
# simulation's end condition.
cntns = Namespace(count=0,total=0)
def cntfun(ignore):
cntns.count += 1
return cntns.count==cntns.total
cntblk = SwissBlock(trans_func=cntfun)
# Generate a synchronize coroutine for waiting.
wrwait = RegisterInterface(rst=fifo.wrrst,clk=fifo.wrclk)._synchronize
# Create the block intended for logging.
logobj = SimLog("cocotb.log")
logblk = SwissBlock(trans_func=lambda x : logobj.info("{}".format(x)))
# Other nodes.
source = SourceBlock() # Where data is written.
score = ScoreBlock()
check = AssertBlock()
end = SucceedBlock()
# Connect the blocks together to create the system.
source.outport.connect(wrdrv.inport)
source.outport.connect(score.inports(0)).outport.connect(check.inport)
rdmon.outport.connect(score.inports(1))
rdmon.outport.connect(cntblk.inport).outport.connect(end.inport)
# Wrap up the objects needed for each test.
te = Namespace(source=source,width=int(fifo.W.value),cntns=cntns,log=logobj,
wrwait=wrwait,
setwrallow=lambda x : setattr(wrdrv,"allow",x),
setrdallow=lambda x : setattr(rddrv,"allow",x))
yield rstdrv.wait()
raise ReturnValue(te)
def perform_setup(dut):
TDUTS = 1 # Total number of duts.
# The following structures need to be created
# prior to another initialization.
sizes_dict = {}
gat_blk_dict = {}
src_blk_dict = {}
drv_blk_dict = {}
rst_sig_dict = {}
rst_prm_dict = {}
clk_sig_dict = {}
clk_prm_dict = {}
# Perform the following operations on each dut.
for each_dut in range(TDUTS):
# Get SimHandleBase of the dut and necessary parameters..
bus = getattr(dut, "dut{}".format(each_dut)) # SimHandleBase
bwrs = int(bus.B_WRS.value) # Total write interfaces
brds = int(bus.B_RDS.value) # Total read interfaces
bclkprdw = int(bus.B_CLKPRDW.value) # Gets the clock period width.
baw = int(bus.B_AW.value) # Address width
bwd = int(bus.B_DW.value) # Data width
ast_blk = AssertBlock(
) # Used for failing test if hardware doesn't match hardware.
sizes_dict[(each_dut, "wr")] = bwrs
sizes_dict[(each_dut, "rd")] = brds
# Create the bus model.
out_prms_lst = []
for idx in range(brds):
bases = int(bus.B_BASES.value)
sizes = int(bus.B_SIZES.value)
base = (bases >> (baw * idx)) & ((1 << baw) - 1)
size = (sizes >> (baw * idx)) & ((1 << baw) - 1)
out_prms_lst.append(Namespace(base=base, size=size))
mdl_blk = BusCrossBlock(inputs=bwrs,
outputs=brds,
outport_params=out_prms_lst)
# Pack clock/resets and create agents.
synclst = [("wr", each_sync) for each_sync in range(bwrs)]
synclst.extend([("rd", each_sync) for each_sync in range(brds)])
for intr, idx in synclst:
# Acquire signals
rst_sig = getattr(bus, "{}rstscc".format(intr))[idx]
clk_sig = getattr(bus, "{}clkscc".format(intr))[idx]
vld_sig = getattr(bus, "{}vldscc".format(intr))[idx]
rdy_sig = getattr(bus, "{}rdyscc".format(intr))[idx]
data_sig = getattr(bus, "{}datas".format(intr))[idx]
addr_sig = getattr(bus, "{}addrs".format(intr))[idx]
# Create the agents.
inter = Interface(rst=rst_sig,
clk=clk_sig,
vld=vld_sig,
rdy=rdy_sig,
data=data_sig,
addr=addr_sig)
drv = HandshakeWriteDriver(
interface=inter) if intr == "wr" else HandshakeReadDriver(
interface=inter)
mon = HandshakeMonitor(interface=inter)
# Store the drivers in order to allow for changes to flow control.
drv_blk_dict[(each_dut, idx, intr)] = drv
# Create name identifiers for clocks and resets.
rst_nme = "dut{}{}rst{}".format(each_dut, intr, idx)
clk_nme = "dut{}{}clk{}".format(each_dut, intr, idx)
# Get periods.
clkprds = int(
getattr(bus, "B_{}CLKPRDS".format(intr.upper())).value)
prdval = (clkprds >> (bclkprdw * idx)) & ((1 << bclkprdw) - 1)
# Store the data in dictionaries.
rst_sig_dict[rst_nme] = rst_sig
rst_prm_dict[rst_nme] = Namespace(associated_clock=clk_sig)
clk_sig_dict[clk_nme] = clk_sig
clk_prm_dict[clk_nme] = Namespace(period=(prdval, "ns"))
# Operations associated with only the writing interface.
if intr == "wr":
# Create blocks.
src_blk = SourceBlock()
msk_blk = SwissBlock(trans_func=lambda trans: ChangeWidth(
trans=trans, aw=baw, dw=bwd))
ComposedBlock(src_blk, msk_blk, drv)
msk_blk.outport.connect(mdl_blk.inports(idx))
#msk_blk.outport.connect(PrintBlock("bus{}.wr{}".format(each_dut,idx)).inport)
# Store the source blocks.
src_blk_dict[(each_dut, idx)] = src_blk
# Operations associated with only the reading interface.
if intr == "rd":
# Store the base and size parmateres.
bases = int(bus.B_BASES.value)
sizes = int(bus.B_SIZES.value)
base = (bases >> (baw * idx)) & ((1 << baw) - 1)
size = (sizes >> (baw * idx)) & ((1 << baw) - 1)
out_prms_lst.append(Namespace(base=base, size=size))
# Create a scoreboard for each reading interface.
sb_blk = ScoreBlock(name="bus{}.rd{}".format(each_dut, idx))
cvt_blk = SwissBlock(trans_func=BinaryToInt)
gat_exp_blk = GatherBlock()
gat_act_blk = GatherBlock()
# Perform connections. The gather blocks are necessary to ensure
# sets of data are compared, this way order can be ignored.
mdl_blk.outports(idx).connect(
gat_exp_blk.inport).outport.connect(sb_blk.inports(0))
ComposedBlock(mon, cvt_blk,
gat_act_blk).outport.connect(sb_blk.inports(1))
ComposedBlock(sb_blk, ast_blk)
#mon.outport.connect(PrintBlock("bus{}.rd{}".format(each_dut,idx)).inport)
# Store the gather blocks so that the user can specify when a comparison
# should occur.
gat_blk_dict[(each_dut, idx, "exp")] = gat_exp_blk
gat_blk_dict[(each_dut, idx, "act")] = gat_act_blk
# Generate the system agents.
clk_drv = ClockDriver(interface=Interface(**clk_sig_dict),
param_namespace=Namespace(**clk_prm_dict))
rst_drv = ResetDriver(interface=Interface(**rst_sig_dict),
param_namespace=Namespace(**rst_prm_dict))
# Yield until all resets have been de-asserted.
yield rst_drv.wait()
# Create testbench environment namespace.
te = Namespace(sources=lambda bus, idx: src_blk_dict[(bus, idx)],
gathers=lambda bus, idx, exp_act: gat_blk_dict[
(bus, idx, exp_act)],
drivers=lambda bus, idx, wr_rd: drv_blk_dict[
(bus, idx, wr_rd)],
buses=TDUTS,
inputs=lambda bus: sizes_dict[(bus, "wr")],
outputs=lambda bus: sizes_dict[(bus, "rd")])
raise ReturnValue(te)