def runTest(self):
        globals.init_openram("config_20_{0}".format(OPTS.tech_name))

        import precharge_array
        import tech

        debug.info(2, "Checking 1 column precharge")
        OPTS.check_lvsdrc = False
        pc = precharge_array.precharge_array(name="precharge_array",
                                             columns=1,
                                             ptx_width=tech.drc["minwidth_tx"],
                                             beta=2)
        OPTS.check_lvsdrc = True
        self.local_check(pc)

        debug.info(2, "Checking 3 column precharge")
        OPTS.check_lvsdrc = False
        pc = precharge_array.precharge_array(name="precharge_array",
                                             columns=3,
                                             ptx_width=tech.drc["minwidth_tx"],
                                             beta=2)
        OPTS.check_lvsdrc = True
        self.local_check(pc)

        globals.end_openram()
    def runTest(self):
        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
        import precharge_array

        # check precharge array in single port
        debug.info(2, "Checking 3 column precharge")
        pc = precharge_array.precharge_array(name="pre1", columns=3)
        self.local_check(pc)

        # check precharge array in multi-port
        OPTS.bitcell = "bitcell_1rw_1r"
        OPTS.num_rw_ports = 1
        OPTS.num_r_ports = 1
        OPTS.num_w_ports = 0

        factory.reset()
        debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell")
        pc = precharge_array.precharge_array(name="pre2",
                                             columns=3,
                                             bitcell_bl="bl0",
                                             bitcell_br="br0")
        self.local_check(pc)

        # debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)")
        # pc = precharge_array.precharge_array(name="pre3", columns=3, bitcell_bl="bl0", bitcell_br="br0")
        # self.local_check(pc)

        # debug.info(2, "Checking 3 column precharge array for pbitcell (outermost connections)")
        # pc = precharge_array.precharge_array(name="pre4", columns=3, bitcell_bl="bl2", bitcell_br="br2")
        # self.local_check(pc)

        globals.end_openram()
    def runTest(self):
        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
        import precharge_array
        import tech

        debug.info(2, "Checking 3 column precharge")
        pc = precharge_array.precharge_array(columns=3)
        self.local_check(pc)

        if OPTS.multiport_check:
            debug.info(2, "Checking precharge array for pbitcell")
            OPTS.bitcell = "pbitcell"
            OPTS.num_rw_ports = 1
            OPTS.num_r_ports = 1
            OPTS.num_w_ports = 1

            pc = precharge_array.precharge_array(columns=3,
                                                 bitcell_bl="bl0",
                                                 bitcell_br="br0")
            self.local_check(pc)

            pc = precharge_array.precharge_array(columns=3,
                                                 bitcell_bl="bl1",
                                                 bitcell_br="br1")
            self.local_check(pc)

            pc = precharge_array.precharge_array(columns=3,
                                                 bitcell_bl="bl2",
                                                 bitcell_br="br2")
            self.local_check(pc)

        globals.end_openram()
Exemple #4
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    def runTest(self):
        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
        OPTS.check_lvsdrc = False

        import precharge_array
        import tech

        debug.info(2, "Checking 3 column precharge")
        pc = precharge_array.precharge_array(columns=3)
        self.local_check(pc)

        OPTS.check_lvsdrc = True
        globals.end_openram()
    def runTest(self):
        globals.init_AMC("config_20_{0}".format(OPTS.tech_name))

        global calibre
        import calibre
        OPTS.check_lvsdrc = False

        import precharge_array

        debug.info(2, "Checking 4 column precharge")
        pc = precharge_array.precharge_array(columns=4)
        self.local_check(pc)

        # return it back to it's normal state
        OPTS.check_lvsdrc = True
        globals.end_AMC()