# This makes the fuzzer compilation more robust against failures.
INCREMENT = os.getenv('CLBN', 0)
CLBN = 40 + int(INCREMENT)
print('//Requested CLBs: %s' % str(CLBN))
def gen_slices():
for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
['SLICEL', 'SLICEM']):
yield site_name
DIN_N = CLBN * 8
DOUT_N = CLBN * 8
verilog.top_harness(DIN_N, DOUT_N)
f = open('params.csv', 'w')
f.write('module,loc,n,def_a\n')
slices = gen_slices()
print('module roi(input clk, input [%d:0] din, output [%d:0] dout);' %
(DIN_N - 1, DOUT_N - 1))
for i in range(CLBN):
bel = ''
module = 'clb_N5FFMUX'
n = random.randint(0, 3)
def_a = random.randint(0, 1)
loc = next(slices)
print(' %s' % module)
def run():
verilog.top_harness(48, 48)
print('module roi(input clk, input [47:0] din, output [47:0] dout);')
data = {}
data['instances'] = []
sites = list(gen_sites())
for i, (tile, site) in enumerate(sites):
synthesis = '(* KEEP, DONT_TOUCH, LOC = "%s" *)' % (site)
module = 'DSP48E1'
instance = 'INST_%s' % (site)
ports = {}
params = {}
ports['A'] = '{30{1\'b1}}'
ports['ACIN'] = '{30{1\'b1}}'
ports['ACOUT'] = '30\'b0'
ports['ALUMODE'] = 'din[3:0]'
ports['B'] = '{18{1\'b1}}'
ports['BCIN'] = '{18{1\'b1}}'
ports['BCOUT'] = '18\'b0'
ports['C'] = '{48{1\'b1}}'
ports['CARRYCASCIN'] = '1\'b1'
ports['CARRYCASCOUT'] = '1\'b0'
ports['CARRYIN'] = 'din[4]'
ports['CARRYINSEL'] = '3\'b000'
ports['CARRYOUT'] = '4\'b0'
ports['CEA1'] = '1\'b1'
ports['CEA2'] = '1\'b1'
ports['CEAD'] = '1\'b1'
ports['CEALUMODE'] = '1\'b1'
ports['CEB1'] = '1\'b1'
ports['CEB2'] = '1\'b1'
ports['CEC'] = '1\'b1'
ports['CECARRYIN'] = '1\'b1'
ports['CECTRL'] = '1\'b1'
ports['CED'] = '1\'b1'
ports['CEINMODE'] = '1\'b1'
ports['CEM'] = '1\'b1'
ports['CEP'] = '1\'b1'
ports['CLK'] = 'clk'
ports['D'] = '{25{1\'b1}}'
ports['INMODE'] = 'din[9:5]'
#ports['MULTISIGNIN'] = '1\'b1'
#ports['MULTISIGNOUT'] = '1\'b0'
ports['OPMODE'] = 'din[16:10]'
ports['OVERFLOW'] = '1\'b0'
ports['P'] = '48\'b0'
ports['PATTERNBDETECT'] = '1\'b0'
ports['PATTERNDETECT'] = '1\'b0'
ports['PCIN'] = '{48{1\'b1}}'
ports['PCOUT'] = '48\'b0'
ports['RSTA'] = '1\'b1'
ports['RSTALLCARRYIN'] = '1\'b1'
ports['RSTALUMODE'] = '1\'b1'
ports['RSTB'] = '1\'b1'
ports['RSTC'] = '1\'b1'
ports['RSTCTRL'] = '1\'b1'
ports['RSTD'] = '1\'b1'
ports['RSTINMODE'] = '1\'b1'
ports['RSTM'] = '1\'b1'
ports['RSTP'] = '1\'b1'
ports['UNDERFLOW'] = '1\'b0'
params['ADREG'] = fuzz((0, 1))
params['ALUMODEREG'] = fuzz((0, 1))
params['AREG'] = fuzz((0, 1, 2))
if params['AREG'] == 0 or params['AREG'] == 1:
params['ACASCREG'] = params['AREG']
else:
params['ACASCREG'] = fuzz((1, 2))
params['BREG'] = fuzz((0, 1, 2))
if params['BREG'] == 0 or params['BREG'] == 1:
params['BCASCREG'] = params['BREG']
else:
params['BCASCREG'] = fuzz((1, 2))
params['CARRYINREG'] = fuzz((0, 1))
params['CARRYINSELREG'] = fuzz((0, 1))
params['CREG'] = fuzz((0, 1))
params['DREG'] = fuzz((0, 1))
params['INMODEREG'] = fuzz((0, 1))
params['OPMODEREG'] = fuzz((0, 1))
params['PREG'] = fuzz((0, 1))
params['A_INPUT'] = verilog.quote(fuzz(('DIRECT', 'CASCADE')))
params['B_INPUT'] = verilog.quote(fuzz(('DIRECT', 'CASCADE')))
params['USE_DPORT'] = verilog.quote(fuzz(('TRUE', 'FALSE')))
params['USE_SIMD'] = verilog.quote(fuzz(('ONE48', 'TWO24', 'FOUR12')))
params['USE_MULT'] = verilog.quote(
'NONE' if params['USE_SIMD'] != verilog.quote('ONE48') else fuzz((
'NONE', 'MULTIPLY', 'DYNAMIC')))
params['MREG'] = 0 if params['USE_MULT'] == verilog.quote(
'NONE') else fuzz((0, 1))
params['AUTORESET_PATDET'] = verilog.quote(
fuzz(('NO_RESET', 'RESET_MATCH', 'RESET_NOT_MATCH')))
params['MASK'] = '48\'d%s' % fuzz(48)
params['PATTERN'] = '48\'d%s' % fuzz(48)
params['SEL_MASK'] = verilog.quote(
fuzz(('MASK', 'C', 'ROUNDING_MODE1', 'ROUNDING_MODE2')))
params['USE_PATTERN_DETECT'] = verilog.quote(
fuzz(('NO_PATDET', 'PATDET')))
params['IS_ALUMODE_INVERTED'] = fuzz(4)
params['IS_CARRYIN_INVERTED'] = fuzz((0, 1))
params['IS_CLK_INVERTED'] = fuzz((0, 1))
params['IS_INMODE_INVERTED'] = fuzz(5)
params['IS_OPMODE_INVERTED'] = fuzz(7)
verilog.instance(synthesis + ' ' + module, instance, ports, params)
params['TILE'] = tile
params['SITE'] = site
data['instances'].append(params)
with open('params.json', 'w') as fp:
json.dump(data, fp)
print("endmodule")
def main():
brams = list(gen_brams())
DUTN = len(brams)
DIN_N = DUTN * 8
DOUT_N = DUTN * 8
verilog.top_harness(DIN_N, DOUT_N)
f = open('params.jl', 'w')
f.write('module,loc,params\n')
print(
'module roi(input clk, input [%d:0] din, output [%d:0] dout);' %
(DIN_N - 1, DOUT_N - 1))
for loci, (site_type, site) in enumerate(brams):
modname, ports, params = {
'RAMB18E1': place_bram18,
#'RAMBFIFO36E1': place_bram36,
}[site_type](site, loci)
verilog.instance(modname, 'inst_%u' % loci, ports, params=params)
j = {'module': modname, 'i': loci, 'params': params}
f.write('%s\n' % (json.dumps(j)))
print('')
f.close()
print(
'''endmodule
// ---------------------------------------------------------------------
''')
# RAMB18E1
print(
'''
module my_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
parameter RAM_MODE = "TDP";
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE";
parameter RSTREG_PRIORITY_A = "RSTREG";
parameter RSTREG_PRIORITY_B = "RSTREG";
parameter DOA_REG = 1'b0;
parameter DOB_REG = 1'b0;
parameter SRVAL_A = 18'b0;
parameter SRVAL_B = 18'b0;
parameter INIT_A = 18'b0;
parameter INIT_B = 18'b0;
parameter READ_WIDTH_A = 0;
parameter READ_WIDTH_B = 0;
parameter WRITE_WIDTH_A = 0;
parameter WRITE_WIDTH_B = 0;
''')
print('''\
(* LOC=LOC *)
RAMB18E1 #(''')
for i in range(8):
print(" .INITP_%02X(256'b0)," % (i, ))
print('')
for i in range(0x40):
print(" .INIT_%02X(256'b0)," % (i, ))
print('')
print(
'''
.IS_CLKARDCLK_INVERTED(IS_CLKARDCLK_INVERTED),
.IS_CLKBWRCLK_INVERTED(IS_CLKBWRCLK_INVERTED),
.IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED),
.IS_ENBWREN_INVERTED(IS_ENBWREN_INVERTED),
.IS_RSTRAMARSTRAM_INVERTED(IS_RSTRAMARSTRAM_INVERTED),
.IS_RSTRAMB_INVERTED(IS_RSTRAMB_INVERTED),
.IS_RSTREGARSTREG_INVERTED(IS_RSTREGARSTREG_INVERTED),
.IS_RSTREGB_INVERTED(IS_RSTREGB_INVERTED),
.RAM_MODE(RAM_MODE),
.WRITE_MODE_A(WRITE_MODE_A),
.WRITE_MODE_B(WRITE_MODE_B),
.DOA_REG(DOA_REG),
.DOB_REG(DOB_REG),
.SRVAL_A(SRVAL_A),
.SRVAL_B(SRVAL_B),
.INIT_A(INIT_A),
.INIT_B(INIT_B),
.READ_WIDTH_A(READ_WIDTH_A),
.READ_WIDTH_B(READ_WIDTH_B),
.WRITE_WIDTH_A(WRITE_WIDTH_A),
.WRITE_WIDTH_B(WRITE_WIDTH_B),
.RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG),
.RSTREG_PRIORITY_A(RSTREG_PRIORITY_A),
.RSTREG_PRIORITY_B(RSTREG_PRIORITY_B)
) ram (
.CLKARDCLK(din[0]),
.CLKBWRCLK(din[1]),
.ENARDEN(din[2]),
.ENBWREN(din[3]),
.REGCEAREGCE(din[4]),
.REGCEB(din[5]),
.RSTRAMARSTRAM(din[6]),
.RSTRAMB(din[7]),
.RSTREGARSTREG(din[0]),
.RSTREGB(din[1]),
.ADDRARDADDR(din[2]),
.ADDRBWRADDR(din[3]),
.DIADI(din[4]),
.DIBDI(din[5]),
.DIPADIP(din[6]),
.DIPBDIP(din[7]),
.WEA(1'b0),
.WEBWE(din[1]),
.DOADO(dout[0]),
.DOBDO(dout[1]),
.DOPADOP(dout[2]),
.DOPBDOP(dout[3]));
endmodule
''')
def generate_netlist(params):
DUTN = len(params)
DIN_N = DUTN * 32
DOUT_N = DUTN * 32
string_output = io.StringIO()
any_bscan = False
any_icap = False
usr_access_on = False
capture_on = False
startup_on = False
frame_ecc_on = False
dcireset_on = False
luts = lut_maker.LutMaker()
verilog.top_harness(DIN_N, DOUT_N)
print(
'''
module roi(input clk, input [%d:0] din, output [%d:0] dout);''' %
(DIN_N - 1, DOUT_N - 1))
for loci, param in enumerate(params):
ports = {
'din': 'din[{} +: 8]'.format(8 * loci),
'dout': 'dout[{} +: 8]'.format(8 * loci),
'clk': 'clk'
}
if param["site_type"] in "BSCAN":
ports = {
'din':
'{{din[{} +: 7],{}}}'.format(
8 * loci + 1, luts.get_next_output_net()),
'dout':
'{{dout[{} +: 7],{}}}'.format(
8 * loci + 1, luts.get_next_input_net()),
'clk':
'clk'
}
any_bscan = True
elif param["site_type"] in ["ICAP"]:
any_icap = True
elif param["site_type"] in ["CAPTURE"]:
capture_on = True
elif param["site_type"] in ["STARTUP"]:
startup_on = True
elif param["site_type"] in ["FRAME_ECC"]:
frame_ecc_on = True
elif param["site_type"] in ["USR_ACCESS", "DCIRESET"]:
if not param["params"]["ENABLED"]:
continue
if param["site_type"] in ["DCIRESET"]:
dcireset_on = True
else:
usr_access_on = True
else:
continue
verilog.instance(
param["module"],
"inst_{}".format(param["site"]),
ports,
param["params"],
string_buffer=string_output)
#Generate LUTs
for l in luts.create_wires_and_luts():
print(l)
print(string_output.getvalue())
print(
'''
endmodule
// ---------------------------------------------------------------------''')
if any_icap:
print(
'''
module mod_ICAP (input [7:0] din, output [7:0] dout, input clk);
parameter ICAP_WIDTH = "X32";
parameter LOC = "ICAP_X0Y0";
wire [23:0] icap_out;
(* KEEP, DONT_TOUCH, LOC=LOC *)
ICAPE2 #(
.ICAP_WIDTH(ICAP_WIDTH),
.SIM_CFG_FILE_NAME("NONE")
)
ICAPE2_inst (
.O({icap_out, dout}),
.CLK(clk),
.CSIB(),
.I({24'd0, din}),
.RDWRB()
);
endmodule
''')
if capture_on:
print(
'''
module mod_CAPTURE (input [7:0] din, output [7:0] dout, input clk);
parameter ONESHOT ="TRUE";
parameter LOC = "ICAP_X0Y0";
(* KEEP, DONT_TOUCH, LOC=LOC *)
CAPTUREE2 #(
.ONESHOT(ONESHOT) // Specifies the procedure for performing single readback per CAP trigger.
)
CAPTUREE2_inst (
.CAP(1'b0),
.CLK(clk)
);
endmodule
''')
if usr_access_on:
print(
'''
module mod_USR_ACCESS (input [7:0] din, output [7:0] dout, input clk);
parameter ENABLED = 1;
parameter LOC = "USR_ACCESS_X0Y0";
wire [23:0] usr_access_wire;
(* KEEP, DONT_TOUCH, LOC=LOC *)
USR_ACCESSE2 USR_ACCESSE2_inst (
.CFGCLK(),
.DATA({usr_access_wire, dout}),
.DATAVALID()
);
endmodule
''')
if any_bscan:
print(
'''
module mod_BSCAN (input [7:0] din, output [7:0] dout, input clk);
parameter JTAG_CHAIN = 1;
parameter LOC = "BSCAN_X0Y0";
(* KEEP, DONT_TOUCH, LOC=LOC *)
BSCANE2 #(
.JTAG_CHAIN(JTAG_CHAIN)
)
dut (
.CAPTURE(),
.DRCK(),
.RESET(),
.RUNTEST(),
.SEL(),
.SHIFT(),
.TCK(),
.TDI(dout[0]),
.TMS(),
.UPDATE(),
.TDO(din[0])
);
endmodule
''')
if startup_on:
print(
'''
module mod_STARTUP (input [7:0] din, output [7:0] dout, input clk);
parameter LOC = "STARTUP_X0Y0";
parameter PROG_USR = "******";
(* KEEP, DONT_TOUCH, LOC=LOC *)
STARTUPE2 #(
.PROG_USR(PROG_USR), // Activate program event security feature. Requires encrypted bitstreams.
.SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency(ns) for simulation.
)
STARTUPE2_inst (
.CFGCLK(),
.CFGMCLK(),
.EOS(),
.PREQ(dout[0]),
.CLK(clk),
.GSR(),
.GTS(),
.KEYCLEARB(),
.PACK(),
.USRCCLKO(),
.USRCCLKTS(),
.USRDONEO(),
.USRDONETS()
);
endmodule
''')
if frame_ecc_on:
print(
'''
module mod_FRAME_ECC (input [7:0] din, output [7:0] dout, input clk);
parameter LOC = "FRAME_ECC_X0Y0";
parameter FARSRC = "EFAR";
wire [25:0] far_wire;
assign dout[7:0] = far_wire[7:0];
(* KEEP, DONT_TOUCH, LOC=LOC *)
FRAME_ECCE2 #(
.FARSRC(FARSRC),
.FRAME_RBT_IN_FILENAME("NONE")
)
FRAME_ECCE2_inst (
.CRCERROR(),
.ECCERROR(),
.ECCERRORSINGLE(),
.FAR(far_wire),
.SYNBIT(),
.SYNDROME(),
.SYNDROMEVALID(),
.SYNWORD()
);
endmodule
''')
if dcireset_on:
print(
'''
module mod_DCIRESET (input [7:0] din, output [7:0] dout, input clk);
parameter LOC = "FRAME_ECC_X0Y0";
parameter ENABLED = 1;
(* KEEP, DONT_TOUCH, LOC=LOC *)
DCIRESET DCIRESET_inst (
.LOCKED(dout[0]),
.RST(dout[1])
);
endmodule
''')