def connect_to_existing_parent_in_port(in_port): parent = in_port.gear.parent in_intf = in_port.producer src_intf = get_source_producer(in_port) for parent_port in parent.in_ports: if src_intf is get_source_producer(parent_port): in_intf.disconnect(in_port) parent_port.consumer.connect(in_port) return True return False
def after_run(self, sim): for sim_gear in sim.sim_gears: module = sim_gear.gear if module.definition == decouple_din: if not module.queue.empty(): if 'data_in_decouple' in self.hooks: self.hooks['data_in_decouple'](module) log.error(f'Data left in decouple: {module.name}') for p in module.in_ports: status = self.get_port_status(p) if status == "active": src_port = get_source_producer(p, sim=True).consumers[0] if src_port.gear.definition == const: # Skip constants since they are never done continue if 'not_ack' in self.hooks: self.hooks['not_ack'](module, p) log.error( f'{src_port.gear.name}.{src_port.basename} -> {module.name}.{p.basename} was not acknowledged' ) if status == "waited": src_port = self.blockers[p] if 'waiting' in self.hooks: self.hooks['waiting'](module, p) log.debug( f'{p.gear.name}.{p.basename} waiting on {src_port.gear.name}.{src_port.basename}' )
def report_out_dangling(port): src_intf = get_source_producer(port) p = src_intf.consumers[0] if hasattr(src_intf, 'var_name'): core_log().warning( f'Interface "{p.gear.name}/{src_intf.var_name}" left dangling.') else: path = [] while True: g = p.gear if hasattr(p.consumer, 'var_name'): path.append(f'{g.parent.name}/{p.consumer.var_name}') else: path.append(p.name) if len(g.in_ports) != 1 or len(g.out_ports) != 1: break p = g.in_ports[0].producer.producer path = ' -> '.join(reversed(path)) core_log().warning(f'Interface "{path}" left dangling.')
def test_through_hier_cosim_in_channel(): reg['gear/infer_signal_names'] = True @gear def hier(din, *, channeled): din | leaf_sink(name='si1') channeled | leaf_sink(name='si2') s = leaf_src(t=Unit) s | hier(sim_cls=CosimBase, channeled=s) intf = get_source_producer(s) assert is_source_producer(intf) assert intf.consumers[0].name == '/leaf_src.dout' consumers = get_consumer_tree(intf) # Leaf consumers are hidden behind "hier" module with "sim_cls" assert len(consumers) == 1 assert consumers[0].name == '/hier.din' assert is_end_consumer(consumers[0].consumer, sim=True) cons_intf = consumers[0].consumer assert len(cons_intf.consumers) == 2 assert cons_intf.consumers[0].name == '/hier/si1.din' assert cons_intf.consumers[1].name == '/hier/si2.din'
def get_port_status(self, port): q = get_producer_queue(port) if q._unfinished_tasks: return "active" prod_port = get_source_producer(port, sim=True).consumers[0] if prod_port in self.handshakes: return "handshaked" if prod_port in self.blockers.values(): return "waited" return "empty"
def test_plain(): reg['gear/infer_signal_names'] = True s = leaf_src(t=Unit) s | leaf_sink(name='si1') s | leaf_sink(name='si2') intf = get_source_producer(s) assert is_source_producer(intf) assert intf.consumers[0].name == '/leaf_src.dout' consumers = get_consumer_tree(intf) assert len(consumers) == 2 assert consumers[0].name == '/si1.din' assert consumers[1].name == '/si2.din' assert is_end_consumer(consumers[0]) assert is_end_consumer(consumers[1])
def test_through_hier_cosim(): reg['gear/infer_signal_names'] = True @gear def hier(din): din | leaf_sink(name='si1') din | leaf_sink(name='si2') s = leaf_src(t=Unit) s | hier(sim_cls=CosimBase) intf = get_source_producer(s) assert is_source_producer(intf) assert intf.consumers[0].name == '/leaf_src.dout' consumers = get_consumer_tree(intf) assert len(consumers) == 1 assert consumers[0].name == '/hier.din' assert is_end_consumer(consumers[0], sim=True)
def test_through_hier_simple(): reg['gear/infer_signal_names'] = True @gear def hier(din): din | leaf_sink(name='si1') din | leaf_sink(name='si2') s = leaf_src(t=Unit) s | hier intf = get_source_producer(s) assert is_source_producer(intf) assert intf.consumers[0].name == '/leaf_src.dout' consumers = get_consumer_tree(intf) assert len(consumers) == 2 assert consumers[0].name == '/hier/si1.din' assert consumers[1].name == '/hier/si2.din' assert is_end_consumer(consumers[0]) assert is_end_consumer(consumers[1])
def test_through_hier_cosim_out_channel(): reg['gear/infer_signal_names'] = True @gear def hier(din, *, channeled): din | leaf_sink(name='si1') channeled |= leaf_src(name='sr2', t=Unit) sout = Intf(Unit) sout | leaf_sink(name='si0') sin = leaf_src(t=Unit) sin | hier(sim_cls=CosimBase, channeled=sout) intf = get_source_producer(sout, sim=True) assert is_source_producer(intf, sim=True) assert intf.consumers[0].name == '/hier.channeled' consumers = get_consumer_tree(intf) # Leaf consumers are hidden behind "hier" module with "sim_cls" assert len(consumers) == 1 assert consumers[0].name == '/si0.din' assert is_end_consumer(consumers[0].consumer)