def randomize_instr(self, instr, is_in_debug=0):
exclude_instr = []
is_SP_in_reserved_rd = riscv_reg_t.SP in self.reserved_rd
is_SP_in_reserved_regs = riscv_reg_t.SP in cfg.reserved_regs
is_SP_in_avail_regs = riscv_reg_t.SP in self.avail_regs
if ((is_SP_in_reserved_rd or is_SP_in_reserved_regs)
or (len(self.avail_regs) > 0 and not is_SP_in_avail_regs)):
exclude_instr.append(riscv_instr_name_t.C_ADDI4SPN.name)
exclude_instr.append(riscv_instr_name_t.C_ADDI16SP.name)
exclude_instr.append(riscv_instr_name_t.C_LWSP.name)
exclude_instr.append(riscv_instr_name_t.C_LDSP.name)
# Post-process the allowed_instr and exclude_instr lists to handle
# adding ebreak instructions into the debug ROM.
if is_in_debug:
if (cfg.no_ebreak and cfg.enable_ebreak_in_debug_rom):
allowed_instr.extend([
riscv_instr_name_t.EBREAK.name,
riscv_instr_name_t.C_EBREAK.name
])
elif (not cfg.no_ebreak and not cfg.enable_ebreak_in_debug_rom):
exclude_instr.extend([
riscv_instr_name_t.EBREAK.name,
riscv_instr_name_t.C_EBREAK.name
])
instr = riscv_instr_ins.get_rand_instr(
include_instr=self.allowed_instr, exclude_instr=exclude_instr)
instr = self.randomize_gpr(instr)
return instr
def post_randomize(self):
order = []
RA = cfg.ra
order = [0] * self.num_of_jump_instr
self.jump = [0] * self.num_of_jump_instr
for i in range(len(order)):
order[i] = i
random.shuffle(order)
self.setup_allowed_instr(1, 1)
jal = [riscv_instr_name_t.JAL]
if not cfg.disable_compressed_instr:
jal.append(riscv_instr_name_t.C_J)
if rcs.XLEN == 32:
jal.append(riscv_instr_name_t.C_JAL)
self.jump_start = riscv_instr_ins.get_instr(
riscv_instr_name_t.JAL.name)
with self.jump_start.randomize_with() as it:
self.jump_start.rd == RA
self.jump_start.imm_str = "{}f".format(order[0])
self.jump_start.label = self.label
# Last instruction
self.jump_end = self.randomize_instr(self.jump_end)
self.jump_end.label = "{}".format(self.num_of_jump_instr)
for i in range(self.num_of_jump_instr):
self.jump[i] = riscv_instr_ins.get_rand_instr(
include_instr=[jal[0].name])
with self.jump[i].randomize_with() as it:
if self.jump[i].has_rd:
vsc.dist(self.jump[i].rd, [
vsc.weight(riscv_reg_t.RA, 5),
vsc.weight(vsc.rng(riscv_reg_t.SP, riscv_reg_t.T0), 1),
vsc.weight(vsc.rng(riscv_reg_t.T2, riscv_reg_t.T6), 2)
])
self.jump[i].rd.not_inside(cfg.reserved_regs)
self.jump[i].label = "{}".format(i)
for i in range(len(order)):
if i == self.num_of_jump_instr - 1:
self.jump[order[i]].imm_str = "{}f".format(
self.num_of_jump_instr)
else:
if order[i + 1] > order[i]:
self.jump[order[i]].imm_str = "{}f".format(order[i + 1])
else:
self.jump[order[i]].imm_str = "{}b".format(order[i + 1])
self.instr_list.append(self.jump_start)
self.instr_list.extend(self.jump)
self.instr_list.append(self.jump_end)
for i in range(len(self.instr_list)):
self.instr_list[i].has_label = 1
self.instr_list[i].atomic = 1
def gen_push_stack_instr(self, stack_len, allow_branch=1):
self.stack_len = stack_len
self.init()
self.push_stack_instr = [0] * (self.num_of_reg_to_save + 1)
for i in range(len(self.push_stack_instr)):
self.push_stack_instr[i] = riscv_instr()
self.push_stack_instr[0] = \
riscv_instr_ins.get_instr(riscv_instr_name_t.ADDI.name)
with self.push_stack_instr[0].randomize_with() as it:
self.push_stack_instr[0].rd == cfg.sp
self.push_stack_instr[0].rs1 == cfg.sp
self.push_stack_instr[0].imm == (~cfg.stack_len) + 1
self.push_stack_instr[0].imm_str = '-{}'.format(self.stack_len)
for i in range(len(self.saved_regs)):
if rcs.XLEN == 32:
self.push_stack_instr[i + 1] = riscv_instr_ins.get_instr(riscv_instr_name_t.SW.name)
with self.push_stack_instr[i + 1].randomize_with() as it:
self.push_stack_instr[i + 1].rs2 == self.saved_regs[i]
self.push_stack_instr[i + 1].rs1 == cfg.sp
self.push_stack_instr[i + 1].imm == 4 * (i + 1)
else:
self.push_stack_instr[i + 1] = riscv_instr_ins.get_instr(riscv_instr_name_t.SD.name)
with self.push_stack_instr[i + 1].randomize_with() as it:
self.push_stack_instr[i + 1].rs2 == self.saved_regs[i]
self.push_stack_instr[i + 1].rs1 == cfg.sp
self.push_stack_instr[i + 1].imm == 8 * (i + 1)
self.push_stack_instr[i + 1].process_load_store = 0
if allow_branch:
# TODO `DV_CHECK_STD_RANDOMIZE_FATAL(enable_branch)
pass
else:
self.enable_branch = 0
if self.enable_branch:
self.branch_instr = \
riscv_instr_ins.get_rand_instr(include_category=[riscv_instr_name_t.BRANCH.name])
# TODO `DV_CHECK_STD_RANDOMIZE_FATAL(branch_instr)
self.branch_instr.imm_str = self.push_start_label
self.branch_instr.brach_assigned = 1
self.push_stack_instr[0].label = self.push_start_label
self.push_stack_instr[0].has_label = 1
self.branch_instr.extend(self.push_stack_instr)
self.mix_instr_stream(self.push_stack_instr)
for i in range(len(self.instr_list)):
self.instr_list[i].atomic = 1
if self.instr_list[i].label == '':
self.instr_list[i].has_label = 0
def randomize_instr(self, instr, is_in_debug=0, disable_dist=0):
exclude_instr = []
is_SP_in_reserved_rd = riscv_reg_t.SP in self.reserved_rd
is_SP_in_reserved_regs = riscv_reg_t.SP in cfg.reserved_regs
is_SP_in_avail_regs = riscv_reg_t.SP in self.avail_regs
if ((is_SP_in_reserved_rd or is_SP_in_reserved_regs)
or (len(self.avail_regs) > 0 and not is_SP_in_avail_regs)):
exclude_instr.append(riscv_instr_name_t.C_ADDI4SPN.name)
exclude_instr.append(riscv_instr_name_t.C_ADDI16SP.name)
exclude_instr.append(riscv_instr_name_t.C_LWSP.name)
exclude_instr.append(riscv_instr_name_t.C_LDSP.name)
if is_in_debug and (not cfg.enable_ebreak_in_debug_rom):
exclude_instr.append(riscv_instr_name_t.EBREAK.name)
exclude_instr.append(riscv_instr_name_t.C_EBREAK.name)
instr = riscv_instr_ins.get_rand_instr(
include_instr=self.allowed_instr, exclude_instr=exclude_instr)
instr = self.randomize_gpr(instr)
return instr
def post_randomize(self):
self.init_instr = [None] * self.num_of_avail_regs
for i in range(len(self.init_val_type)):
if self.init_val_type[i] == int_numeric_e.Zero:
self.init_val[i] = 0
elif self.init_val_type[i] == int_numeric_e.AllOne:
self.init_val[i] = 1
elif self.init_val_type[i] == int_numeric_e.NegativeMax:
self.init_val[i] = 1 << (rcs.XLEN - 1)
self.init_instr[i] = riscv_pseudo_instr()
self.init_instr[i].rd = self.avail_regs[i]
self.init_instr[i].pseudo_instr_name = riscv_pseudo_instr_name_t.LI
self.init_instr[i].imm_str = "0x%0x" % (self.init_val[i])
self.instr_list.append(self.init_instr[i])
for i in range(self.num_of_instr):
instr = riscv_instr_ins.get_rand_instr(
include_category = ['ARITHMETIC'],
exclude_group = ['RV32C', 'RV64C', 'RV32F', 'RV64F', 'RV32D', 'RV64D'])
instr = self.randomize_gpr(instr)
self.instr_list.append(instr)
super().post_randomize()