def main(self, arg):
b = Sfix(0.5, 0, -17)
b = Sfix(0.5, 5, -5)
assert b.left == 5
assert b.right == -5
return arg
def test_sfix_add_shift_right_resize(shift_i):
right = -18
left = 0
class T10(Hardware):
def main(self, x, y, i):
ret = resize(x - (y >> i),
size_res=x,
round_style='truncate',
overflow_style='saturate')
return ret
x = (np.random.rand(1024) * 2) - 1
y = (np.random.rand(1024) * 2) - 1
i = [shift_i] * len(x)
dut = T10()
sims = simulate(
dut,
x,
y,
i,
simulations=SIMULATIONS,
input_types=[Sfix(0, left, right),
Sfix(0, left, right), int])
assert sims_close(sims, rtol=1e-9, atol=1e-9)
def test_add_none(self):
a = Sfix(0.123, None, None)
b = Sfix(-0.223, 0, -18)
c = a + b
assert float(c) == float(a) + float(b)
assert c.left == 1
assert c.right == -18
def test_sub_none(self):
a = Sfix(0.223, 0, -8)
b = Sfix(0.013, None, None)
c = a - b
assert float(c) == float(a) - float(b)
assert c.left == 1
assert c.right == -8
def __init__(self):
self.a = Sfix(0, 0, -17)
self.b = Sfix(0, 2, -17)
self.c = Complex(0, 0, -17)
self.c2 = Complex(0, 0, -17)
self.DELAY = 1
def test_add():
a = Sfix(0.123, 0, -8)
b = Sfix(-0.223, 0, -18)
c = a + b
assert float(c) == float(a) + float(b)
assert c.left == 1
assert c.right == -18
def __init__(self):
self.a = [
Sfix(0.1, 0, -28),
Sfix(0.2, 0, -28),
Sfix(0.3, 0, -28),
Sfix(0.4, 0, -28)
]
def test_auto_size_negative_int_bits():
pytest.skip()
a = 0.00390623013197
b = Sfix.auto_size(a, 18)
np.isclose(b.val, a)
assert b.left == -7
assert b.right == -24
a = 0.45
b = Sfix.auto_size(a, 18)
np.isclose(b.val, a)
assert b.left == -2
assert b.right == -19
a = 0.25
b = Sfix.auto_size(a, 18)
np.isclose(b.val, a)
assert b.left == -1
assert b.right == -18
a = -0.000000025124
b = Sfix.auto_size(a, 18)
np.isclose(b.val, a)
assert b.left == -25
assert b.right == -42
def test_sub():
a = Sfix(0.223, 0, -8)
b = Sfix(0.013, 0, -18)
c = a - b
assert float(c) == float(a) - float(b)
assert c.left == 1
assert c.right == -18
def test_mul():
a = Sfix(0.223, 0, -8)
b = Sfix(0.321, 0, -18)
c = a * b
assert float(c) == float(a) * float(b)
assert c.left == 1
assert c.right == -26
def test_sub_overlow():
a = Sfix(-0.5, 0, -8)
b = Sfix(-1, 0, -18)
c = a - b
assert float(c) == float(a) - float(b)
assert c.left == 1
assert c.right == -18
def test_pyha_reset_value(self):
dut = VHDLSfix('name', Sfix(0, 1, -17), initial=Sfix(0.3, 1, -17))
expect = 'Sfix(0.29999542236328125, 1, -17)'
assert dut._pyha_reset_value() == expect
dut = VHDLSfix('name', Sfix(0, 2, -8), initial=Sfix(0.3))
expect = 'Sfix(0.3, 2, -8)'
assert dut._pyha_reset_value() == expect
def main(self, arg):
b = Sfix(0.5, 0, -17)
c = Sfix(0.1, 5, -12)
a = b
b = c
c = a
return arg, a, b, c
def test_non_unit_resize():
pytest.skip()
a = Sfix(0.8, -1, -12)
assert a.val == 0.499755859375
a = Sfix(1.5, 1, -12)
b = a.resize(-1, -12)
assert b.val == 0.499755859375
def basic_obj():
class Register(Hardware):
def main(self, a, b, c=0):
return a * 5, True, Sfix(0.0, 5, -8)
dut = Register()
dut._pyha_enable_function_profiling_for_types()
dut.main(2, Sfix(1.0, 2, -17))
dut.main(-57, Sfix(1.0, 2, -17))
dut.main(-57, Sfix(1.0, 2, -17), c=True)
return dut
def test_len():
a = Sfix(0.223, 0, -8)
assert len(a) == 9
a = Sfix(0.223, 2, -8)
assert len(a) == 11
a = Sfix(0.223, -2, -8)
assert len(a) == 7
a = Sfix(0.223, 8, 3)
assert len(a) == 6
def test_arith():
a = Sfix(0.223, 0, -8)
b = Sfix(-0.098, 0, -18)
c = Sfix(0.731, 0, -17)
d = Sfix(0.201, 0, -6)
e = Sfix(0.01, 0, -12)
f = (a * b + c - d) * e
full_prec = (float(a) * float(b) + float(c) - float(d)) * float(e)
assert float(f) == full_prec
assert f.left == 4
assert f.right == -38
def test_radd():
b = Sfix(0.1, 0, -17)
c = 0.1 + b
assert c.val == 0.1999969482421875
c = -0.1 + b
assert c.val == 0.0
b = Sfix(-0.1, 0, -17)
c = 0.1 + b
assert c.val == -7.62939453125e-06
c = -0.1 + b
assert c.val == -0.20000457763671875
def test_rsub():
b = Sfix(0.1, 0, -17)
c = 0.1 - b
assert c.val == 0.0
c = -0.1 - b
assert c.val == -0.1999969482421875
b = Sfix(-0.1, 0, -17)
c = 0.1 - b
assert c.val == 0.20000457763671875
c = -0.1 - b
assert c.val == 7.62939453125e-06
def test_init():
f = Sfix(0.123, 0, -8, round_style='round')
assert f.val == 0.12109375 # round down
f = Sfix(0.124, 0, -8, round_style='round')
assert f.val == 0.125 # round up
f = Sfix(1, 0, -8, overflow_style='saturate')
assert f.val == 0.99609375 # saturates up
f = Sfix(-2, 0, -8, overflow_style='saturate')
assert f.val == -1 # saturates down
assert f.left == 0
assert f.right == -8
def test_abs():
a = Sfix(0.355, 0, -12)
b = abs(a)
assert a.val == b.val
assert b.left == a.left + 1
assert b.right == a.right
a = Sfix(-0.05, 0, -12)
b = abs(a)
assert b.val == -a.val
assert b.left == a.left + 1
assert b.right == a.right
c = abs(b)
assert c.left == 2
def test_build_arguments(self):
class T(Hardware):
def __init__(self):
self.reg = 1
def a(self, i, b, f, l):
return 1, 1 < 2, resize(f, 0, -17), Sfix(0.1, 0,
-5), l[0], self.reg
dut = T()
dut._pyha_enable_function_profiling_for_types()
dut.a(1, False, Sfix(0.5, 1, -2), [1, 2])
expect = 'self:in self_t; ' \
'self_next:inout self_t; ' \
'constant self_const: self_t_const; ' \
'i: integer; ' \
'b: boolean; ' \
'f: sfixed(1 downto -2); ' \
'l: Typedefs.integer_list_t(0 to 1); ' \
'ret_0:out integer; ' \
'ret_1:out boolean; ' \
'ret_2:out sfixed(0 downto -17); ' \
'ret_3:out sfixed(0 downto -5); ' \
'ret_4:out integer; ' \
'ret_5:out integer'
conv = get_conversion(dut)
func = conv.get_function('a')
assert expect == func.build_arguments()
def test_saturation(self):
x = [0.9, 1.0, 1.5, 2.0]
expected = [0.875 + 0.875j, 0.9375 + 0.9375j, 0.9375 + 0.9375j, 0.9375 + 0.9375j]
dut = self.A2('saturate', 'truncate')
assert_sim_match(dut, expected, x, types=[Sfix(left=2, right=-17)],
simulations=['HARDWARE', 'RTL', 'NETLIST'])
def __init__(self, start_value):
if start_value == 0:
bits = 1
else:
bits = int(np.log2(start_value)) + 1
self.START_VALUE = Sfix(start_value, bits, 0)
self.counter = self.START_VALUE
def test_wrap(self):
x = [0.9, 1.0, 1.5, 2.0]
expected = [0.875, -1, -0.5, 0]
dut = self.A('wrap', 'truncate')
assert_sim_match(dut, expected, x, types=[Sfix(left=2, right=-17)],
simulations=['HARDWARE', 'RTL', 'NETLIST'])
def test_shift_left(self):
with Sfix._float_mode:
f = Sfix(0.12345678, 0, -2)
b = f << 1
assert b.val == 0.12345678 * 2
assert b.left == 0
assert b.right == -2
def test_resize_no_effect(self):
with Sfix._float_mode:
f = Sfix(0.12345678, 0, -20)
b = resize(f, 0, -2)
assert b.val == 0.12345678
assert b.left == 0
assert b.right == -2
def _convert_other_operand(self, other):
if isinstance(other, complex):
other = Complex(other, self.left, self.right, overflow_style='saturate', round_style='round',
signed=self.signed)
elif isinstance(other, (float, int)):
other = Sfix(other, self.left, self.right, overflow_style='saturate', round_style='round',
signed=self.signed)
return other
def setup(self):
d = [Sfix(0, 1, -2)] * 2
self.dut = VHDLList('out', d, d)
class T(Hardware):
pass
self.dut_sub = VHDLList('out', [T()] * 2, [T()] * 2)
def test_neg(self):
a = Sfix(0.223, 0, None)
b = -a
assert b.val == -0.223
assert b.left == 1
assert b.right == None
a = Sfix(0.223, None, None)
b = -a
assert b.val == -0.223
assert b.left == None
assert b.right == None
a = Sfix(0.223, None, -5)
b = -a
assert b.val == -0.223
assert b.left == None
assert b.right == -5
