def f_fpga(coord):
    gcoord = C.FPGAGlobal(coord, WAFER)
    result = []
    for dnc_f in C.iter_all(C.DNCOnFPGA):
        dnc = dnc_f.toDNCOnWafer(gcoord)
        result += hicanns_on_dnc(dnc)
    return result
Exemple #2
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    def test_has_outbound_mergers(self):
        import pyhalbe
        import pysthal
        from pyhalco_common import Enum
        import pyhalco_hicann_v2 as C

        wafer_c = C.Wafer(33)
        gbitlink_c = C.GbitLinkOnHICANN(Enum(0))
        fpga_on_wafer_c = C.FPGAOnWafer(Enum(0))
        fpga_c = C.FPGAGlobal(fpga_on_wafer_c, wafer_c)
        hicann_cs = [
            C.HICANNGlobal(h, wafer_c) for h in fpga_c.toHICANNOnWafer()
        ]
        hicann_c = hicann_cs[0]
        hicann_on_dnc_c = hicann_c.toHICANNOnWafer().toHICANNOnDNC()
        dnc_on_fpga_c = hicann_c.toDNCOnFPGA()

        w = pysthal.Wafer()
        h = w[hicann_c.toHICANNOnWafer()]
        f = w[fpga_on_wafer_c]

        self.assertFalse(f.hasOutboundMergers())

        f[dnc_on_fpga_c][hicann_on_dnc_c].layer1[
            gbitlink_c] = pyhalbe.HICANN.GbitLink.Direction.TO_DNC
        self.assertTrue(f.hasOutboundMergers())
Exemple #3
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 def test_fpga_copy(self):
     import copy
     import pyhalbe
     f = pysthal.FPGA(C.FPGAGlobal(), pysthal.FPGAShared())
     f2 = copy.deepcopy(f)
     self.assertEqual(f, f2)
     # change something to ensure that it's not a mere pointer copy
     f.insertReceivedPulseEvent(pyhalbe.FPGA.PulseEvent())
     self.assertNotEqual(f, f2)
def f_fpga(coord):
    """print fpga related infomations"""
    gcoord = Coordinate.FPGAGlobal(coord, WAFER)
    out = "{}:\n".format(gcoord)
    for dnc_f in iter_all(Coordinate.DNCOnFPGA):
        dnc = dnc_f.toDNCOnWafer(gcoord)
        out += "\t{} ({}, {}):\n".format(dnc, dnc.toEnum(), dnc.toPowerCoordinate())
        out += print_hicanns_on_dnc(dnc, "\t\t")
    return out
    def test_add_to_empty_db(self):
        mydb = pyhwdb.database()
        fpga_coord = coord.FPGAGlobal(self.FPGA_COORD, self.WAFER_COORD)
        hicann_coord = coord.HICANNGlobal(self.HICANN_COORD, self.WAFER_COORD)

        with self.assertRaises(IndexError):
            mydb.add_fpga_entry(fpga_coord, pyhwdb.FPGAEntry())
        with self.assertRaises(IndexError):
            mydb.add_hicann_entry(hicann_coord, pyhwdb.HICANNEntry())
Exemple #6
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 def test_fpga_pickle(self):
     import pickle
     import pyhalbe
     f = pysthal.FPGA(C.FPGAGlobal(), pysthal.FPGAShared())
     f_str = pickle.dumps(f)
     f2 = pickle.loads(f_str)
     self.assertEqual(f, f2)
     # change something to ensure that it's not a mere pointer copy
     f.insertReceivedPulseEvent(pyhalbe.FPGA.PulseEvent())
     self.assertNotEqual(f, f2)
Exemple #7
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    def test_custom_db(self):
        db = pyhwdb.database()
        wafer = pyhwdb.WaferEntry()
        wafer.setup_type = coord.SetupType.BSSWafer
        wafer_coord = coord.Wafer(10)
        db.add_wafer_entry(wafer_coord, wafer)
        fpga = pyhwdb.FPGAEntry()
        fpga_coord = coord.FPGAGlobal(coord.FPGAOnWafer(0), wafer_coord)
        db.add_fpga_entry(fpga_coord, fpga)

        licenses, tres = generate_license_strings(db)
        # licenses is generated from set -> order not guaranteed
        self.assertTrue(licenses == "Licenses=W10F0,W10T8"
                        or licenses == "Licenses=W10T8,W10F0")
        self.assertTrue(
            tres == "AccountingStorageTRES=License/W10F0,License/W10T8"
            or tres == "AccountingStorageTRES=License/W10T8,License/W10F0")

        try:
            tmpdirname = tempfile.mkdtemp()
            lic_tmp_file = os.path.join(tmpdirname, str(uuid.uuid4()))
            tres_tmp_file = os.path.join(tmpdirname, str(uuid.uuid4()))

            create_license_files(db, lic_tmp_file, tres_tmp_file)

            with open(lic_tmp_file, "r") as file:
                content = file.read()
                self.assertTrue(
                    any(lic in content for lic in
                        ["Licenses=W10F0,W10T8", "Licenses=W10T8,W10F0"]))

            with open(tres_tmp_file, "r") as file:
                content = file.read()
                self.assertTrue(
                    any(tres in content for tres in [
                        "AccountingStorageTRES=License/W10F0,License/W10T8",
                        "AccountingStorageTRES=License/W10T8,License/W10F0"
                    ]))
        finally:
            shutil.rmtree(tmpdirname)
Exemple #8
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    def setUp(self):
        if 'nose' in list(sys.modules.keys()):
            # ugly hack to support nose-based execution...
            self.FPGA_IP = '0.0.0.0'
            self.PMU_IP = '0.0.0.0'
            self.HICANN = 0
            self.DNC = 1
            self.FPGA = 0
            self.LOGLEVEL = 2
            self.ON_WAFER = False
            self.WAFER = 0

        import pyhalco_hicann_v2 as Coordinate
        from pyhalbe import Handle, HICANN, FPGA, Debug
        # The module pyhalbe.apicheck wraps pyhalbe for hardware-less
        # apichecks. It will be enabled only if the environment variable
        # PYHALBE_API_CHECK is set to true. The attribute "enabled" will be set
        # accordingly. KHS.
        import pyhalbe_apicheck as apicheck

        from pyhalco_common import Enum
        highspeed = True
        arq = True
        hicann_num = 1
        fpga_ip = Coordinate.IPv4.from_string(self.FPGA_IP)
        pmu_ip = Coordinate.IPv4.from_string(self.pmu_IP)
        if self.LOGLEVEL >= 0:
            Debug.change_loglevel(self.LOGLEVEL)

        self.dnc = Coordinate.DNCOnFPGA(Enum(self.DNC))
        self.hicann = Coordinate.HICANNOnDNC(Enum(self.HICANN))
        self.f = Coordinate.FPGAGlobal(Enum(self.FPGA),
                                       Coordinate.Wafer(Enum(self.WAFER)))

        self.fpga = Handle.createFPGAHw(self.f, fpga_ip, self.dnc,
                                        self.ON_WAFER, hicann_num, pmu_ip)
        self.addCleanup(Handle.freeFPGAHw, self.fpga)

        self.h = self.fpga.get(self.dnc, self.hicann)
        if self.ON_WAFER:
            self.h0 = self.fpga.get(self.dnc, Coordinate.HICANNOnDNC(Enum(0)))
            self.h1 = self.fpga.get(self.dnc, Coordinate.HICANNOnDNC(Enum(1)))
            self.h2 = self.fpga.get(self.dnc, Coordinate.HICANNOnDNC(Enum(2)))
            self.h3 = self.fpga.get(self.dnc, Coordinate.HICANNOnDNC(Enum(3)))
            self.h4 = self.fpga.get(self.dnc, Coordinate.HICANNOnDNC(Enum(4)))
            self.h5 = self.fpga.get(self.dnc, Coordinate.HICANNOnDNC(Enum(5)))
            self.h6 = self.fpga.get(self.dnc, Coordinate.HICANNOnDNC(Enum(6)))
            self.h7 = self.fpga.get(self.dnc, Coordinate.HICANNOnDNC(Enum(7)))

        self.apicheck = apicheck.enabled()
        if apicheck.enabled():  # equals PYHALBE_API_CHECK
            # With hardware access disabled pyhalbe functions return anything
            # but the expected, i.e. all unittest assertions naturally fail.
            # I.e. for a functional API check they have to be disabled. KHS.
            apicheck.monkeyPatch(
                self, 'assert'
            )  # disables all functions in self that start with "assert"

        # ECM says: this should be part of the tests... automatic resets during construction isn't very "standalone"
        # OR it is necessary and in this case it should be a member function and documented somehow.
        # FPGA reset
        FPGA.reset(self.fpga)
        HICANN.init(self.h, False)
        if self.ON_WAFER:
            HICANN.init(self.h0, False)
            HICANN.init(self.h1, False)
            HICANN.init(self.h2, False)
            HICANN.init(self.h3, False)
            HICANN.init(self.h4, False)
            HICANN.init(self.h5, False)
            HICANN.init(self.h6, False)
            HICANN.init(self.h7, False)
                    help="Used Pll frequency (in MHz)")
parser.add_argument('-zs',
                    '--zero-synapses',
                    action='store_true',
                    dest='zero_syn',
                    help="try to set synapse values to zero in highspeed test")
args = parser.parse_args()

if not args.skip_empty_backend_path_check and glob.glob(
        os.path.join(args.backend_path, "*.xml")):
    raise RuntimeError("{} is not empty".format(args.backend_path))

wafer_c = C.Wafer(args.wafer)
hicann_c = C.HICANNOnWafer(Enum(args.hicann))
fpga_c = hicann_c.toFPGAOnWafer()
fpga_global_c = C.FPGAGlobal(fpga_c, wafer_c)

redman_wafer_backend = load.WaferWithBackend(args.backend_path, wafer_c)
redman_fpga_backend = load.FpgaWithBackend(args.backend_path, fpga_global_c)
hs_exit = 0
jtag_exit = 0

# reset fpga before each HICANN test
fpga_reset_cmd = [
    "fpga_remote_init.py", "-r", "1", "-w",
    str(args.wafer), "-f",
    str(fpga_c.value()), "--alloc", "existing"
]
subprocess.call(fpga_reset_cmd)
highspeed_test_cmd = [
    "sthal_single_chip_init.py", "--wafer",
Exemple #10
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    def test_database_access(self):
        mydb = pyhwdb.database()

        if IS_PYPLUSPLUS:
            wafer = pyhwdb.WaferEntry()
            wafer_coord = self.WAFER_COORD
            wafer.setup_type = self.WAFER_SETUP_TYPE
            self.assertFalse(mydb.has_wafer_entry(wafer_coord))
            mydb.add_wafer_entry(wafer_coord, wafer)
            self.assertTrue(mydb.has_wafer_entry(wafer_coord))
            self.assertEqual(mydb.get_wafer_entry(wafer_coord).setup_type, wafer.setup_type)
            wafer_coords = mydb.get_wafer_coordinates()
            self.assertEqual(len(wafer_coords), 1)
            mydb.remove_wafer_entry(wafer_coord)
            self.assertFalse(mydb.has_wafer_entry(wafer_coord))

        dls_entry = pyhwdb.DLSSetupEntry()
        dls_setup_id = self.DLS_SETUP_ID
        self.assertFalse(mydb.has_dls_entry(dls_setup_id))
        mydb.add_dls_entry(dls_setup_id, dls_entry)
        self.assertTrue(mydb.has_dls_entry(dls_setup_id))
        mydb.remove_dls_entry(dls_setup_id)
        self.assertFalse(mydb.has_dls_entry(dls_setup_id))

        if not IS_PYPLUSPLUS:
            hxcube_entry = pyhwdb.HXCubeSetupEntry()
            hxcube_id = self.HXCUBE_ID
            hxcube_entry.hxcube_id = hxcube_id
            hxcube_entry.usb_host = "fantasy"
            hxcube_entry.usb_serial = "ABACD1243"
            fpga_entry = pyhwdb.HXCubeFPGAEntry()
            fpga_entry.ip = self.FPGA_IP
            wing_entry = pyhwdb.HXCubeWingEntry()
            wing_entry.ldo_version = 8
            wing_entry.eeprom_chip_serial = 0x987DE
            wing_entry.handwritten_chip_serial = 12
            wing_entry.chip_revision = 42
            fpga_entry.wing = wing_entry
            fpga_entry2 = pyhwdb.HXCubeFPGAEntry()
            hxcube_entry.fpgas = {0: fpga_entry, 3: fpga_entry2}

            self.assertFalse(mydb.has_hxcube_setup_entry(hxcube_id))
            mydb.add_hxcube_setup_entry(hxcube_id, hxcube_entry)
            self.assertTrue(mydb.has_hxcube_setup_entry(hxcube_id))
            mydb.remove_hxcube_setup_entry(hxcube_id)
            self.assertFalse(mydb.has_hxcube_setup_entry(hxcube_id))
            self.assertEqual(hxcube_entry.get_unique_branch_identifier(12),
                            "hxcube9fpga0chip12_1")
            with self.assertRaises(RuntimeError):
                hxcube_entry.get_unique_branch_identifier(108)


        if IS_PYPLUSPLUS:
            # require wafer entry to write other entry typed into
            mydb.add_wafer_entry(wafer_coord, wafer)

            fpga = pyhwdb.FPGAEntry()
            fpga_coord = coord.FPGAGlobal(self.FPGA_COORD, self.WAFER_COORD)
            fpga.ip = self.FPGA_IP
            self.assertFalse(mydb.has_fpga_entry(fpga_coord))
            mydb.add_fpga_entry(fpga_coord, fpga)
            self.assertTrue(mydb.has_fpga_entry(fpga_coord))
            self.assertEqual(mydb.get_fpga_entry(fpga_coord).ip, fpga.ip)
            mydb.remove_fpga_entry(fpga_coord)
            self.assertFalse(mydb.has_fpga_entry(fpga_coord))

            reticle = pyhwdb.ReticleEntry()
            reticle_coord = coord.DNCGlobal(self.RETICLE_COORD, self.WAFER_COORD)
            reticle.to_be_powered = self.RETICLE_TO_BE_POWERED
            self.assertFalse(mydb.has_reticle_entry(reticle_coord))
            mydb.add_reticle_entry(reticle_coord, reticle)
            self.assertTrue(mydb.has_reticle_entry(reticle_coord))
            self.assertEqual(mydb.get_reticle_entry(reticle_coord).to_be_powered, reticle.to_be_powered)
            mydb.remove_reticle_entry(reticle_coord)
            self.assertFalse(mydb.has_reticle_entry(reticle_coord))


            # require fpga entry to add hicann entry
            mydb.add_fpga_entry(fpga_coord, fpga)

            hicann = pyhwdb.HICANNEntry()
            hicann_coord = coord.HICANNGlobal(self.HICANN_COORD, self.WAFER_COORD)
            hicann.version = self.HICANN_VERSION
            self.assertFalse(mydb.has_hicann_entry(hicann_coord))
            mydb.add_hicann_entry(hicann_coord, hicann)
            self.assertTrue(mydb.has_hicann_entry(hicann_coord))
            self.assertEqual(mydb.get_hicann_entry(hicann_coord).version, hicann.version)
            mydb.remove_hicann_entry(hicann_coord)
            self.assertFalse(mydb.has_hicann_entry(hicann_coord))

            # test clear()
            mydb.add_hicann_entry(hicann_coord, hicann)
            mydb.clear()
            self.assertFalse(mydb.has_hicann_entry(hicann_coord))
            self.assertFalse(mydb.has_fpga_entry(fpga_coord))
            self.assertFalse(mydb.has_wafer_entry(wafer_coord))