def tv_in(m, tv): m.enq_en = Bits1(tv[0]) m.enq_msg = Bits32(tv[1]) m.deq_en = Bits1(tv[3])
def __init__( s, foo=42 ): s.foo = Bits32( foo )
def __init__(s, a=0, b=0): s.a = Bits8(a) s.b = Bits32(b)
def up_wr_y(): s.y = Bits32(0x12345678)
def construct(s): s.out = dsl.OutPort(Bits32) dsl.connect(s.out, Bits32(0))
def up_wr_A(): s.A = Bits32(123)
def up_wr_x(): s.x = Bits32(0x87654321)
def construct(s): s.in_ = B(Bits32(42)) s.out = OutPort(Bits32) connect(s.out, s.in_.foo)
def visit_Number(s, node): # By default, number literals have bitwidth of 32 node.Type = rt.get_rtlir(node.value) node._value = Bits32(node.value)
def up(): s.a <<= Bits32(12)
def test_packed_array(do_test): @bitstruct class B: foo: [Bits32] * 2 class A(Component): def construct(s): s.in_ = InPort(B) s.out = [OutPort(Bits32) for _ in range(2)] connect(s.out[0], s.in_.foo[0]) connect(s.out[1], s.in_.foo[1]) a = A() _foo = rdt.PackedArray([2], rdt.Vector(32)) a._ref_structs = [ ( rdt.Struct( 'B', {'foo':_foo} ), \ """\ typedef struct packed { logic [1:0][31:0] foo; } B; """ ) ] a._ref_ports = { a : \ """\ input logic [0:0] clk, input B in_, output logic [31:0] out [0:1], input logic [0:0] reset\ """ } a._ref_wires = {a: ""} a._ref_conns = { a : \ """\ assign out[0] = in_.foo[0]; assign out[1] = in_.foo[1];\ """ } # Yosys backend test reference output a._ref_ports_port_yosys = { a : \ """\ input logic [0:0] clk, input logic [31:0] in___foo__0, input logic [31:0] in___foo__1, output logic [31:0] out__0, output logic [31:0] out__1, input logic [0:0] reset\ """ } a._ref_ports_wire_yosys = { a : \ """\ logic [31:0] in___foo [0:1]; logic [63:0] in_; logic [31:0] out [0:1];\ """ } a._ref_ports_conn_yosys = { a : \ """\ assign in___foo[0] = in___foo__0; assign in___foo[1] = in___foo__1; assign in_[63:32] = in___foo__1; assign in_[31:0] = in___foo__0; assign out__0 = out[0]; assign out__1 = out[1];\ """ } a._ref_wires_yosys = a._ref_wires a._ref_conns_yosys = { a : \ """\ assign out[0] = in___foo[0]; assign out[1] = in___foo[1];\ """ } # TestVectorSimulator properties def tv_in(m, tv): m.in_ = tv[0] def tv_out(m, tv): assert m.out[0] == Bits32(tv[1]) assert m.out[1] == Bits32(tv[2]) a._test_vectors = [ [B(), 0, 0], [B([Bits32(1), Bits32(2)]), 1, 2], [B([Bits32(-1), Bits32(-2)]), -1, -2], [B([Bits32(-2), Bits32(-3)]), -2, -3], [B([Bits32(24), Bits32(25)]), 24, 25], ] a._tv_in, a._tv_out = tv_in, tv_out do_test(a)
def up(): s.a @= Bits32(12)
def up_write(): if s.counter_assign & 1: assign( Bits32(1), Bits32(2) ) else: assign( Bits32(10), Bits32(20) ) s.counter_assign @= s.counter_assign + 1
def upblk(): s.out_b = Bits32(0)
def construct(s): s.wire = Wire(Bits32) connect(s.wire, Bits32(0))
def tv_in(m, tv): m.in_[0].foo = Bits32(tv[0]) m.in_[1].foo = Bits32(tv[1])
def _lambda__s_out(): s.out2 = Bits32(2)
def tv_in(m, tv): m.in_.val = Bits1(tv[0]) m.in_.msg = Bits32(tv[1]) m.out.rdy = Bits1(1)
def up_wr_x(): s.x = Bits32(123)
def tv_out(m, tv): assert m.in_.rdy == Bits1(1) assert m.out.val == Bits1(tv[2]) assert m.out.msg == Bits32(tv[3])
def up_wr_A(): s.A = Bits32(0x12345678)
def tv_out(m, tv): assert m.out_foo == Bits32(tv[1]) assert m.out_bar == Bits32(tv[2])
def up_wr_s_w(): s.w = Bits32(0x12345678)
def __init__(s, bar=1): s.bar = Bits32(bar)
def construct(s): s.const = [Bits32(42) for _ in range(5)]
def tv_out(m, tv): assert m.out[0] == Bits32(tv[1]) assert m.out[1] == Bits32(tv[2])
def __init__( s, foo=42 ): s.foo = [ Bits32( foo ) for _ in range(5) ]
def tv_out(m, tv): assert m.out == Bits32(tv[0])
def construct(s): s.wire = Wire(SomeMsg1) connect(s.wire, Bits32(1))
def tv_out(m, test_vector): assert m.out == Bits32(test_vector[1])