def construct(s):
s.struct = InPort(B)
s.out = OutPort(C)
connect(s.struct.bar[1], s.out)
def construct( s ): s.out = OutPort( Bits32 ) s.b = [ B() for _ in range(2) ] connect( s.out, s.b[1].foo )
def construct( s ): s.foo = InPort( B ) s.bar = OutPort( C )
def construct( s, nbits=0 ):
s.in_ = InPort ( mk_bits(nbits) )
s.out = [ OutPort( mk_bits(nbits) ) for i in range(5) ]
s.inner = [ Foo_shamt( i )( in_ = s.in_, out = s.out[i] ) for i in range(5) ]
def construct( s ): s.in_ = InPort( Bits32 ) s.b = [ B() for _ in range(1) ] s.out = OutPort( Bits32 ) connect( s.in_, s.b[0].ifc[0].foo[0].bar[0] ) connect( s.out, s.b[0].out )
def construct( s, nbits=0 ): s.in_ = InPort ( mk_bits(nbits) ) s.out = OutPort( mk_bits(nbits) ) s.x = X()( in_ = s.in_, out = s.out )
def construct( s, shamt=1 ): s.in_ = InPort ( Bits32 ) s.out = OutPort( Bits32 )
def construct( s ): s.val = OutPort( Bits1 ) s.msg = OutPort( Bits32 ) s.rdy = InPort( Bits1 )
def construct( s ): s.foo = OutPort( Bits32 )
def construct(s):
s.msg = [InPort(Bits32) for _ in range(2)]
s.val = InPort(Bits1)
s.rdy = OutPort(Bits1)
def construct(s):
s.valrdy_ifc = InnerIfc()
s.ctrl_bar = InPort(Bits32)
s.ctrl_foo = OutPort(Bits32)
def construct(s, Type):
s.out = OutPort(Type)
def construct(s):
s.out = OutPort(B.A)
@update
def drive():
s.out @= 0
def construct(s):
s.in1 = InIfc(A.A)
s.in2 = InIfc(B.A)
s.out2 = OutPort(Bits16)
s.out2 //= s.in2.in_.a
def construct(s):
s.in_ = InPort(Bits32)
s.out = OutPort(Bits32)
s.v = VReg()
s.v.in_ //= s.in_
s.v.out //= s.out
def construct( s ):
s.in_ = [ Ifc() for _ in range(2) ]
s.out = OutPort( Bits32 )
@s.update
def upblk():
s.out = s.in_[1].foo
def construct( s, nbits=0 ):
s.in_ = InPort ( mk_bits(nbits) )
s.out = OutPort( mk_bits(nbits) )
@s.update
def up_x():
s.out = s.in_ + 1
def construct(s):
s.foo = InPort(Bits32)
s.bar = OutPort(Bits1)
connect(s.bar, s.foo[1])
def construct( s ): s.in_ = InPort( Bits32 ) s.inner = Inner() s.out = OutPort( Bits32 ) connect( s.inner.out, s.out ) connect( s.in_, s.inner.in_)
def construct(s):
s.foo = InPort(Bits32)
s.bar = OutPort(Bits4)
connect(s.bar, s.foo[0:4])
def construct( s, shamt=1 ):
s.in_ = InPort ( Bits32 )
s.out = OutPort( Bits32 )
@s.update
def up_real():
s.out = s.in_ + shamt
def construct(s):
s.foo = [InPort(Bits32) for _ in range(5)]
s.bar = OutPort(Bits32)
connect(s.bar, s.foo[1])
def construct( s ): s.ifc = [ Ifc() for _ in range(1) ] s.out = OutPort( Bits32 ) connect( s.out, s.ifc[0].foo[0].bar[0] )
def construct(s):
s.in0 = InPort(Bits32)
s.in1 = InPort(Bits32)
s.cin = InPort(Bits1)
s.out = OutPort(Bits32)
s.cout = OutPort(Bits1)
def construct( s ): s.foo = OutPort( Bits32 ) connect( s.foo, 0 )
def construct(s, Type):
s.en = InPort(Bits1)
s.rdy = OutPort(Bits1)
s.msg = InPort(Type)
def construct( s ): s.foo = InPort( Bits32 ) s.bar = OutPort( Bits32 )
def construct(s, data_width, num_entries, count_width):
s.count = OutPort(mk_bits(count_width))
s.deq = DequeueIfc(mk_bits(data_width))
s.enq = EnqueueIfc(mk_bits(data_width))
def construct(s, *args, **kwargs):
# Set up the VCD file name
verilator_vcd_file = ""
if 1:
if True:
verilator_vcd_file = "SPI_pymtl2.SPIStacks.FPUStack.test.FPUStack_test__test_stack_8bit_basic_0x0_top_fpu_stack_spi_stack_spi_loopback.verilator1.vcd"
else:
verilator_vcd_file = "SPILoopback__pack_size_128.verilator1.vcd"
# Convert string to `bytes` which is required by CFFI on python 3
verilator_vcd_file = verilator_vcd_file.encode('ascii')
# Construct the model
s._ffi_m = s._ffi_inst.create_model(
s.ffi.new("char[]", verilator_vcd_file))
# Buffer for line tracing
s._line_trace_str = s.ffi.new('char[512]')
s._convert_string = s.ffi.string
# Use non-attribute varialbe to reduce CPython bytecode count
_ffi_m = s._ffi_m
_ffi_inst_comb_eval = s._ffi_inst.comb_eval
_ffi_inst_seq_eval = s._ffi_inst.seq_eval
# declare the port interface
s.from_device = InPort(Bits128)
s.from_master = InPort(Bits128)
s.loop_en = InPort(Bits1)
s.serve = InPort(Bits1)
s.to_device = OutPort(Bits128)
s.to_master = OutPort(Bits128)
# update blocks that converts ffi interface to/from pymtl ports
s.s_DOT_from_device = Wire(Bits128)
@update
def isignal_s_DOT_from_device():
s.s_DOT_from_device @= s.from_device
s.s_DOT_from_master = Wire(Bits128)
@update
def isignal_s_DOT_from_master():
s.s_DOT_from_master @= s.from_master
s.s_DOT_loop_en = Wire(Bits1)
@update
def isignal_s_DOT_loop_en():
s.s_DOT_loop_en @= s.loop_en
s.s_DOT_serve = Wire(Bits1)
@update
def isignal_s_DOT_serve():
s.s_DOT_serve @= s.serve
s.s_DOT_to_device = Wire(Bits128)
@update
def osignal_s_DOT_to_device():
s.to_device @= s.s_DOT_to_device
s.s_DOT_to_master = Wire(Bits128)
@update
def osignal_s_DOT_to_master():
s.to_master @= s.s_DOT_to_master
@update
def comb_upblk():
# Set inputs
x = _ffi_m.from_device
x[0] = int(s.s_DOT_from_device[0:32])
x[1] = int(s.s_DOT_from_device[32:64])
x[2] = int(s.s_DOT_from_device[64:96])
x[3] = int(s.s_DOT_from_device[96:128])
x = _ffi_m.from_master
x[0] = int(s.s_DOT_from_master[0:32])
x[1] = int(s.s_DOT_from_master[32:64])
x[2] = int(s.s_DOT_from_master[64:96])
x[3] = int(s.s_DOT_from_master[96:128])
_ffi_m.loop_en[0] = int(s.s_DOT_loop_en)
_ffi_m.serve[0] = int(s.s_DOT_serve)
_ffi_inst_comb_eval(_ffi_m)
# Write all outputs
x = _ffi_m.to_device
s.s_DOT_to_device[0:32] @= x[0]
s.s_DOT_to_device[32:64] @= x[1]
s.s_DOT_to_device[64:96] @= x[2]
s.s_DOT_to_device[96:128] @= x[3]
x = _ffi_m.to_master
s.s_DOT_to_master[0:32] @= x[0]
s.s_DOT_to_master[32:64] @= x[1]
s.s_DOT_to_master[64:96] @= x[2]
s.s_DOT_to_master[96:128] @= x[3]
@update_ff
def seq_upblk():
# seq_eval will automatically tick clock in C land
_ffi_inst_seq_eval(_ffi_m)
def construct(s):
s.in_ = InPort(B)
s.out = OutPort(Bits32)
connect(s.out, s.in_.foo)
