def test_c9_rom(self, c9_top_rom): # Read ROM table component ID. cmpid = CoreSightComponentID(None, c9_top_rom, MockCSSOC600Components.C9_ROM_TABLE_BASE) cmpid.read_id_registers() # Create the ROM table. rom_table = ROMTable.create(c9_top_rom, cmpid) rom_table.init() # Validate ROM table properties. assert rom_table._width == 32 assert not rom_table.has_com_port assert rom_table.has_prr assert not rom_table.is_sysmem # Validate components. assert len(rom_table.components) == 2 # Validate SDC-600. sdc = rom_table.components[0] assert sdc.component_class == 9 assert sdc.designer == 0x43b assert sdc.part == 0x9ef assert sdc.archid == 0xa57 # Validate AHB-AP. ahb = rom_table.components[1] assert ahb.component_class == 9 assert ahb.designer == 0x43b assert ahb.part == 0x9e3 assert ahb.archid == 0xa17
def test_c9_rom(self): cmp = CoreSightComponentID( None, MockCoreSight([MockCSSOC600Components.C9_ROM_TABLE]), MockCSSOC600Components.C9_ROM_TABLE_BASE) cmp.read_id_registers() assert cmp.component_class == 9 assert cmp.is_rom_table
def test_scs(self): cmp = CoreSightComponentID(None, MockCoreSight([MockM4Components.SCS]), MockM4Components.SCS_BASE) cmp.read_id_registers() assert cmp.component_class == 14 assert cmp.designer == 0x43b assert cmp.part == 0xc assert cmp.devarch == 0 assert cmp.devid == [0, 0, 0]
def test_etm(self): cmp = CoreSightComponentID(None, MockCoreSight([MockM4Components.ETM]), MockM4Components.ETM_BASE) cmp.read_id_registers() assert cmp.component_class == 9 assert cmp.designer == 0x43b assert cmp.part == 0x925 assert cmp.devtype == 0x13 assert cmp.archid == 0 assert cmp.devarch == 0 assert cmp.devid == [0, 0, 0]
def test_tpiu(self): cmp = CoreSightComponentID(None, MockCoreSight([MockM4Components.TPIU]), MockM4Components.TPIU_BASE) cmp.read_id_registers() assert cmp.component_class == 9 assert cmp.designer == 0x43b assert cmp.part == 0x9a1 assert cmp.devtype == 0x11 assert cmp.archid == 0 assert cmp.devarch == 0 assert cmp.devid == [0xca1, 0, 0]
def sdc(): cs = MockCoreSight([MockCSSOC600Components.SDC600]) # Add SDC-600 register values. cs.write_memory_block32(0xd00, [ 0x00000000, # VIDR = 0xD00 0, # 0xD04 0x00000411, # FIDTXR = 0xD08 0x00000401, # FIDRXR = 0xD0C 0x00000000, # ICSR = 0xD10 0, # 0xD14 0, # 0xD18 0, # 0xD1C 0x00000000, # DR = 0xD20 0, # 0xD24 0, # 0xD28 0x80011001, # SR = 0xD2C 0x00000000, # DBR = 0xD30 0, # 0xD34 0, # 0xD38 0x80011001, # SR_ALIAS = 0xD3C ]) cmpid = CoreSightComponentID(None, cs, MockCSSOC600Components.SDC600_BASE) sdc600 = SDC600(cs, cmpid, 0x1000) sdc600.init() return sdc600
def test_m4_rom(self, m4_rom): # Read ROM table component ID. cmpid = CoreSightComponentID(None, m4_rom, MockM4Components.M4_ROM_TABLE_BASE) cmpid.read_id_registers() # Create the ROM table. rom_table = ROMTable.create(m4_rom, cmpid) rom_table.init() # Verify all components were parsed. assert len(rom_table.components) == 6 # Check SCS-M4. scs = rom_table.components[0] assert scs.component_class == 14 assert scs.designer == 0x43b assert scs.part == 0xc # Check TPIU. tpiu = rom_table.components[4] assert tpiu.component_class == 9 assert tpiu.part == 0x9a1 assert tpiu.devid == [0xca1, 0, 0]