check=False,
encoding='utf-8',
env=os.environ,
)
def run(c, run_opts=default_run_opts):
print(c)
subprocess.run(c, **run_opts)
root = '..'
design = ys.Design()
ys.run_pass(
f"verilog_defaults -add -I{root}/src/main/resources/rtl_v1/include",
design)
ys.run_pass(f"read_verilog {root}/work/chisel/copperv2.v", design)
ys.run_pass(f"read_verilog {root}/src/main/resources/rtl_v1/execution.v",
design)
ys.run_pass(f"read_verilog {root}/src/main/resources/rtl_v1/register_file.v",
design)
ys.run_pass(f"read_verilog {root}/src/main/resources/rtl_v1/idecoder.v",
design)
ys.run_pass(f"prep -auto-top", design)
ys.run_pass("select -module Copperv2Core c:$*", design)
ys.run_pass("submod -name bus_if", design)
ys.run_pass("cd", design)
#!/usr/bin/python3
from pyosys import libyosys as ys
import matplotlib.pyplot as plt
import numpy as np
design = ys.Design()
ys.run_pass("read_verilog ../../tests/simple/fiedler-cooley.v", design)
ys.run_pass("prep", design)
ys.run_pass("opt -full", design)
cell_stats = {}
for module in design.selected_whole_modules_warn():
for cell in module.selected_cells():
if cell.type.str() in cell_stats:
cell_stats[cell.type.str()] += 1
else:
cell_stats[cell.type.str()] = 1
plt.bar(range(len(cell_stats)),
height=list(cell_stats.values()),
align='center')
plt.xticks(range(len(cell_stats)), list(cell_stats.keys()))
plt.show()
def toolchain_prepare(self, fragment, name, **kwargs):
rtlil_text, self._name_map = rtlil.convert_fragment(fragment,
name=name)
build_dir = "build"
os.makedirs(build_dir, exist_ok=True)
with open(f"{build_dir}/{name}.il", "w") as f:
f.write(rtlil_text)
# For some reason running abc (which is run in synth) from
# Python requires yosys-abc at /usr/bin. Maybe because it
# just takes the exe dir from the currently running executable
# (/usr/bin/python3)?
py_register_pass(ReplaceSopWithNotPass())
py_register_pass(CoalesceNotWithSopPass())
py_register_pass(SplitLargeSopPass())
py_register_pass(AddIOMacrocellsPass(self.device))
py_register_pass(AllocateSOPMacrocellsPass(self.device))
py_register_pass(SetUIMPass(self.device))
py_register_pass(WriteJEDPass(self.device))
ys.Pass.init_register()
design = ys.Design()
ys.run_pass(f"read_ilang {build_dir}/{name}.il", design)
ys.run_pass("delete w:$verilog_initial_trigger", design)
ys.run_pass("proc", design)
ys.run_pass("flatten", design)
ys.run_pass("stat", design)
ys.run_pass("synth", design)
py_run_pass("next_pass", design)
ys.run_pass("clean", design)
ys.run_pass("opt -full", design)
ys.run_pass("stat", design)
ys.run_pass("abc -sop -I 40 -P 5", design)
ys.run_pass("clean", design)
ys.run_pass("stat", design)
ys.run_pass(f"write_ilang {build_dir}/{name}_pass1.il", design)
py_run_pass("replace_sop_with_not", design)
py_run_pass("split_large_sop", design)
ys.run_pass(f"write_ilang {build_dir}/{name}_pass2.il", design)
py_run_pass("coalesce_not_with_sop", design)
ys.run_pass(f"write_ilang {build_dir}/{name}_pass3.il", design)
py_run_pass("add_io_macrocells", design)
ys.run_pass(f"write_ilang {build_dir}/{name}_pass4.il", design)
py_run_pass("allocate_sop_macrocells", design)
ys.run_pass(f"write_ilang {build_dir}/{name}_pass5.il", design)
py_run_pass("set_uims", design)
ys.run_pass(f"write_ilang {build_dir}/{name}_pass6.il", design)
py_run_pass(f"write_jed {build_dir}/out.jed", design)
plan = BuildPlan(script=f"build_{name}")
plan.add_file(f"build_{name}.sh", "")
return plan
#!/usr/bin/python3
from pyosys import libyosys as ys
import matplotlib.pyplot as plt
import numpy as np
design = ys.Design()
ys.run_pass("read_verilog ../../tests/simple/fiedler-cooley.v", design);
ys.run_pass("prep", design)
ys.run_pass("opt -full", design)
cell_stats = {}
for module in design.selected_whole_modules_warn():
for cell in module.selected_cells():
if cell.type.str() in cell_stats:
cell_stats[cell.type.str()] += 1
else:
cell_stats[cell.type.str()] = 1
plt.bar(range(len(cell_stats)), height = list(cell_stats.values()),align='center')
plt.xticks(range(len(cell_stats)), list(cell_stats.keys()))
plt.show()
def test_count_modules(yosys):
design = ys.Design()
ys.run_pass("read_verilog verilog/simple.v", design)
ys.run_pass("proc", design)
assert (len(design.modules_.keys()) == 2)
def test_top_module(yosys):
design = ys.Design()
ys.run_pass("read_verilog verilog/simple.v", design)
ys.run_pass("synth_ice40", design)
assert (ys.unescape_id(design.top_module().name) == "main")