def assy_eax(self, pj, eam, ear):
eax = 1 << eam
if eax > 0x40:
eax = 0x100 << ear
eamask = int(self.im.assy[-1], 16)
if not eax & eamask:
print ("0x%x Wrong EA mode m=%d/r=%d" % (self.lo, eam, ear))
raise assy.Invalid("0x%x Wrong EA mode m=%d/r=%d" % (
self.lo, eam, ear))
if eax == 0x0001:
return "D%d" % ear
if eax == 0x0002:
return "A%d" % ear
if eax == 0x0004:
return "(A%d)" % ear
if eax == 0x0008:
return "(A%d)+" % ear
if eax == 0x0010:
return "-(A%d)" % ear
if eax == 0x0020:
o = pj.m.bs16(self.hi)
self.hi += 2
if o < 0:
return "(A%d-0x%x)" % (ear, -o)
else:
return "(A%d+0x%x)" % (ear, o)
if eax == 0x0040:
return self.assy_eaxt(pj, "A%d" % ear)
if eax == 0x0100:
o = pj.m.bu16(self.hi)
self.hi += 2
if o & 0x8000:
o |= 0xffff0000
self.dstadr = o
return assy.Arg_dst(pj, o)
if eax == 0x0200:
o = pj.m.bu32(self.hi)
self.hi += 4
self.dstadr = o
return assy.Arg_dst(pj, o)
if eax == 0x0400:
o = self.hi + pj.m.bs16(self.hi)
self.hi += 2
self.dstadr = o
return assy.Arg_dst(pj, o)
if eax == 0x0800:
return self.assy_eaxt(pj, "PC")
if eax == 0x1000 and self.sz == 1:
self.hi += 2
return "#0x%02x" % pj.m.rd(self.hi-1)
if eax == 0x1000 and self.sz == 2:
self.hi += 2
return "#0x%04x" % pj.m.bu16(self.hi-2)
if eax == 0x1000 and self.sz == 4:
self.hi += 4
return "#0x%08x" % pj.m.bu32(self.hi-4)
print("0x%x EA? 0x%04x m=%d/r=%d" % (self.lo, eax, eam, ear))
raise assy.Invalid("0x%x EA? 0x%04x m=%d/r=%d" % (self.lo, eax, eam, ear))
def assy_Pzy(self):
d = self.lang.m[self.hi]
self.hi += 1
return [
assy.Arg_dst(self.lang.m, d),
assy.Arg_verbatim("Y"),
]
def assy_rel2(self):
self.dstadr = self['c1']
self.dstadr |= self['c2'] << 4
if self.dstadr & 0x80:
self.dstadr -= 0x100
self.dstadr += (self.hi - 2)
return assy.Arg_dst(self.lang.m, self.dstadr)
def assy_Absy(self):
d = self.lang.m.lu16(self.hi)
self.hi += 2
return [
assy.Arg_dst(self.lang.m, d),
assy.Arg_verbatim("Y"),
]
def assy_Indy(self):
d = self.lang.m[self.hi]
self.hi += 1
return [
assy.Arg_dst(self.lang.m, d, pfx="(", sfx=")"),
assy.Arg_verbatim("Y"),
]
def assy_e(self):
self.dstadr = self.hi
e = self['e']
if e & 0x80:
e -= 256
self.dstadr += e
return assy.Arg_dst(self.lang.m, self.dstadr)
def assy_abs5(self):
self.dstadr = self['c1']
self.dstadr |= self['c2'] << 4
self.dstadr |= self['c3'] << 8
self.dstadr |= self['c4'] << 12
self.dstadr |= self['c5'] << 16
return assy.Arg_dst(self.lang.m, self.dstadr)
def assy_rel(self):
""" Relative address """
d = self['disp']
if d & 0x80:
d -= 256
self.dstadr = self.hi + d
return assy.Arg_dst(self.lang.m, self.dstadr)
def assy_e(self, pj):
self.dstadr = self.hi
e = self['e']
if e & 0x80:
e -= 256
self.dstadr += e
return assy.Arg_dst(pj, self.dstadr)
def assy_pgadr(self):
self.dst_pg = self['pgno']
self.dst_off = (self['ahi'] << 8) | self['alo']
self.lang[self.dst_pg].m.set_block_comment(
self.dst_off, "LJMP target from " + self.lang.m.afmt(self.lo))
self.lang[self.dst_pg].disass(self.dst_off)
return assy.Arg_dst(self.lang[self.dst_pg].m, self.dst_off)
def assy_Rel(self):
""" 16 bit Relative address """
d = self['i1'] | (self['i2'] << 8)
if d & 0x8000:
d -= 65536
self.dstadr = self.hi + d
return assy.Arg_dst(self.lang.m, self.dstadr)
def assy_dst(self):
o = self['off'] << 2
if o & (1 << 25):
o |= 0xfc000000
self.dstadr = 4 + (self.hi + o) & 0xffffffff
if self.mne.find("L") != -1:
self.lang.m.set_block_comment(self.dstadr, "from %x" % self.lo)
return assy.Arg_dst(self.lang.m, self.dstadr, "")
def assy_rel3b(self):
self.dstadr = self['c1']
self.dstadr |= self['c2'] << 4
self.dstadr |= self['c3'] << 8
if self.dstadr & 0x800:
self.dstadr -= 0x1000
self.dstadr += self.hi
return assy.Arg_dst(self.lang.m, self.dstadr)
def assy_r(self, pj):
a = self['r']
if a & 0x80:
a -= 256
self.dstadr = self.hi + a
if self.mne != "BRA":
self.cc = self.mne[1:]
return assy.Arg_dst(pj, self.dstadr)
def assy_subr(self):
''' ... '''
adr = self['x'] + 0x18
self.dstadr = self.lang.m[adr]
if not self.dstadr:
raise assy.Invalid()
self.lang.codeptr(adr)
self.lang.subrs.add(self.dstadr)
return assy.Arg_dst(self.lang.m, self.dstadr)
def assy_rel4(self):
self.dstadr = self['c1']
self.dstadr |= self['c2'] << 4
self.dstadr |= self['c3'] << 8
self.dstadr |= self['c4'] << 12
if self.dstadr & 0x8000:
self.dstadr -= 0x10000
self.dstadr += (self.hi - 4)
return assy.Arg_dst(self.lang.m, self.dstadr)
def assy_skip(self):
s = self['skip']
d = self['d']
if d:
s = 0x20 - s
self.dstadr = self.lo - s
else:
self.dstadr = self.lo + s
self += code.Jump(cond="?s", to=self.hi)
self += code.Jump(cond="?!s", to=self.dstadr)
return assy.Arg_dst(self.lang.m, self.dstadr)
def assy_da(self):
i = self["idx"]
d = self["displ"]
t = None
asp = self.lang.m
if i == 0:
return assy.Arg_dst(self.lang.page_zero_asp, d)
if d & 0x80:
d -= 256
if i == 1:
t = self.lo + d
if not self['i']:
self.dstadr = t
return assy.Arg_dst(asp, t)
for j in self.lang.ac23:
k = j(self.lo, i, d)
if k:
return k
if d < 0:
return "-0x%x,%d" % (-d, i)
return "0x%x,%d" % (d, i)
def assy_dst(self, pj):
x = self['disp8']
if x == 0x00:
self.dstadr = self.hi + pj.m.bs16(self.hi)
self.hi += 2
elif x == 0xff:
self.dstadr = self.hi + pj.m.bs32(self.hi)
self.hi += 4
elif x & 0x80:
self.dstadr = self.hi + x - 0x100
else:
self.dstadr = self.hi + x
return assy.Arg_dst(pj, self.dstadr)
def assy_dst(self, cde=True):
a = self['adr']
if a & 0x200:
a -= 0x400
if self['c']:
a += self.lo
dd = (a + (1 << 16)) & 0x7fff
if not self['d']:
if cde:
self.dstadr = dd
return assy.Arg_dst(self.lang.m, dd)
try:
d = self.lang.m[dd]
y = data.Data(self.lang.m, dd, dd + 1)
y.rendered = ".REF\t0x%04x" % d
if cde:
self.dstadr = d
return [assy.Arg_dst(self.lang.m, d), assy.Arg_verbatim("[Via 0x%04x]" % dd)]
except mem.MemError:
pass
if cde:
self.dstadr = dd
return [assy.Arg_dst(self.lang.m, dd), assy.Arg_verbatim("I")]
def assy_dst(self):
x = self['disp8']
if x == 0x00:
self.dstadr = self.hi + self.lang.m.bs16(self.hi)
self.hi += 2
elif x == 0xff:
self.dstadr = self.hi + self.lang.m.bs32(self.hi)
self.hi += 4
elif x & 0x01:
raise assy.Invalid("Odd numbered destination address")
elif x & 0x80:
self.dstadr = self.hi + x - 0x100
else:
self.dstadr = self.hi + x
return assy.Arg_dst(self.lang.m, self.dstadr)
def assy_Dst1011(self):
i1 = not (self['j'] ^ self['s'])
i2 = not (self['k'] ^ self['s'])
imm32 = self['s'] * 0xff
imm32 <<= 1
imm32 |= i1
imm32 <<= 1
imm32 |= i2
imm32 <<= 10
imm32 |= self['imm10']
imm32 <<= 11
imm32 |= self['imm11']
imm32 <<= 1
self.dstadr = (self.hi + imm32) & 0xffffffff
return assy.Arg_dst(self.lang.m, self.dstadr)
def assy_a_rn(self):
''' Addressing mode Rn/U/P/W '''
imm32 = self['imm12']
rn = REG[self['rn']]
if self['u']:
imm = "#0x%x" % imm32
else:
imm = "#-0x%x" % imm32
p = self.lim[-1].flds.get('p')
w = self.lim[-1].flds.get('w')
if not p:
if not w:
#return [assy.Arg_verbatim("[%s]" % rn), assy.Arg_dst(self.lang.m, imm)]
return "[%s]," % rn + imm
raise assy.Invalid("a_rn mode wrong (!p,w)")
if w:
return "[%s," % rn + imm + "]!"
if self['rn'] != 15 or OBJDUMP_COMPAT:
if imm32:
return "[%s," % rn + imm + "]"
return "[%s]" % rn
if self['u']:
t = self.hi + 4 + imm32
else:
t = self.hi + 4 - imm32
try:
v = self.lang.m.lu32(t)
if not self.lang.m.occupied(t):
data.Const(self.lang.m,
t,
t + 4,
func=self.lang.m.lu32,
size=4)
self.lcmt += "[%s,%s] = [#0x%x]\n" % (rn, imm, t)
return assy.Arg_dst(self.lang.m, v, pfx="#")
return "#0x%x" % v
except:
self.lcmt += "[%s,%s]\n" % (rn, imm)
return "[#0x%x]" % t
def arg_o(self, pj, sd):
to = self['t' + sd]
o = self[sd]
nm = 'G' + sd
if to == 0:
return "R%d" % o
if to == 1:
return "*R%d" % o
if to == 2:
v = pj.m.bu16(self.hi)
self.hi += 2
self[nm] = v
if o != 0:
return "R%d+#0x%04x" % (o, v)
x = pj.find(v)
if len(x) > 0:
return assy.Arg_ref(pj, x[0])
try:
w = pj.m.bu16(v)
except:
return assy.Arg_dst(pj, v, "@")
# print("XXX", "%04x" % v, "%04x" % w, self.mne)
if self.mne[-1] == "b":
c = data.Const(pj, v, v + 1)
c.typ = ".BYTE"
c.fmt = "0x%02x" % pj.m.rd(v)
else:
c = data.Const(pj, v, v + 2)
c.typ = ".WORD"
c.fmt = "0x%04x" % w
return assy.Arg_ref(pj, c)
if to == 3:
return "*R%d+" % o
def arg_o(self, sd):
to = self['t' + sd]
o = self[sd]
nm = 'G' + sd
if to == 0:
return "R%d" % o
if to == 1:
return "*R%d" % o
if to == 2:
v = self.lang.m.bu16(self.hi)
self.hi += 2
self[nm] = v
if o != 0:
return "R%d+#0x%04x" % (o, v)
x = list(self.lang.m.find(v))
if x:
return assy.Arg_ref(self.lang.m, x[0])
try:
w = self.lang.m.bu16(v)
except:
return assy.Arg_dst(self.lang.m, v, "@")
if self.mne[-1] == "b":
c = data.Const(self.lang.m, v, v + 1)
c.typ = ".BYTE"
c.fmt = "0x%02x" % self.lang.m[v]
else:
c = data.Const(self.lang.m, v, v + 2)
c.typ = ".WORD"
c.fmt = "0x%04x" % w
return assy.Arg_ref(self.lang.m, c)
if to == 3:
return "*R%d+" % o
def assy_ladr(self):
self.dstadr = (self['ahi'] << 8) | self['alo']
return assy.Arg_dst(self.lang.m, self.dstadr)
def assy_adr(self):
self.dstadr = (self.lo & ~0xff) | self['adr']
return assy.Arg_dst(self.lang.m, self.dstadr)
def assy_da(self):
""" Direct address """
self.dstadr = self['alo'] | self['ahi'] << 8
return assy.Arg_dst(self.lang.m, self.dstadr)
def assy_i2(self):
""" Immediate 16 bit """
self.dstadr = self['i1'] | self['i2'] << 8
return assy.Arg_dst(self.lang.m, self.dstadr, "#")
def assy_io1(self):
""" Immediate I/O 8 bit """
return assy.Arg_dst(self.lang.as_io, self['io1'], "#")
