def test_blif_input_simulates_correctly_with_merged_outputs(self):
# The 'counter_blif' string contains a model of a standard 4-bit synchronous-reset
# counter with enable. In particular, the model has 4 1-bit outputs named "count[0]",
# "count[1]", "count[2]", and "count[3]". The internal PyRTL representation will by
# default convert these related 1-bit wires into a single 4-bit wire called "count".
# This test simulates the design and, among other things, ensures that this output
# wire conversion occurred correctly.
pyrtl.input_from_blif(counter4bit_blif)
io_vectors = pyrtl.working_block().wirevector_subset(
(pyrtl.Input, pyrtl.Output))
sim_trace = pyrtl.SimulationTrace(wires_to_track=io_vectors)
sim = pyrtl.Simulation(sim_trace)
inputs = {
'rst': [1] + [0] * 20,
'en': [1] + [1] * 20,
}
expected = {'count': [0] + list(range(0, 16)) + list(range(0, 4))}
sim.step_multiple(inputs, expected)
correct_output = (
" --- Values in base 10 ---\n"
"count 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3\n"
"en 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1\n"
"rst 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n"
)
output = six.StringIO()
sim_trace.print_trace(output)
self.assertEqual(output.getvalue(), correct_output)
def test_combo_blif_input_no_crashy(self):
pyrtl.input_from_blif(full_adder_blif)
x, y, cin = [
pyrtl.working_block().get_wirevector_by_name(s)
for s in ['x', 'y', 'cin']
]
io_vectors = pyrtl.working_block().wirevector_subset(
(pyrtl.Input, pyrtl.Output))
def test_output_to_graphviz_with_custom_namer_does_not_throw_error(self):
from .test_importexport import full_adder_blif
with io.StringIO() as vfile:
pyrtl.input_from_blif(full_adder_blif)
timing = pyrtl.TimingAnalysis()
node_fan_in = {net: len(net.args) for net in pyrtl.working_block()}
graph_namer = pyrtl.graphviz_detailed_namer(
extra_node_info=node_fan_in, extra_edge_info=timing.timing_map)
pyrtl.output_to_graphviz(vfile, namer=graph_namer)
def test_output_to_graphviz_with_custom_edge_namer_does_not_throw_error(
self):
with io.StringIO() as vfile:
pyrtl.input_from_blif(full_adder_blif)
timing = analysis.TimingAnalysis()
def graph_namer(t, i, j):
edge_namer = pyrtl.inputoutput.detailed_edge_namer(
timing.timing_map)
return pyrtl.inputoutput.graphviz_default_namer(
t, i, j, edge_namer=edge_namer)
pyrtl.output_to_graphviz(vfile, namer=graph_namer)
def test_blif_with_output_as_arg(self):
pyrtl.input_from_blif(blif_with_output_as_arg)
inw, outw = [
pyrtl.working_block().get_wirevector_by_name(s)
for s in ['in', 'out']
]
self.assertIsNotNone(inw)
self.assertIsNotNone(outw)
self.assertEquals(len(inw), 2)
self.assertEquals(len(outw), 1)
io_input = pyrtl.working_block().wirevector_subset(pyrtl.Input)
self.assertIn(inw, io_input)
io_output = pyrtl.working_block().wirevector_subset(pyrtl.Output)
self.assertIn(outw, io_output)
def test_sequential_blif_input_has_correct_io_interface_counter(self):
pyrtl.input_from_blif(counter4bit_blif)
rst, en, count = [
pyrtl.working_block().get_wirevector_by_name(s)
for s in ['rst', 'en', 'count']
]
self.assertIsNotNone(rst)
self.assertIsNotNone(en)
self.assertIsNotNone(count)
self.assertEquals(len(rst), 1)
self.assertEquals(len(en), 1)
self.assertEquals(len(count), 4)
io_input = pyrtl.working_block().wirevector_subset(pyrtl.Input)
self.assertIn(rst, io_input)
self.assertIn(en, io_input)
io_output = pyrtl.working_block().wirevector_subset(pyrtl.Output)
self.assertIn(count, io_output)
def test_sequential_blif_input_has_correct_io_interface(self):
pyrtl.input_from_blif(state_machine_blif)
inw, reset, out = [
pyrtl.working_block().get_wirevector_by_name(s)
for s in ['in', 'reset', 'out']
]
self.assertIsNotNone(inw)
self.assertIsNotNone(reset)
self.assertIsNotNone(out)
self.assertEquals(len(inw), 1)
self.assertEquals(len(reset), 1)
self.assertEquals(len(out), 4)
io_input = pyrtl.working_block().wirevector_subset(pyrtl.Input)
self.assertIn(inw, io_input)
self.assertIn(reset, io_input)
io_output = pyrtl.working_block().wirevector_subset(pyrtl.Output)
self.assertIn(out, io_output)
def test_combo_blif_input_has_correct_io_interface(self):
pyrtl.input_from_blif(full_adder_blif)
x, y, cin, sumw, cout, bad = [
pyrtl.working_block().get_wirevector_by_name(s)
for s in ['x', 'y', 'cin', 'sum', 'cout', 'bad']
]
self.assertIsNotNone(x)
self.assertIsNotNone(y)
self.assertIsNotNone(cin)
self.assertIsNotNone(sumw)
self.assertIsNotNone(cout)
self.assertIsNone(bad)
self.assertEquals(len(x), 1)
self.assertEquals(len(y), 1)
self.assertEquals(len(cin), 1)
self.assertEquals(len(sumw), 1)
self.assertEquals(len(cout), 1)
io_input = pyrtl.working_block().wirevector_subset(pyrtl.Input)
self.assertIn(x, io_input)
self.assertIn(y, io_input)
self.assertIn(cin, io_input)
io_output = pyrtl.working_block().wirevector_subset(pyrtl.Output)
self.assertIn(sumw, io_output)
self.assertIn(cout, io_output)
def test_output_to_graphviz_does_not_throw_error(self):
with io.StringIO() as vfile:
pyrtl.input_from_blif(full_adder_blif)
pyrtl.output_to_graphviz(vfile)
def test_sequential_blif_input_fails_to_parse_with_bad_latch_init(self):
with self.assertRaises(pyrtl.PyrtlError):
pyrtl.input_from_blif(counter4bit_blif_bad_latch_inits)
def test_output_to_tgf_does_not_throw_error(self):
with io.StringIO() as vfile:
pyrtl.input_from_blif(full_adder_blif)
pyrtl.output_to_trivialgraph(vfile)
def test_romblock_does_not_throw_error(self):
pyrtl.input_from_blif(full_adder_blif)
x, y, cin = [pyrtl.working_block().get_wirevector_by_name(s) for s in ['x', 'y', 'cin']]
io_vectors = pyrtl.working_block().wirevector_subset((pyrtl.Input, pyrtl.Output))
def test_output_to_tgf_does_not_throw_error(self):
from .test_importexport import full_adder_blif
with io.StringIO() as vfile:
pyrtl.input_from_blif(full_adder_blif)
pyrtl.output_to_trivialgraph(vfile)
def test_sequential_blif_input_no_crashy(self):
pyrtl.input_from_blif(state_machine_blif)
io = pyrtl.working_block().wirevector_subset((pyrtl.Input, pyrtl.Output))
def test_combo_blif_input_no_crashy(self):
pyrtl.input_from_blif(full_adder_blif)
x, y, cin = [pyrtl.working_block().get_wirevector_by_name(s) for s in ['x', 'y', 'cin']]
io_vectors = pyrtl.working_block().wirevector_subset((pyrtl.Input, pyrtl.Output))
def test_sequential_blif_input_no_crashy(self):
pyrtl.input_from_blif(state_machine_blif)
io = pyrtl.working_block().wirevector_subset((pyrtl.Input, pyrtl.Output))
.names x y $and$FA.v:19$11_Y
11 1
.names ind0 ind1 ind2
1- 1
-1 1
.names cin ind2 $and$FA.v:19$12_Y
11 1
.names $and$FA.v:19$11_Y $and$FA.v:19$12_Y cout
1- 1
-1 1
.names $not$FA.v:11$1_Y y ind0
11 1
.end
"""
pyrtl.input_from_blif(full_adder_blif)
# Have to find the actual wire vectors generated from the names in the blif file
x, y, cin = [
pyrtl.working_block().get_wirevector_by_name(s) for s in ['x', 'y', 'cin']
]
io_vectors = pyrtl.working_block().wirevector_subset(
(pyrtl.Input, pyrtl.Output))
# We are only going to trace the input and output vectors for clarity
sim_trace = pyrtl.SimulationTrace(wires_to_track=io_vectors)
# Now simulate the logic with some random inputs
sim = pyrtl.Simulation(tracer=sim_trace)
for i in range(15):
# here we actually generate random booleans for the inputs
sim.step({
'x': random.choice([0, 1]),
.names x y $and$FA.v:19$11_Y
11 1
.names ind0 ind1 ind2
1- 1
-1 1
.names cin ind2 $and$FA.v:19$12_Y
11 1
.names $and$FA.v:19$11_Y $and$FA.v:19$12_Y cout
1- 1
-1 1
.names $not$FA.v:11$1_Y y ind0
11 1
.end
"""
pyrtl.input_from_blif(full_adder_blif)
# have to find the actual wire vectors generated from the names in the blif file
x, y, cin = [pyrtl.working_block().get_wirevector_by_name(s) for s in ['x', 'y', 'cin']]
io_vectors = pyrtl.working_block().wirevector_subset((pyrtl.Input, pyrtl.Output))
# we are only going to trace the input and output vectors for clarity
sim_trace = pyrtl.SimulationTrace(wirevector_subset=io_vectors)
# now simulate the logic with some random inputs
sim = pyrtl.Simulation(tracer=sim_trace)
for i in range(15):
# here we actually generate random booleans for the inputs
sim.step({
x: random.choice([0, 1]),
y: random.choice([0, 1]),
cin: random.choice([0, 1])
})