def test_simple_probe_debug(self):
pyrtl.set_debug_mode()
i = pyrtl.Input(1)
o = pyrtl.Output(1)
output = six.StringIO()
sys.stdout = output
o <<= pyrtl.probe(i + 1, name="probe0")
sys.stdout = sys.__stdout__
self.assertTrue(output.getvalue().startswith("Probe: probe0"))
pyrtl.set_debug_mode(False)
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)
for cycle in range(len(vals1)):
sim.step({'in1': vals1[cycle], 'in2': vals2[cycle]})
# Now we will show the values of the inputs and probes
# and look at that, we didn't need to make any outputs!
# (although we did, to demonstrate the power and convenience of probes)
sim_trace.render_trace()
sim_trace.print_trace()
print("--- Probe w/ debugging: ---")
# Say we wanted to have gotten more information about
# one of those probes above at declaration.
# We could have used pyrtl.set_debug_mode() before their creation, like so:
pyrtl.set_debug_mode()
pyrtl.probe(multout - 16, 'debugsubtr_probe)')
pyrtl.set_debug_mode(debug=False)
# ---- WireVector Stack Trace ----
# Another case that might arise is that a certain wire is causing an error to occur
# in your program. WireVector Stack Traces allow you to find out more about where a particular
# WireVector was made in your code. With this enabled the WireVector will
# store exactly were it was created, which should help with issues where
# there is a problem with an identified wire.
# Like above, just add the following line before the relevant WireVector
# might be made or at the beginning of the program.
pyrtl.set_debug_mode()
def test_simple_probe_debug(self):
pyrtl.set_debug_mode()
i = pyrtl.Input(1)
o = pyrtl.Output(1)
o <<= pyrtl.probe(i + 1)
pyrtl.set_debug_mode(False)
def test_get_call_stack(self):
pyrtl.set_debug_mode(True)
wire = pyrtl.WireVector()
call_stack = wire.init_call_stack
self.assertIsInstance(call_stack, list)
def test_no_call_stack(self):
pyrtl.set_debug_mode(False)
wire = pyrtl.WireVector()
with self.assertRaises(AttributeError):
call_stack = wire.init_call_stack
def tearDownClass(cls):
pyrtl.set_debug_mode(False)
def test_simple_probe_debug(self):
pyrtl.set_debug_mode()
i = pyrtl.Input(1)
o = pyrtl.Output(1)
o <<= pyrtl.probe(i + 1)
pyrtl.set_debug_mode(False)
#!/usr/bin/env python
# -*- coding: utf-8 -*-
import pyrtl
pyrtl.set_debug_mode(debug=True)
DATA_WIDTH = 8
ADDR_WIDTH = 8
RAM_DEPTH = 1 << 8
address = pyrtl.Input(ADDR_WIDTH, "address")
cs = pyrtl.Input(1, "cs")
we = pyrtl.Input(1, "we")
oe = pyrtl.Input(1, "oe")
data_in = pyrtl.Input(DATA_WIDTH, "data_in")
data_out = pyrtl.Output(DATA_WIDTH, "data_out")
mem = pyrtl.memory.MemBlock(RAM_DEPTH, ADDR_WIDTH,
name="mem", asynchronous=True)
mem[address] <<= pyrtl.MemBlock.EnabledWrite(data_in, we & cs)
data_out_wire = pyrtl.wire.WireVector(DATA_WIDTH, "DATA_WIDTH")
with pyrtl.conditional_assignment:
with cs:
with we:
pass
with pyrtl.otherwise:
with oe:
data_out_wire |= mem[address]
# pyrtl.reset_working_block() # ... # ----Wirevector Stack Trace ---- # Another case that might arise is that a certain wire is causing an error to occur # in your program. Wirevector Stack Traces allow you to find out more about where a particular # wirevector was made in your code. With this enabled the wirevector will # store exactly were it was created, which should help with issues where # there is a problem with an indentified wire. # To enable this, just add the following line before the relevant wirevector # might be made or at the beginning of the program. pyrtl.set_debug_mode() # a test wire to show this feature test_out = pyrtl.Output(9, "test_out") test_out <<= adders.kogge_stone(in1, in3) # Now to retrieve information wire_trace = test_out.init_call_stack # This data is generated using the traceback.format_stack() call from the Python # standard library's Traceback module (look at the Python standard library docs for # details on the function). Therefore, the stack traces are stored as a list with the # outermost call first. # for frame in wire_trace:
for cycle in range(len(vals1)):
sim.step({
'in1': vals1[cycle],
'in2': vals2[cycle]})
# Now we will show the values of the inputs and probes
# and look at that, we didn't need to make any outputs!
# (although we did, to demonstrate the power and convenience of probes)
sim_trace.render_trace()
sim_trace.print_trace()
print("--- Probe w/ debugging: ---")
# Say we wanted to have gotten more information about
# one of those probes above at declaration.
# We could have used pyrtl.set_debug_mode() before their creation, like so:
pyrtl.set_debug_mode()
pyrtl.probe(multout - 16, 'debugsubtr_probe)')
pyrtl.set_debug_mode(debug=False)
# ---- WireVector Stack Trace ----
# Another case that might arise is that a certain wire is causing an error to occur
# in your program. WireVector Stack Traces allow you to find out more about where a particular
# WireVector was made in your code. With this enabled the WireVector will
# store exactly were it was created, which should help with issues where
# there is a problem with an identified wire.
# Like above, just add the following line before the relevant WireVector
# might be made or at the beginning of the program.
