def main():
a = vast.Identifier('a')
b = vast.Identifier('b')
c = vast.Plus(a, b)
ids = getIdentifiers(c)
print(ids)
def build_package_axi(self, configs, synthesized_code, common_code,
masterlist, slavelist, top_parameters, top_ioports,
userlogic_topmodule, memimg, usertest,
ignore_protocol_error):
code = synthesized_code + common_code
# default values
ext_burstlength = 256
# write to files, with AXI interface
def_top_parameters = []
def_top_localparams = []
def_top_ioports = []
name_top_ioports = []
mpd_parameters = []
mpd_ports = []
ext_params = []
ext_ports = []
asttocode = ASTCodeGenerator()
for pk, pv in top_parameters.items():
r = asttocode.visit(pv)
def_top_parameters.append(r)
if r.count('localparam'):
def_top_localparams.append(r)
continue
_name = pv.name
_value = asttocode.visit(pv.value)
_dt = 'string' if r.count('"') else 'integer'
mpd_parameters.append((_name, _value, _dt))
for pk, (pv, pwidth) in top_ioports.items():
name_top_ioports.append(pk)
new_pv = vast.Wire(pv.name, pv.width, pv.signed)
def_top_ioports.append(asttocode.visit(new_pv))
_name = pv.name
_dir = ('I' if isinstance(pv, vast.Input) else
'O' if isinstance(pv, vast.Output) else 'IO')
_vec = '' if pv.width is None else asttocode.visit(pv.width)
mpd_ports.append((_name, _dir, _vec))
for pk, (pv, pwidth) in top_ioports.items():
new_pv = vast.Wire(pv.name, pv.width, pv.signed)
_name = pv.name
_dir = ('in' if isinstance(pv, vast.Input) else
'out' if isinstance(pv, vast.Output) else 'inout')
_vec = None if pv.width is None else pwidth - 1
_ids = None if pv.width is None else iv.getIdentifiers(
pv.width.msb)
_d = {}
if _ids is not None:
for i in _ids:
_d[i] = "(spirit:decode(id('MODELPARAM_VALUE." + i + "')))"
_msb = (None if _ids is None else asttocode.visit(
ir.replaceIdentifiers(pv.width.msb, _d)))
ext_ports.append((_name, _dir, _vec, _msb))
for pk, pv in top_parameters.items():
r = asttocode.visit(pv)
if r.count('localparam'):
def_top_localparams.append(r)
continue
_name = pv.name
_value = asttocode.visit(pv.value)
_dt = 'string' if r.count('"') else 'integer'
ext_params.append((_name, _value, _dt))
# write to files
# with AXI interface, create IPcore dir
ipcore_version = '_v1_00_a'
mpd_version = '_v2_1_0'
dirname = 'ipgen_' + userlogic_topmodule + ipcore_version + '/'
# pcore
mpdname = 'ipgen_' + userlogic_topmodule + mpd_version + '.mpd'
#muiname = 'ipgen_' + userlogic_topmodule + mpd_version + '.mui'
paoname = 'ipgen_' + userlogic_topmodule + mpd_version + '.pao'
tclname = 'ipgen_' + userlogic_topmodule + mpd_version + '.tcl'
# IP-XACT
xmlname = 'component.xml'
xdcname = 'ipgen_' + userlogic_topmodule + '.xdc'
bdname = 'bd.tcl'
xguiname = 'xgui.tcl'
# source
hdlname = 'ipgen_' + userlogic_topmodule + '.v'
testname = 'test_ipgen_' + userlogic_topmodule + '.v'
memname = 'mem.img'
makefilename = 'Makefile'
copied_memimg = memname if memimg is not None else None
binfile = (True if memimg is not None and memimg.endswith('.bin') else
False)
# pcore
mpdpath = dirname + 'data/'
#muipath = dirname + 'data/'
paopath = dirname + 'data/'
tclpath = dirname + 'data/'
# IP-XACT
xmlpath = dirname
xdcpath = dirname + 'data/'
bdpath = dirname + 'bd/'
xguipath = dirname + 'xgui/'
# source
hdlpath = dirname + 'hdl/'
verilogpath = dirname + 'hdl/verilog/'
testpath = dirname + 'test/'
makefilepath = dirname + 'test/'
if not os.path.exists(dirname):
os.mkdir(dirname)
if not os.path.exists(dirname + '/' + 'data'):
os.mkdir(dirname + '/' + 'data')
if not os.path.exists(dirname + '/' + 'doc'):
os.mkdir(dirname + '/' + 'doc')
if not os.path.exists(dirname + '/' + 'bd'):
os.mkdir(dirname + '/' + 'bd')
if not os.path.exists(dirname + '/' + 'xgui'):
os.mkdir(dirname + '/' + 'xgui')
if not os.path.exists(dirname + '/' + 'hdl'):
os.mkdir(dirname + '/' + 'hdl')
if not os.path.exists(dirname + '/' + 'hdl/verilog'):
os.mkdir(dirname + '/' + 'hdl/verilog')
if not os.path.exists(dirname + '/' + 'test'):
os.mkdir(dirname + '/' + 'test')
# mpd file
mpd_template_file = 'mpd.txt'
mpd_code = self.render(mpd_template_file,
userlogic_topmodule,
masterlist,
slavelist,
def_top_parameters,
def_top_localparams,
def_top_ioports,
name_top_ioports,
ext_addrwidth=configs['ext_addrwidth'],
ext_burstlength=ext_burstlength,
single_clock=configs['single_clock'],
hdlname=hdlname,
ipcore_version=ipcore_version,
mpd_ports=mpd_ports,
mpd_parameters=mpd_parameters)
f = open(mpdpath + mpdname, 'w')
f.write(mpd_code)
f.close()
# mui file
#mui_template_file = 'mui.txt'
#mui_code = self.render(mui_template_file, userlogic_topmodule,
# masterlist, slavelist,
# def_top_parameters, def_top_localparams, def_top_ioports, name_top_ioports,
# ext_addrwidth=configs['ext_addrwidth'], ext_burstlength=ext_burstlength,
# single_clock=configs['single_clock'],
# hdlname=hdlname,
# ipcore_version=ipcore_version,
# mpd_ports=mpd_ports, mpd_parameters=mpd_parameters)
#f = open(muipath+muiname, 'w')
#f.write(mui_code)
#f.close()
# pao file
pao_template_file = 'pao.txt'
pao_code = self.render(pao_template_file,
userlogic_topmodule,
masterlist,
slavelist,
def_top_parameters,
def_top_localparams,
def_top_ioports,
name_top_ioports,
ext_addrwidth=configs['ext_addrwidth'],
ext_burstlength=ext_burstlength,
single_clock=configs['single_clock'],
hdlname=hdlname,
ipcore_version=ipcore_version,
mpd_ports=mpd_ports,
mpd_parameters=mpd_parameters)
f = open(paopath + paoname, 'w')
f.write(pao_code)
f.close()
# tcl file
tcl_code = ''
if not configs['single_clock']:
tcl_code = open(TEMPLATE_DIR + 'pcore_tcl.tcl', 'r').read()
f = open(tclpath + tclname, 'w')
f.write(tcl_code)
f.close()
memorylist = []
for m in masterlist:
memorylist.append(
ipgen.utils.componentgen.AxiDefinition(m.name + '_AXI',
m.datawidth, True,
m.lite))
for s in slavelist:
memorylist.append(
ipgen.utils.componentgen.AxiDefinition(s.name + '_AXI',
s.datawidth, False,
s.lite))
# component.xml
gen = ipgen.utils.componentgen.ComponentGen()
xml_code = gen.generate('ipgen_' + userlogic_topmodule,
memorylist,
ext_addrwidth=configs['ext_addrwidth'],
ext_burstlength=ext_burstlength,
ext_ports=ext_ports,
ext_params=ext_params)
f = open(xmlpath + xmlname, 'w')
f.write(xml_code)
f.close()
# xdc
xdc_code = ''
if not configs['single_clock']:
xdc_code = open(TEMPLATE_DIR + 'ipxact.xdc', 'r').read()
f = open(xdcpath + xdcname, 'w')
f.write(xdc_code)
f.close()
# bd
bd_code = ''
bd_code = open(TEMPLATE_DIR + 'bd.tcl', 'r').read()
f = open(bdpath + bdname, 'w')
f.write(bd_code)
f.close()
# xgui file
xgui_template_file = 'xgui_tcl.txt'
xgui_code = self.render(xgui_template_file,
userlogic_topmodule,
masterlist,
slavelist,
def_top_parameters,
def_top_localparams,
def_top_ioports,
name_top_ioports,
ext_addrwidth=configs['ext_addrwidth'],
ext_burstlength=ext_burstlength,
single_clock=configs['single_clock'],
hdlname=hdlname,
ipcore_version=ipcore_version,
mpd_ports=mpd_ports,
mpd_parameters=mpd_parameters)
f = open(xguipath + xguiname, 'w')
f.write(xgui_code)
f.close()
# hdl file
f = open(verilogpath + hdlname, 'w')
f.write(code)
f.close()
# user test code
usertestcode = None
if usertest is not None:
usertestcode = open(usertest, 'r').read()
# test file
test_template_file = 'test_ipgen_axi.txt'
test_code = self.render(
test_template_file,
userlogic_topmodule,
masterlist,
slavelist,
def_top_parameters,
def_top_localparams,
def_top_ioports,
name_top_ioports,
ext_addrwidth=configs['ext_addrwidth'],
ext_burstlength=ext_burstlength,
single_clock=configs['single_clock'],
hdlname=hdlname,
memimg=copied_memimg,
binfile=binfile,
usertestcode=usertestcode,
simaddrwidth=configs['sim_addrwidth'],
clock_hperiod_userlogic=configs['hperiod_ulogic'],
clock_hperiod_bus=configs['hperiod_bus'],
ignore_protocol_error=ignore_protocol_error)
f = open(testpath + testname, 'w')
f.write(test_code)
f.write(open(TEMPLATE_DIR + 'axi_master_fifo.v', 'r').read())
f.close()
# memory image for test
if memimg is not None:
shutil.copyfile(os.path.expanduser(memimg), testpath + memname)
# makefile file
makefile_template_file = 'Makefile.txt'
makefile_code = self.render(makefile_template_file,
userlogic_topmodule,
masterlist,
slavelist,
def_top_parameters,
def_top_localparams,
def_top_ioports,
name_top_ioports,
ext_addrwidth=configs['ext_addrwidth'],
ext_burstlength=ext_burstlength,
single_clock=configs['single_clock'],
testname=testname)
f = open(makefilepath + makefilename, 'w')
f.write(makefile_code)
f.close()
def main():
INFO = "Verilog identifier renamer"
USAGE = "Usage: python3 amnesia.py file ..."
keeplist = ["clk", "reset", "inData", "outData"]
def showUsage():
print(INFO)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-I",
"--include",
dest="include",
action="append",
default=[],
help="Include path")
optparser.add_option("-D",
dest="define",
action="append",
default=[],
help="Macro Definition")
optparser.add_option("-x",
dest="exclude",
action="append",
default=keeplist,
help="Identifiers to exclude from obfuscation")
(options, args) = optparser.parse_args()
filelist = args
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showUsage()
ast, directives = parse(filelist,
preprocess_include=options.include,
preprocess_define=options.define)
#ast.show()
# getIdentifiers is a list of all identifiers, including repeats.
# ths i:i thing changes it on the fly into a dictionary,
# as a way of doing "sort | uniq," basically.
ids = {i: i for i in getIdentifiers(ast)}
# now build our from:to mapping for all of those identifiers.
for orig_id in ids:
if orig_id in options.exclude:
ids[orig_id] = orig_id
else:
ids[orig_id] = stringGarbage(32)
## PyVerilog comes with a function called "replaceIdentifiers" that should
## do this, but it doesn't get everything. Ours will chomp on anything
## what has a name.
AST_traverse_rename_identifiers(ast, ids)
codegen = ASTCodeGenerator()
rslt = codegen.visit(ast) ## AST back to Verilog
print(rslt)
def build_package_axi(
self,
configs,
synthesized_code,
common_code,
masterlist,
slavelist,
top_parameters,
top_ioports,
userlogic_topmodule,
memimg,
usertest,
ignore_protocol_error,
):
code = synthesized_code + common_code
# default values
ext_burstlength = 256
# write to files, with AXI interface
def_top_parameters = []
def_top_localparams = []
def_top_ioports = []
name_top_ioports = []
mpd_parameters = []
mpd_ports = []
ext_params = []
ext_ports = []
asttocode = ASTCodeGenerator()
for pk, pv in top_parameters.items():
r = asttocode.visit(pv)
def_top_parameters.append(r)
if r.count("localparam"):
def_top_localparams.append(r)
continue
_name = pv.name
_value = asttocode.visit(pv.value)
_dt = "string" if r.count('"') else "integer"
mpd_parameters.append((_name, _value, _dt))
for pk, (pv, pwidth) in top_ioports.items():
name_top_ioports.append(pk)
new_pv = vast.Wire(pv.name, pv.width, pv.signed)
def_top_ioports.append(asttocode.visit(new_pv))
_name = pv.name
_dir = "I" if isinstance(pv, vast.Input) else "O" if isinstance(pv, vast.Output) else "IO"
_vec = "" if pv.width is None else asttocode.visit(pv.width)
mpd_ports.append((_name, _dir, _vec))
for pk, (pv, pwidth) in top_ioports.items():
new_pv = vast.Wire(pv.name, pv.width, pv.signed)
_name = pv.name
_dir = "in" if isinstance(pv, vast.Input) else "out" if isinstance(pv, vast.Output) else "inout"
_vec = None if pv.width is None else pwidth - 1
_ids = None if pv.width is None else iv.getIdentifiers(pv.width.msb)
_d = {}
if _ids is not None:
for i in _ids:
_d[i] = "(spirit:decode(id('MODELPARAM_VALUE." + i + "')))"
_msb = None if _ids is None else asttocode.visit(ir.replaceIdentifiers(pv.width.msb, _d))
ext_ports.append((_name, _dir, _vec, _msb))
for pk, pv in top_parameters.items():
r = asttocode.visit(pv)
if r.count("localparam"):
def_top_localparams.append(r)
continue
_name = pv.name
_value = asttocode.visit(pv.value)
_dt = "string" if r.count('"') else "integer"
ext_params.append((_name, _value, _dt))
# write to files
# with AXI interface, create IPcore dir
ipcore_version = "_v1_00_a"
mpd_version = "_v2_1_0"
dirname = "ipgen_" + userlogic_topmodule + ipcore_version + "/"
# pcore
mpdname = "ipgen_" + userlogic_topmodule + mpd_version + ".mpd"
# muiname = 'ipgen_' + userlogic_topmodule + mpd_version + '.mui'
paoname = "ipgen_" + userlogic_topmodule + mpd_version + ".pao"
tclname = "ipgen_" + userlogic_topmodule + mpd_version + ".tcl"
# IP-XACT
xmlname = "component.xml"
xdcname = "ipgen_" + userlogic_topmodule + ".xdc"
bdname = "bd.tcl"
xguiname = "xgui.tcl"
# source
hdlname = "ipgen_" + userlogic_topmodule + ".v"
testname = "test_ipgen_" + userlogic_topmodule + ".v"
memname = "mem.img"
makefilename = "Makefile"
copied_memimg = memname if memimg is not None else None
binfile = True if memimg is not None and memimg.endswith(".bin") else False
# pcore
mpdpath = dirname + "data/"
# muipath = dirname + 'data/'
paopath = dirname + "data/"
tclpath = dirname + "data/"
# IP-XACT
xmlpath = dirname
xdcpath = dirname + "data/"
bdpath = dirname + "bd/"
xguipath = dirname + "xgui/"
# source
hdlpath = dirname + "hdl/"
verilogpath = dirname + "hdl/verilog/"
testpath = dirname + "test/"
makefilepath = dirname + "test/"
if not os.path.exists(dirname):
os.mkdir(dirname)
if not os.path.exists(dirname + "/" + "data"):
os.mkdir(dirname + "/" + "data")
if not os.path.exists(dirname + "/" + "doc"):
os.mkdir(dirname + "/" + "doc")
if not os.path.exists(dirname + "/" + "bd"):
os.mkdir(dirname + "/" + "bd")
if not os.path.exists(dirname + "/" + "xgui"):
os.mkdir(dirname + "/" + "xgui")
if not os.path.exists(dirname + "/" + "hdl"):
os.mkdir(dirname + "/" + "hdl")
if not os.path.exists(dirname + "/" + "hdl/verilog"):
os.mkdir(dirname + "/" + "hdl/verilog")
if not os.path.exists(dirname + "/" + "test"):
os.mkdir(dirname + "/" + "test")
# mpd file
mpd_template_file = "mpd.txt"
mpd_code = self.render(
mpd_template_file,
userlogic_topmodule,
masterlist,
slavelist,
def_top_parameters,
def_top_localparams,
def_top_ioports,
name_top_ioports,
ext_addrwidth=configs["ext_addrwidth"],
ext_burstlength=ext_burstlength,
single_clock=configs["single_clock"],
hdlname=hdlname,
ipcore_version=ipcore_version,
mpd_ports=mpd_ports,
mpd_parameters=mpd_parameters,
)
f = open(mpdpath + mpdname, "w")
f.write(mpd_code)
f.close()
# mui file
# mui_template_file = 'mui.txt'
# mui_code = self.render(mui_template_file, userlogic_topmodule,
# masterlist, slavelist,
# def_top_parameters, def_top_localparams, def_top_ioports, name_top_ioports,
# ext_addrwidth=configs['ext_addrwidth'], ext_burstlength=ext_burstlength,
# single_clock=configs['single_clock'],
# hdlname=hdlname,
# ipcore_version=ipcore_version,
# mpd_ports=mpd_ports, mpd_parameters=mpd_parameters)
# f = open(muipath+muiname, 'w')
# f.write(mui_code)
# f.close()
# pao file
pao_template_file = "pao.txt"
pao_code = self.render(
pao_template_file,
userlogic_topmodule,
masterlist,
slavelist,
def_top_parameters,
def_top_localparams,
def_top_ioports,
name_top_ioports,
ext_addrwidth=configs["ext_addrwidth"],
ext_burstlength=ext_burstlength,
single_clock=configs["single_clock"],
hdlname=hdlname,
ipcore_version=ipcore_version,
mpd_ports=mpd_ports,
mpd_parameters=mpd_parameters,
)
f = open(paopath + paoname, "w")
f.write(pao_code)
f.close()
# tcl file
tcl_code = ""
if not configs["single_clock"]:
tcl_code = open(TEMPLATE_DIR + "pcore_tcl.tcl", "r").read()
f = open(tclpath + tclname, "w")
f.write(tcl_code)
f.close()
memorylist = []
for m in masterlist:
memorylist.append(ipgen.utils.componentgen.AxiDefinition(m.name + "_AXI", m.datawidth, True, m.lite))
for s in slavelist:
memorylist.append(ipgen.utils.componentgen.AxiDefinition(s.name + "_AXI", s.datawidth, False, s.lite))
# component.xml
gen = ipgen.utils.componentgen.ComponentGen()
xml_code = gen.generate(
"ipgen_" + userlogic_topmodule,
memorylist,
ext_addrwidth=configs["ext_addrwidth"],
ext_burstlength=ext_burstlength,
ext_ports=ext_ports,
ext_params=ext_params,
)
f = open(xmlpath + xmlname, "w")
f.write(xml_code)
f.close()
# xdc
xdc_code = ""
if not configs["single_clock"]:
xdc_code = open(TEMPLATE_DIR + "ipxact.xdc", "r").read()
f = open(xdcpath + xdcname, "w")
f.write(xdc_code)
f.close()
# bd
bd_code = ""
bd_code = open(TEMPLATE_DIR + "bd.tcl", "r").read()
f = open(bdpath + bdname, "w")
f.write(bd_code)
f.close()
# xgui file
xgui_template_file = "xgui_tcl.txt"
xgui_code = self.render(
xgui_template_file,
userlogic_topmodule,
masterlist,
slavelist,
def_top_parameters,
def_top_localparams,
def_top_ioports,
name_top_ioports,
ext_addrwidth=configs["ext_addrwidth"],
ext_burstlength=ext_burstlength,
single_clock=configs["single_clock"],
hdlname=hdlname,
ipcore_version=ipcore_version,
mpd_ports=mpd_ports,
mpd_parameters=mpd_parameters,
)
f = open(xguipath + xguiname, "w")
f.write(xgui_code)
f.close()
# hdl file
f = open(verilogpath + hdlname, "w")
f.write(code)
f.close()
# user test code
usertestcode = None
if usertest is not None:
usertestcode = open(usertest, "r").read()
# test file
test_template_file = "test_ipgen_axi.txt"
test_code = self.render(
test_template_file,
userlogic_topmodule,
masterlist,
slavelist,
def_top_parameters,
def_top_localparams,
def_top_ioports,
name_top_ioports,
ext_addrwidth=configs["ext_addrwidth"],
ext_burstlength=ext_burstlength,
single_clock=configs["single_clock"],
hdlname=hdlname,
memimg=copied_memimg,
binfile=binfile,
usertestcode=usertestcode,
simaddrwidth=configs["sim_addrwidth"],
clock_hperiod_userlogic=configs["hperiod_ulogic"],
clock_hperiod_bus=configs["hperiod_bus"],
ignore_protocol_error=ignore_protocol_error,
)
f = open(testpath + testname, "w")
f.write(test_code)
f.write(open(TEMPLATE_DIR + "axi_master_fifo.v", "r").read())
f.close()
# memory image for test
if memimg is not None:
shutil.copyfile(os.path.expanduser(memimg), testpath + memname)
# makefile file
makefile_template_file = "Makefile.txt"
makefile_code = self.render(
makefile_template_file,
userlogic_topmodule,
masterlist,
slavelist,
def_top_parameters,
def_top_localparams,
def_top_ioports,
name_top_ioports,
ext_addrwidth=configs["ext_addrwidth"],
ext_burstlength=ext_burstlength,
single_clock=configs["single_clock"],
testname=testname,
)
f = open(makefilepath + makefilename, "w")
f.write(makefile_code)
f.close()
def build_package_axi(self, configs, synthesized_code, common_code,
threads,
top_parameters, top_ioports, userlogic_topmodule,
memimg, usertest):
code = synthesized_code + common_code
# default values
ext_burstlength = 256
# write to files, with AXI interface
def_top_parameters = []
def_top_localparams = []
def_top_ioports = []
name_top_ioports = []
mpd_parameters = []
mpd_ports = []
ext_params = []
ext_ports = []
asttocode = ASTCodeGenerator()
for pk, pv in top_parameters.items():
r = asttocode.visit(pv)
def_top_parameters.append( r )
if r.count('localparam'):
def_top_localparams.append( r )
continue
_name = pv.name
_value = asttocode.visit( pv.value )
_dt = 'string' if r.count('"') else 'integer'
mpd_parameters.append( (_name, _value, _dt) )
for pk, (pv, pwidth) in top_ioports.items():
name_top_ioports.append( pk )
new_pv = vast.Wire(pv.name, pv.width, pv.signed)
def_top_ioports.append( asttocode.visit(new_pv) )
_name = pv.name
_dir = ('I' if isinstance(pv, vast.Input) else
'O' if isinstance(pv, vast.Output) else
'IO')
_vec = '' if pv.width is None else asttocode.visit(pv.width)
mpd_ports.append( (_name, _dir, _vec) )
for pk, (pv, pwidth) in top_ioports.items():
new_pv = vast.Wire(pv.name, pv.width, pv.signed)
_name = pv.name
_dir = ('in' if isinstance(pv, vast.Input) else
'out' if isinstance(pv, vast.Output) else
'inout')
_vec = None if pv.width is None else pwidth - 1
_ids = None if pv.width is None else iv.getIdentifiers(pv.width.msb)
_d = {}
if _ids is not None:
for i in _ids:
_d[i] = "(spirit:decode(id('MODELPARAM_VALUE." + i + "')))"
_msb = (None if _ids is None else
asttocode.visit(ir.replaceIdentifiers(pv.width.msb, _d)))
ext_ports.append( (_name, _dir, _vec, _msb) )
for pk, pv in top_parameters.items():
r = asttocode.visit(pv)
if r.count('localparam'):
def_top_localparams.append( r )
continue
_name = pv.name
_value = asttocode.visit( pv.value )
_dt = 'string' if r.count('"') else 'integer'
ext_params.append( (_name, _value, _dt) )
# write to files
# with AXI interface, create IPcore dir
ipcore_version = '_v1_00_a'
mpd_version = '_v2_1_0'
dirname = 'pycoram_' + userlogic_topmodule + ipcore_version + '/'
# pcore
mpdname = 'pycoram_' + userlogic_topmodule + mpd_version + '.mpd'
#muiname = 'pycoram_' + userlogic_topmodule + mpd_version + '.mui'
paoname = 'pycoram_' + userlogic_topmodule + mpd_version + '.pao'
tclname = 'pycoram_' + userlogic_topmodule + mpd_version + '.tcl'
# IP-XACT
xmlname = 'component.xml'
xdcname = 'pycoram_' + userlogic_topmodule + '.xdc'
bdname = 'bd.tcl'
xguiname = 'xgui.tcl'
# source
hdlname = 'pycoram_' + userlogic_topmodule + '.v'
testname = 'test_pycoram_' + userlogic_topmodule + '.v'
memname = 'mem.img'
makefilename = 'Makefile'
copied_memimg = memname if memimg is not None else None
binfile = (True if memimg is not None and memimg.endswith('.bin') else False)
# pcore
mpdpath = dirname + 'data/'
#muipath = dirname + 'data/'
paopath = dirname + 'data/'
tclpath = dirname + 'data/'
# IP-XACT
xmlpath = dirname
xdcpath = dirname + 'data/'
bdpath = dirname + 'bd/'
xguipath = dirname + 'xgui/'
# source
hdlpath = dirname + 'hdl/'
verilogpath = dirname + 'hdl/verilog/'
testpath = dirname + 'test/'
makefilepath = dirname + 'test/'
if not os.path.exists(dirname):
os.mkdir(dirname)
if not os.path.exists(dirname + '/' + 'data'):
os.mkdir(dirname + '/' + 'data')
if not os.path.exists(dirname + '/' + 'doc'):
os.mkdir(dirname + '/' + 'doc')
if not os.path.exists(dirname + '/' + 'bd'):
os.mkdir(dirname + '/' + 'bd')
if not os.path.exists(dirname + '/' + 'xgui'):
os.mkdir(dirname + '/' + 'xgui')
if not os.path.exists(dirname + '/' + 'hdl'):
os.mkdir(dirname + '/' + 'hdl')
if not os.path.exists(dirname + '/' + 'hdl/verilog'):
os.mkdir(dirname + '/' + 'hdl/verilog')
if not os.path.exists(dirname + '/' + 'test'):
os.mkdir(dirname + '/' + 'test')
# mpd file
mpd_template_file = 'mpd.txt'
mpd_code = self.render(mpd_template_file,
userlogic_topmodule, threads,
def_top_parameters, def_top_localparams, def_top_ioports, name_top_ioports,
ext_addrwidth=configs['ext_addrwidth'], ext_burstlength=ext_burstlength,
single_clock=configs['single_clock'], lite=configs['io_lite'],
hdlname=hdlname,
ipcore_version=ipcore_version,
mpd_ports=mpd_ports, mpd_parameters=mpd_parameters)
f = open(mpdpath+mpdname, 'w')
f.write(mpd_code)
f.close()
# mui file
#mui_template_file = 'mui.txt'
#mui_code = self.render(mui_template_file,
# userlogic_topmodule, threads,
# def_top_parameters, def_top_localparams, def_top_ioports, name_top_ioports,
# ext_addrwidth=configs['ext_addrwidth'], ext_burstlength=ext_burstlength,
# single_clock=configs['single_clock'], lite=configs['io_lite'],
# hdlname=hdlname,
# ipcore_version=ipcore_version,
# mpd_ports=mpd_ports, mpd_parameters=mpd_parameters)
#f = open(muipath+muiname, 'w')
#f.write(mui_code)
#f.close()
# pao file
pao_template_file = 'pao.txt'
pao_code = self.render(pao_template_file,
userlogic_topmodule, threads,
def_top_parameters, def_top_localparams, def_top_ioports, name_top_ioports,
ext_addrwidth=configs['ext_addrwidth'], ext_burstlength=ext_burstlength,
single_clock=configs['single_clock'], lite=configs['io_lite'],
hdlname=hdlname,
ipcore_version=ipcore_version,
mpd_ports=mpd_ports, mpd_parameters=mpd_parameters)
f = open(paopath+paoname, 'w')
f.write(pao_code)
f.close()
# tcl file
tcl_code = ''
if not configs['single_clock']:
tcl_code = open(TEMPLATE_DIR+'pcore_tcl.tcl', 'r').read()
f = open(tclpath+tclname, 'w')
f.write(tcl_code)
f.close()
# component.xml
gen = pycoram.utils.componentgen.ComponentGen()
xml_code = gen.generate(userlogic_topmodule, threads,
lite=configs['io_lite'],
ext_addrwidth=configs['ext_addrwidth'],
ext_burstlength=ext_burstlength,
ext_ports=ext_ports,
ext_params=ext_params)
f = open(xmlpath+xmlname, 'w')
f.write(xml_code)
f.close()
# xdc
xdc_code = ''
if not configs['single_clock']:
xdc_code = open(TEMPLATE_DIR+'ipxact.xdc', 'r').read()
f = open(xdcpath+xdcname, 'w')
f.write(xdc_code)
f.close()
# bd
bd_code = ''
bd_code = open(TEMPLATE_DIR+'bd.tcl', 'r').read()
f = open(bdpath+bdname, 'w')
f.write(bd_code)
f.close()
# xgui file
xgui_template_file = 'xgui_tcl.txt'
xgui_code = self.render(xgui_template_file,
userlogic_topmodule, threads,
def_top_parameters, def_top_localparams, def_top_ioports, name_top_ioports,
ext_addrwidth=configs['ext_addrwidth'], ext_burstlength=ext_burstlength,
single_clock=configs['single_clock'], lite=configs['io_lite'],
hdlname=hdlname,
ipcore_version=ipcore_version,
mpd_ports=mpd_ports, mpd_parameters=mpd_parameters)
f = open(xguipath+xguiname, 'w')
f.write(xgui_code)
f.close()
# hdl file
f = open(verilogpath+hdlname, 'w')
f.write(code)
f.close()
# user test code
usertestcode = None
if usertest is not None:
usertestcode = open(usertest, 'r').read()
# test file
test_template_file = 'test_coram_axi.txt'
test_code = self.render(test_template_file,
userlogic_topmodule, threads,
def_top_parameters, def_top_localparams, def_top_ioports, name_top_ioports,
ext_addrwidth=configs['ext_addrwidth'], ext_burstlength=ext_burstlength,
single_clock=configs['single_clock'], lite=configs['io_lite'],
hdlname=hdlname,
memimg=copied_memimg, binfile=binfile,
usertestcode=usertestcode,
simaddrwidth=configs['sim_addrwidth'],
clock_hperiod_userlogic=configs['hperiod_ulogic'],
clock_hperiod_controlthread=configs['hperiod_cthread'],
clock_hperiod_bus=configs['hperiod_bus'])
f = open(testpath+testname, 'w')
f.write(test_code)
f.write( open(TEMPLATE_DIR+'axi_master_fifo.v', 'r').read() )
f.close()
# memory image for test
if memimg is not None:
shutil.copyfile(os.path.expanduser(memimg), testpath+memname)
# makefile file
makefile_template_file = 'Makefile.txt'
makefile_code = self.render(makefile_template_file,
userlogic_topmodule, threads,
def_top_parameters, def_top_localparams, def_top_ioports, name_top_ioports,
ext_addrwidth=configs['ext_addrwidth'], ext_burstlength=ext_burstlength,
single_clock=configs['single_clock'], lite=configs['io_lite'],
testname=testname)
f = open(makefilepath+makefilename, 'w')
f.write(makefile_code)
f.close()
