def __init__(
self,
qubits,
clbits,
nodes,
scale,
style=None,
reverse_bits=False,
plot_barriers=True,
layout=None,
initial_state=False,
cregbundle=False,
global_phase=None,
qregs=None,
cregs=None,
):
"""QCircuitImage initializer.
Args:
qubits (list[Qubit]): list of qubits
clbits (list[Clbit]): list of clbits
nodes (list[list[DAGNode]]): list of circuit instructions, grouped by layer
scale (float): image scaling
style (dict or str): dictionary of style or file name of style file
reverse_bits (bool): when True, reverse the bit ordering of the registers
plot_barriers (bool): Enable/disable drawing barriers in the output
circuit. Defaults to True.
layout (Layout or None): If present, the layout information will be
included.
initial_state (bool): Optional. Adds |0> in the beginning of the line. Default: `False`.
cregbundle (bool): Optional. If set True bundle classical registers. Default: `False`.
global_phase (float): Optional, the global phase for the circuit.
qregs (list): List qregs present in the circuit.
cregs (list): List of cregs present in the circuit.
Raises:
ImportError: If pylatexenc is not installed
"""
# list of lists corresponding to layers of the circuit
self.nodes = nodes
# image scaling
self.scale = 1.0 if scale is None else scale
# Map of qregs to sizes
self.qregs = {}
# Map of cregs to sizes
self.cregs = {}
# List of qubits and cbits in order of appearance in code and image
# May also include ClassicalRegisters if cregbundle=True
self.ordered_bits = []
# Map from registers to the list they appear in the image
self.img_regs = {}
# Array to hold the \\LaTeX commands to generate a circuit image.
self._latex = []
# Variable to hold image depth (width)
self.img_depth = 0
# Variable to hold image width (height)
self.img_width = 0
# Variable to hold total circuit depth
self.sum_column_widths = 0
# Variable to hold total circuit width
self.sum_wire_heights = 0
# em points of separation between circuit columns
self.column_separation = 1
# em points of separation between circuit wire
self.wire_separation = 0
# presence of "box" or "target" determines wire spacing
self.has_box = False
self.has_target = False
self.layout = layout
self.initial_state = initial_state
self.reverse_bits = reverse_bits
self.plot_barriers = plot_barriers
#################################
self.qubit_list = qubits
self.ordered_bits = qubits + clbits
self.cregs = {reg: reg.size for reg in cregs}
self.bit_locations = {
bit: {
"register": register,
"index": index
}
for register in cregs + qregs for index, bit in enumerate(register)
}
for index, bit in list(enumerate(qubits)) + list(enumerate(clbits)):
if bit not in self.bit_locations:
self.bit_locations[bit] = {"register": None, "index": index}
self.cregbundle = cregbundle
# If there is any custom instruction that uses clasiscal bits
# then cregbundle is forced to be False.
for layer in self.nodes:
for node in layer:
if node.op.name not in {"measure"} and node.cargs:
self.cregbundle = False
self.cregs_bits = [
self.bit_locations[bit]["register"] for bit in clbits
]
self.img_regs = {bit: ind for ind, bit in enumerate(self.ordered_bits)}
if self.cregbundle:
self.img_width = len(qubits) + len(self.cregs)
else:
self.img_width = len(self.img_regs)
self.global_phase = global_phase
self._style, _ = load_style(style)
def __init__(
self,
qubits,
clbits,
nodes,
scale,
style=None,
reverse_bits=False,
plot_barriers=True,
layout=None,
initial_state=False,
cregbundle=False,
global_phase=None,
qregs=None,
cregs=None,
with_layout=False,
circuit=None,
):
"""QCircuitImage initializer.
Args:
qubits (list[Qubit]): list of qubits
clbits (list[Clbit]): list of clbits
nodes (list[list[DAGNode]]): list of circuit instructions, grouped by layer
scale (float): image scaling
style (dict or str): dictionary of style or file name of style file
reverse_bits (bool): when True, reverse the bit ordering of the registers
plot_barriers (bool): Enable/disable drawing barriers in the output
circuit. Defaults to True.
layout (Layout or None): If present, the layout information will be
included.
initial_state (bool): Optional. Adds |0> in the beginning of the line. Default: `False`.
cregbundle (bool): Optional. If set True bundle classical registers. Default: `False`.
global_phase (float): Optional, the global phase for the circuit.
circuit (QuantumCircuit): the circuit that's being displayed
Raises:
ImportError: If pylatexenc is not installed
"""
if qregs is not None:
warn(
"The 'qregs' kwarg to the QCircuitImage class is deprecated "
"as of 0.20.0 and will be removed no earlier than 3 months "
"after the release date.",
DeprecationWarning,
2,
)
if cregs is not None:
warn(
"The 'cregs' kwarg to the QCircuitImage class is deprecated "
"as of 0.20.0 and will be removed no earlier than 3 months "
"after the release date.",
DeprecationWarning,
2,
)
if layout is not None:
warn(
"The 'layout' kwarg to the QCircuitImage class is deprecated "
"as of 0.20.0 and will be removed no earlier than 3 months "
"after the release date.",
DeprecationWarning,
2,
)
if global_phase is not None:
warn(
"The 'global_phase' kwarg to the QCircuitImage class is deprecated "
"as of 0.20.0 and will be removed no earlier than 3 months "
"after the release date.",
DeprecationWarning,
2,
)
# This check should be removed when the 4 deprecations above are removed
if circuit is None:
warn(
"The 'circuit' kwarg to the QCircuitImage class must be a valid "
"QuantumCircuit and not None. A new circuit is being created using "
"the qubits and clbits for rendering the drawing.",
DeprecationWarning,
2,
)
circ = QuantumCircuit(qubits, clbits)
for reg in qregs:
bits = [qubits[circ._qubit_indices[q].index] for q in reg]
circ.add_register(QuantumRegister(None, reg.name, list(bits)))
for reg in cregs:
bits = [clbits[circ._clbit_indices[q].index] for q in reg]
circ.add_register(ClassicalRegister(None, reg.name,
list(bits)))
self._circuit = circ
else:
self._circuit = circuit
self._qubits = qubits
self._clbits = clbits
# list of lists corresponding to layers of the circuit
self._nodes = nodes
# image scaling
self._scale = 1.0 if scale is None else scale
# Map of cregs to sizes
self._cregs = {}
# Array to hold the \\LaTeX commands to generate a circuit image.
self._latex = []
# Variable to hold image depth (width)
self._img_depth = 0
# Variable to hold image width (height)
self._img_width = 0
# Variable to hold total circuit depth
self._sum_column_widths = 0
# Variable to hold total circuit width
self._sum_wire_heights = 0
# em points of separation between circuit columns
self._column_separation = 1
# em points of separation between circuit wire
self._wire_separation = 0
# presence of "box" or "target" determines wire spacing
self._has_box = False
self._has_target = False
self._plot_barriers = plot_barriers
self._reverse_bits = reverse_bits
if with_layout:
self._layout = self._circuit._layout
else:
self._layout = None
self._initial_state = initial_state
self._cregbundle = cregbundle
self._global_phase = circuit.global_phase
# If there is any custom instruction that uses classical bits
# then cregbundle is forced to be False.
for layer in self._nodes:
for node in layer:
if node.op.name not in {"measure"} and node.cargs:
self._cregbundle = False
self._wire_map = get_wire_map(circuit, qubits + clbits,
self._cregbundle)
self._img_width = len(self._wire_map)
self._style, _ = load_style(style)
