def test_fir_impulse(self):
in_sign = Signature("in", True, bits=9)
out_sign = Signature("out", True, bits=9)
s = FirSim(in_sign=in_sign, out_sign=out_sign)
#s.design(48e3, 6e3, 1e3, 40.0)
taps = (4 << COEFF_SHIFT, 3 << COEFF_SHIFT, 2 << COEFF_SHIFT,
1 << COEFF_SHIFT)
coeff_ram = Ram(s.clearn,
s.clock,
s.clock,
data=taps,
width=18,
depth=512)
delay_line_i_ram = Ram(s.clearn, s.clock, s.clock, width=9, depth=512)
delay_line_q_ram = Ram(s.clearn, s.clock, s.clock, width=9, depth=512)
enable = Signal(bool(1))
bank1 = Signal(bool(0))
bank0 = Signal(bool(0))
N = Signal(intbv(4, min=0, max=2**7 - 1))
coeff_ram_inst = coeff_ram.instance_type()(
**coeff_ram.instance_signals())
delay_line_i_ram_inst = delay_line_i_ram.instance_type()(
**delay_line_i_ram.instance_signals())
delay_line_q_ram_inst = delay_line_q_ram.instance_type()(
**delay_line_q_ram.instance_signals())
def test_fir_impulse():
load_coeff_ram_addr = coeff_ram.port['b'].addr
load_coeff_ram_blk = coeff_ram.port['b'].blk
load_coeff_ram_wen = coeff_ram.port['b'].wen
fir_0 = fir(s.clearn,
s.clock,
s.input,
s.output,
coeff_ram.port['a'].addr,
coeff_ram.port['a'].din,
coeff_ram.port['a'].blk,
coeff_ram.port['a'].wen,
coeff_ram.port['a'].dout,
delay_line_i_ram.port['a'].addr,
delay_line_i_ram.port['a'].din,
delay_line_i_ram.port['a'].blk,
delay_line_i_ram.port['a'].wen,
delay_line_i_ram.port['a'].dout,
delay_line_q_ram.port['a'].addr,
delay_line_q_ram.port['a'].din,
delay_line_q_ram.port['a'].blk,
delay_line_q_ram.port['a'].wen,
delay_line_q_ram.port['a'].dout,
enable,
bank1,
bank0,
N,
sim=s)
return fir_0, coeff_ram_inst, delay_line_i_ram_inst, delay_line_q_ram_inst
in_t = arange(0, 8)
in_c = 0 * in_t + 1j * 0 * in_t
in_i = 0 * in_t
in_q = 0 * in_t
in_i[0] = 1 << 5
in_i[4] = 1 << 5
out_i, out_q = s.simulate(in_i, in_q, test_fir_impulse, 128, coeff_ram,
taps)
out_t = arange(0, out_i.shape[0])
new_shape = tuple([in_t.shape[i] for i in range(len(in_t.shape))])
assert out_t.shape == new_shape
print 'out_i', out_i
assert array_equal(out_i, [4, 3, 2, 1, 4, 3, 2, 1])
def whitebox(
resetn,
pclk,
paddr,
psel,
penable,
pwrite,
pwdata,
pready,
prdata,
#pslverr,
clearn,
clear_enable,
dac_clock,
dac2x_clock,
dac_en,
dac_data,
adc_idata,
adc_qdata,
tx_status_led,
tx_dmaready,
rx_status_led,
rx_dmaready,
tx_fifo_re,
tx_fifo_rdata,
tx_fifo_we,
tx_fifo_wdata,
tx_fifo_full,
tx_fifo_afull,
tx_fifo_empty,
tx_fifo_aempty,
tx_fifo_afval,
tx_fifo_aeval,
tx_fifo_wack,
tx_fifo_dvld,
tx_fifo_overflow,
tx_fifo_underflow,
tx_fifo_rdcnt,
tx_fifo_wrcnt,
rx_fifo_re,
rx_fifo_rdata,
rx_fifo_we,
rx_fifo_wdata,
rx_fifo_full,
rx_fifo_afull,
rx_fifo_empty,
rx_fifo_aempty,
rx_fifo_afval,
rx_fifo_aeval,
rx_fifo_wack,
rx_fifo_dvld,
rx_fifo_overflow,
rx_fifo_underflow,
rx_fifo_rdcnt,
rx_fifo_wrcnt,
**kwargs):
"""The whitebox.
:param resetn: Reset the whole radio front end.
:param clearn: Clear the DSP Chain
:param dac_clock: Clock running at DAC rate
:param dac2x_clock: Clock running at double DAC rate
:param pclk: The system bus clock
:param paddr: The bus assdress
:param psel: The bus slave select
:param penable: The bus slave enable line
:param pwrite: The bus read/write flag
:param pwdata: The bus write data
:param pready: The bus slave ready signal
:param prdata: The bus read data
:param pslverr: The bus slave error flag
:param dac_clock: The DAC clock
:param dac_data: The DAC data
:param dac_en: Enable DAC output
:param status_led: Output pin for whitebox status
:param dmaready: Ready signal to DMA controller
:param txirq: Almost empty interrupt to CPU
:param clear_enable: To reset controller, set this high for reset
"""
dspsim = kwargs.get('dspsim', None)
interp_default = kwargs.get('interp', 1)
fcw_bitwidth = kwargs.get('fcw_bitwidth', 25)
######### VARS AND FLAGS ###########
print 'interp=', interp_default
interp = Signal(intbv(interp_default)[11:])
shift = Signal(intbv(0, min=0, max=21))
firen = Signal(bool(0))
fir_bank1 = Signal(bool(0))
fir_bank0 = Signal(bool(0))
fir_N = Signal(intbv(0, min=0, max=2**7))
tx_correct_i = Signal(intbv(0, min=-2**9, max=2**9))
tx_correct_q = Signal(intbv(0, min=-2**9, max=2**9))
tx_gain_i = Signal(intbv(int(1.0 * 2**9 + .5))[10:])
tx_gain_q = Signal(intbv(int(1.0 * 2**9 + .5))[10:])
fcw = Signal(intbv(1)[fcw_bitwidth:])
txen = Signal(bool(0))
txstop = Signal(bool(0))
txfilteren = Signal(bool(0))
ddsen = Signal(bool(False))
loopen = Signal(bool(False))
decim = Signal(intbv(interp_default)[11:])
rx_correct_i = Signal(intbv(0, min=-2**9, max=2**9))
rx_correct_q = Signal(intbv(0, min=-2**9, max=2**9))
rxen = Signal(bool(0))
rxstop = Signal(bool(0))
rxfilteren = Signal(bool(0))
# The RAMs
fir_coeff_ram = Ram(clearn, dac_clock, bus.pclk, width=18, depth=512)
fir_delay_line_i_ram = Ram(clearn,
dac_clock,
dac_clock,
width=9,
depth=512)
fir_delay_line_q_ram = Ram(clearn,
dac_clock,
dac_clock,
width=9,
depth=512)
fir_coeff_ram_addr = fir_coeff_ram.port['a'].addr
fir_coeff_ram_din = fir_coeff_ram.port['a'].din
fir_coeff_ram_blk = fir_coeff_ram.port['a'].blk
fir_coeff_ram_wen = fir_coeff_ram.port['a'].wen
fir_coeff_ram_dout = fir_coeff_ram.port['a'].dout
fir_load_coeff_ram_addr = fir_coeff_ram.port['b'].addr
fir_load_coeff_ram_din = fir_coeff_ram.port['b'].din
fir_load_coeff_ram_blk = fir_coeff_ram.port['b'].blk
fir_load_coeff_ram_wen = fir_coeff_ram.port['b'].wen
fir_load_coeff_ram_dout = fir_coeff_ram.port['b'].dout
fir_delay_line_i_ram_addr = fir_delay_line_i_ram.port['a'].addr
fir_delay_line_i_ram_din = fir_delay_line_i_ram.port['a'].din
fir_delay_line_i_ram_blk = fir_delay_line_i_ram.port['a'].blk
fir_delay_line_i_ram_wen = fir_delay_line_i_ram.port['a'].wen
fir_delay_line_i_ram_dout = fir_delay_line_i_ram.port['a'].dout
fir_delay_line_q_ram_addr = fir_delay_line_q_ram.port['a'].addr
fir_delay_line_q_ram_din = fir_delay_line_q_ram.port['a'].din
fir_delay_line_q_ram_blk = fir_delay_line_q_ram.port['a'].blk
fir_delay_line_q_ram_wen = fir_delay_line_q_ram.port['a'].wen
fir_delay_line_q_ram_dout = fir_delay_line_q_ram.port['a'].dout
########### DIGITAL SIGNAL PROCESSING #######
loopback = Signature("loopback", False, bits=10)
duc_underrun = Signal(modbv(0, min=0, max=2**16))
dac_last = Signal(bool(0))
ddc_overrun = Signal(modbv(0, min=0, max=2**16))
ddc_flags = Signal(intbv(0)[4:])
adc_last = Signal(bool(0))
tx_sample = Signature("tx_sample", True, bits=16)
tx_sample_valid = tx_sample.valid
tx_sample_last = tx_sample.last
tx_sample_i = tx_sample.i
tx_sample_q = tx_sample.q
rx_sample = Signature("rx_sample", True, bits=16)
rx_sample_valid = rx_sample.valid
rx_sample_last = rx_sample.last
rx_sample_i = rx_sample.i
rx_sample_q = rx_sample.q
duc_args = (
clearn,
dac_clock,
dac2x_clock,
loopen,
loopback,
tx_fifo_empty,
tx_fifo_re,
tx_fifo_dvld,
tx_fifo_rdata,
tx_fifo_underflow,
txen,
txstop,
ddsen,
txfilteren,
interp,
shift,
fcw,
tx_correct_i,
tx_correct_q,
tx_gain_i,
tx_gain_q,
duc_underrun,
tx_sample,
dac_en,
dac_data,
dac_last,
rx_fifo_full,
rx_fifo_we,
rx_fifo_wdata,
rxen,
rxstop,
rxfilteren,
decim,
rx_correct_i,
rx_correct_q,
ddc_overrun,
rx_sample,
adc_idata,
adc_qdata,
adc_last,
fir_coeff_ram_addr,
fir_coeff_ram_din,
fir_coeff_ram_blk,
fir_coeff_ram_wen,
fir_coeff_ram_dout,
fir_delay_line_i_ram_addr,
fir_delay_line_i_ram_din,
fir_delay_line_i_ram_blk,
fir_delay_line_i_ram_wen,
fir_delay_line_i_ram_dout,
fir_delay_line_q_ram_addr,
fir_delay_line_q_ram_din,
fir_delay_line_q_ram_blk,
fir_delay_line_q_ram_wen,
fir_delay_line_q_ram_dout,
firen,
fir_bank1,
fir_bank0,
fir_N,
)
duc_kwargs = dict(dspsim=dspsim,
interp=interp_default,
cic_enable=kwargs.get('cic_enable', True),
cic_order=kwargs.get('cic_order', 4),
cic_delay=kwargs.get('cic_delay', 1),
fir_enable=kwargs.get('fir_enable', True),
dds_enable=kwargs.get('dds_enable', True),
conditioning_enable=kwargs.get('conditioning_enable',
True))
if kwargs.get("duc_enable", True):
duc = DUC(*duc_args, **duc_kwargs)
else:
duc = None
########### RADIO FRONT END ##############
rfe_args = (
resetn,
pclk,
paddr,
psel,
penable,
pwrite,
pwdata,
pready,
prdata, #pslverr,
clearn,
clear_enable,
loopen,
tx_status_led,
tx_dmaready,
rx_status_led,
rx_dmaready,
tx_fifo_we,
tx_fifo_wdata,
tx_fifo_empty,
tx_fifo_full,
tx_fifo_afval,
tx_fifo_aeval,
tx_fifo_afull,
tx_fifo_aempty,
tx_fifo_wack,
tx_fifo_dvld,
tx_fifo_overflow,
tx_fifo_underflow,
tx_fifo_rdcnt,
tx_fifo_wrcnt,
rx_fifo_re,
rx_fifo_rdata,
rx_fifo_empty,
rx_fifo_full,
rx_fifo_afval,
rx_fifo_aeval,
rx_fifo_afull,
rx_fifo_aempty,
rx_fifo_wack,
rx_fifo_dvld,
rx_fifo_overflow,
rx_fifo_underflow,
rx_fifo_rdcnt,
rx_fifo_wrcnt,
fir_load_coeff_ram_addr,
fir_load_coeff_ram_din,
fir_load_coeff_ram_blk,
fir_load_coeff_ram_wen,
fir_load_coeff_ram_dout,
firen,
fir_bank1,
fir_bank0,
fir_N,
interp,
shift,
fcw,
tx_correct_i,
tx_correct_q,
tx_gain_i,
tx_gain_q,
txen,
txstop,
ddsen,
txfilteren,
decim,
rx_correct_i,
rx_correct_q,
rxen,
rxstop,
rxfilteren,
duc_underrun,
dac_last,
ddc_overrun,
adc_last)
rfe = RFE(*rfe_args)
instances = (rfe, duc)
if kwargs.get('fir_enable', True):
fir_coeff_ram_inst = fir_coeff_ram.instance_type()(
**fir_coeff_ram.instance_signals())
fir_delay_line_i_ram_inst = fir_delay_line_i_ram.instance_type()(
**fir_delay_line_i_ram.instance_signals())
fir_delay_line_q_ram_inst = fir_delay_line_q_ram.instance_type()(
**fir_delay_line_q_ram.instance_signals())
instances += (fir_coeff_ram_inst, fir_delay_line_i_ram_inst,
fir_delay_line_q_ram_inst)
return instances
def test_fir_impulse(self):
in_sign = Signature("in", True, bits=9)
out_sign = Signature("out", True, bits=9)
s = FirSim(in_sign=in_sign, out_sign=out_sign)
#s.design(48e3, 6e3, 1e3, 40.0)
taps = (4 << COEFF_SHIFT, 3 << COEFF_SHIFT, 2 << COEFF_SHIFT, 1 << COEFF_SHIFT)
coeff_ram = Ram(s.clearn, s.clock, s.clock, data=taps,
width=18, depth=512)
delay_line_i_ram = Ram(s.clearn, s.clock, s.clock, width=9, depth=512)
delay_line_q_ram = Ram(s.clearn, s.clock, s.clock, width=9, depth=512)
enable = Signal(bool(1))
bank1 = Signal(bool(0))
bank0 = Signal(bool(0))
N = Signal(intbv(4, min=0, max=2**7-1))
coeff_ram_inst = coeff_ram.instance_type()(**coeff_ram.instance_signals())
delay_line_i_ram_inst = delay_line_i_ram.instance_type()(**delay_line_i_ram.instance_signals())
delay_line_q_ram_inst = delay_line_q_ram.instance_type()(**delay_line_q_ram.instance_signals())
def test_fir_impulse():
load_coeff_ram_addr = coeff_ram.port['b'].addr
load_coeff_ram_blk = coeff_ram.port['b'].blk
load_coeff_ram_wen = coeff_ram.port['b'].wen
fir_0 = fir(s.clearn, s.clock, s.input, s.output,
coeff_ram.port['a'].addr,
coeff_ram.port['a'].din,
coeff_ram.port['a'].blk,
coeff_ram.port['a'].wen,
coeff_ram.port['a'].dout,
delay_line_i_ram.port['a'].addr,
delay_line_i_ram.port['a'].din,
delay_line_i_ram.port['a'].blk,
delay_line_i_ram.port['a'].wen,
delay_line_i_ram.port['a'].dout,
delay_line_q_ram.port['a'].addr,
delay_line_q_ram.port['a'].din,
delay_line_q_ram.port['a'].blk,
delay_line_q_ram.port['a'].wen,
delay_line_q_ram.port['a'].dout,
enable, bank1, bank0, N,
sim=s)
return fir_0, coeff_ram_inst, delay_line_i_ram_inst, delay_line_q_ram_inst
in_t = arange(0, 8)
in_c = 0*in_t + 1j * 0*in_t
in_i = 0*in_t
in_q = 0*in_t
in_i[0] = 1 << 5
in_i[4] = 1 << 5
out_i, out_q = s.simulate(in_i, in_q, test_fir_impulse, 128,
coeff_ram, taps)
out_t = arange(0, out_i.shape[0])
new_shape = tuple([in_t.shape[i] for i in range(len(in_t.shape))])
assert out_t.shape == new_shape
print 'out_i', out_i
assert array_equal(out_i, [4, 3, 2, 1, 4, 3, 2, 1])
def whitebox(
resetn,
pclk,
paddr,
psel,
penable,
pwrite,
pwdata,
pready,
prdata,
#pslverr,
clearn,
clear_enable,
dac_clock,
dac2x_clock,
dac_en,
dac_data,
adc_idata,
adc_qdata,
tx_status_led,
tx_dmaready,
rx_status_led,
rx_dmaready,
tx_fifo_re,
tx_fifo_rdata,
tx_fifo_we,
tx_fifo_wdata,
tx_fifo_full,
tx_fifo_afull,
tx_fifo_empty,
tx_fifo_aempty,
tx_fifo_afval,
tx_fifo_aeval,
tx_fifo_wack,
tx_fifo_dvld,
tx_fifo_overflow,
tx_fifo_underflow,
tx_fifo_rdcnt,
tx_fifo_wrcnt,
rx_fifo_re,
rx_fifo_rdata,
rx_fifo_we,
rx_fifo_wdata,
rx_fifo_full,
rx_fifo_afull,
rx_fifo_empty,
rx_fifo_aempty,
rx_fifo_afval,
rx_fifo_aeval,
rx_fifo_wack,
rx_fifo_dvld,
rx_fifo_overflow,
rx_fifo_underflow,
rx_fifo_rdcnt,
rx_fifo_wrcnt,
**kwargs):
"""The whitebox.
:param resetn: Reset the whole radio front end.
:param clearn: Clear the DSP Chain
:param dac_clock: Clock running at DAC rate
:param dac2x_clock: Clock running at double DAC rate
:param pclk: The system bus clock
:param paddr: The bus assdress
:param psel: The bus slave select
:param penable: The bus slave enable line
:param pwrite: The bus read/write flag
:param pwdata: The bus write data
:param pready: The bus slave ready signal
:param prdata: The bus read data
:param pslverr: The bus slave error flag
:param dac_clock: The DAC clock
:param dac_data: The DAC data
:param dac_en: Enable DAC output
:param status_led: Output pin for whitebox status
:param dmaready: Ready signal to DMA controller
:param txirq: Almost empty interrupt to CPU
:param clear_enable: To reset controller, set this high for reset
"""
dspsim = kwargs.get('dspsim', None)
interp_default = kwargs.get('interp', 1)
fcw_bitwidth = kwargs.get('fcw_bitwidth', 25)
######### VARS AND FLAGS ###########
print 'interp=', interp_default
interp = Signal(intbv(interp_default)[11:])
shift = Signal(intbv(0, min=0, max=21))
firen = Signal(bool(0))
fir_bank1 = Signal(bool(0))
fir_bank0 = Signal(bool(0))
fir_N = Signal(intbv(0, min=0, max=2**7))
tx_correct_i = Signal(intbv(0, min=-2**9, max=2**9))
tx_correct_q = Signal(intbv(0, min=-2**9, max=2**9))
tx_gain_i = Signal(intbv(int(1.0 * 2**9 + .5))[10:])
tx_gain_q = Signal(intbv(int(1.0 * 2**9 + .5))[10:])
fcw = Signal(intbv(1)[fcw_bitwidth:])
txen = Signal(bool(0))
txstop = Signal(bool(0))
txfilteren = Signal(bool(0))
ddsen = Signal(bool(False))
loopen = Signal(bool(False))
decim = Signal(intbv(interp_default)[11:])
rx_correct_i = Signal(intbv(0, min=-2**9, max=2**9))
rx_correct_q = Signal(intbv(0, min=-2**9, max=2**9))
rxen = Signal(bool(0))
rxstop = Signal(bool(0))
rxfilteren = Signal(bool(0))
# The RAMs
fir_coeff_ram = Ram(clearn, dac_clock, bus.pclk, width=18, depth=512)
fir_delay_line_i_ram = Ram(clearn, dac_clock, dac_clock, width=9, depth=512)
fir_delay_line_q_ram = Ram(clearn, dac_clock, dac_clock, width=9, depth=512)
fir_coeff_ram_addr = fir_coeff_ram.port['a'].addr
fir_coeff_ram_din = fir_coeff_ram.port['a'].din
fir_coeff_ram_blk = fir_coeff_ram.port['a'].blk
fir_coeff_ram_wen = fir_coeff_ram.port['a'].wen
fir_coeff_ram_dout = fir_coeff_ram.port['a'].dout
fir_load_coeff_ram_addr = fir_coeff_ram.port['b'].addr
fir_load_coeff_ram_din = fir_coeff_ram.port['b'].din
fir_load_coeff_ram_blk = fir_coeff_ram.port['b'].blk
fir_load_coeff_ram_wen = fir_coeff_ram.port['b'].wen
fir_load_coeff_ram_dout = fir_coeff_ram.port['b'].dout
fir_delay_line_i_ram_addr = fir_delay_line_i_ram.port['a'].addr
fir_delay_line_i_ram_din = fir_delay_line_i_ram.port['a'].din
fir_delay_line_i_ram_blk = fir_delay_line_i_ram.port['a'].blk
fir_delay_line_i_ram_wen = fir_delay_line_i_ram.port['a'].wen
fir_delay_line_i_ram_dout = fir_delay_line_i_ram.port['a'].dout
fir_delay_line_q_ram_addr = fir_delay_line_q_ram.port['a'].addr
fir_delay_line_q_ram_din = fir_delay_line_q_ram.port['a'].din
fir_delay_line_q_ram_blk = fir_delay_line_q_ram.port['a'].blk
fir_delay_line_q_ram_wen = fir_delay_line_q_ram.port['a'].wen
fir_delay_line_q_ram_dout = fir_delay_line_q_ram.port['a'].dout
########### DIGITAL SIGNAL PROCESSING #######
loopback = Signature("loopback", False, bits=10)
duc_underrun = Signal(modbv(0, min=0, max=2**16))
dac_last = Signal(bool(0))
ddc_overrun = Signal(modbv(0, min=0, max=2**16))
ddc_flags = Signal(intbv(0)[4:])
adc_last = Signal(bool(0))
tx_sample = Signature("tx_sample", True, bits=16)
tx_sample_valid = tx_sample.valid
tx_sample_last = tx_sample.last
tx_sample_i = tx_sample.i
tx_sample_q = tx_sample.q
rx_sample = Signature("rx_sample", True, bits=16)
rx_sample_valid = rx_sample.valid
rx_sample_last = rx_sample.last
rx_sample_i = rx_sample.i
rx_sample_q = rx_sample.q
duc_args = (clearn, dac_clock, dac2x_clock,
loopen, loopback,
tx_fifo_empty, tx_fifo_re, tx_fifo_dvld, tx_fifo_rdata, tx_fifo_underflow,
txen, txstop,
ddsen, txfilteren,
interp, shift,
fcw,
tx_correct_i, tx_correct_q,
tx_gain_i, tx_gain_q,
duc_underrun, tx_sample,
dac_en, dac_data, dac_last,
rx_fifo_full, rx_fifo_we, rx_fifo_wdata,
rxen, rxstop, rxfilteren,
decim, rx_correct_i, rx_correct_q,
ddc_overrun, rx_sample,
adc_idata, adc_qdata, adc_last,
fir_coeff_ram_addr,
fir_coeff_ram_din,
fir_coeff_ram_blk,
fir_coeff_ram_wen,
fir_coeff_ram_dout,
fir_delay_line_i_ram_addr,
fir_delay_line_i_ram_din,
fir_delay_line_i_ram_blk,
fir_delay_line_i_ram_wen,
fir_delay_line_i_ram_dout,
fir_delay_line_q_ram_addr,
fir_delay_line_q_ram_din,
fir_delay_line_q_ram_blk,
fir_delay_line_q_ram_wen,
fir_delay_line_q_ram_dout,
firen, fir_bank1, fir_bank0, fir_N,)
duc_kwargs = dict(dspsim=dspsim,
interp=interp_default,
cic_enable=kwargs.get('cic_enable', True),
cic_order=kwargs.get('cic_order', 4),
cic_delay=kwargs.get('cic_delay', 1),
fir_enable=kwargs.get('fir_enable', True),
dds_enable=kwargs.get('dds_enable', True),
conditioning_enable=kwargs.get('conditioning_enable', True))
if kwargs.get("duc_enable", True):
duc = DUC(*duc_args, **duc_kwargs)
else:
duc = None
########### RADIO FRONT END ##############
rfe_args = (resetn,
pclk, paddr, psel, penable, pwrite, pwdata, pready, prdata, #pslverr,
clearn, clear_enable, loopen,
tx_status_led, tx_dmaready,
rx_status_led, rx_dmaready,
tx_fifo_we, tx_fifo_wdata,
tx_fifo_empty, tx_fifo_full,
tx_fifo_afval, tx_fifo_aeval, tx_fifo_afull, tx_fifo_aempty,
tx_fifo_wack, tx_fifo_dvld,
tx_fifo_overflow, tx_fifo_underflow,
tx_fifo_rdcnt, tx_fifo_wrcnt,
rx_fifo_re, rx_fifo_rdata,
rx_fifo_empty, rx_fifo_full,
rx_fifo_afval, rx_fifo_aeval, rx_fifo_afull, rx_fifo_aempty,
rx_fifo_wack, rx_fifo_dvld,
rx_fifo_overflow, rx_fifo_underflow,
rx_fifo_rdcnt, rx_fifo_wrcnt,
fir_load_coeff_ram_addr,
fir_load_coeff_ram_din,
fir_load_coeff_ram_blk,
fir_load_coeff_ram_wen,
fir_load_coeff_ram_dout,
firen, fir_bank1, fir_bank0, fir_N,
interp, shift,
fcw, tx_correct_i, tx_correct_q, tx_gain_i, tx_gain_q,
txen, txstop, ddsen, txfilteren,
decim, rx_correct_i, rx_correct_q,
rxen, rxstop, rxfilteren,
duc_underrun, dac_last,
ddc_overrun, adc_last)
rfe = RFE(*rfe_args)
instances = (rfe, duc)
if kwargs.get('fir_enable', True):
fir_coeff_ram_inst = fir_coeff_ram.instance_type()(**fir_coeff_ram.instance_signals())
fir_delay_line_i_ram_inst = fir_delay_line_i_ram.instance_type()(**fir_delay_line_i_ram.instance_signals())
fir_delay_line_q_ram_inst = fir_delay_line_q_ram.instance_type()(**fir_delay_line_q_ram.instance_signals())
instances += (fir_coeff_ram_inst, fir_delay_line_i_ram_inst, fir_delay_line_q_ram_inst)
return instances