def rms_process_chn(path,
wb,
onedir="step1",
env="RT",
FEMB="FEMB0",
rms_smps=130000,
jumbo_flag=False):
#### file_exist = os.path.exists( path + "\\" +onedir + "\\" + FEMB + "rms.xlsx")
#### if (file_exist):
#### os.remove( path + "\\" +onedir + "\\" + FEMB + "rms.xlsx")
####
#rms_data_dir = path + "\\" + onedir + "\\"
rms_data_dir = path + "/" + onedir + "/"
print rms_data_dir
for root, dirs, files in os.walk(rms_data_dir):
break
alldata = []
for chip in range(8):
for onefile in files:
pos1 = onefile.find(FEMB)
pos2 = onefile.find("_RMS")
pos3 = onefile.find("_RMS")
if (pos1 >= 0) and (pos2 >= 0) and (pos3 >= 0):
chip_num = int(onefile[onefile.find("CHIP") + 4])
if (chip_num == chip):
rms_data_file = rms_data_dir + onefile
print rms_data_file
fileinfo = os.stat(rms_data_file)
filelength = fileinfo.st_size
print filelength
with open(rms_data_file, 'rb') as f:
#raw_data = f.read(filelength)
raw_data = f.read()
#print len(raw_data)
#if ( filelength/2/16 > rms_smps ):
# smps = rms_smps
# #smps = (filelength-1024)/2/16
#else:
smps = (filelength - 1024) / 2 / 16
femb_num = int(onefile[onefile.find("FEMB") + 4])
chip_num = int(onefile[onefile.find("CHIP") + 4])
tp = int(onefile[onefile.find("CHIP") + 6])
print smps, femb_num, chip_num, tp
chn_data = raw_convertor(raw_data, smps, jumbo_flag)
alldata.append([femb_num, chip_num, tp, chn_data])
return alldata
def gain_process(path,
wb,
onedir="step1",
env="RT",
FEMB="FEMB0",
DAC="FPGADAC",
jumbo_flag=True):
#save_file = path + "\\" +onedir + "\\" + FEMB + DAC + "gain.xlsx"
save_file = path + "/" + onedir + "/" + "original" + FEMB + DAC + "gain.xlsx"
#gain_data_dir = path + "\\" + onedir + "\\"
gain_data_dir = path + onedir + "/"
print gain_data_dir
for root, dirs, files in os.walk(gain_data_dir):
break
print files
for onefile in files:
pos1 = onefile.find(FEMB)
pos2 = onefile.find(DAC)
#pos2 = onefile.find(DAC+"05")
#pos2 = onefile.find("CHIP5_3F_ASICDAC07")
pos3 = onefile.find(".bin")
#pos3 = onefile.find("step132_FEMB3CHIP7_3D_FPGADAC04.bin")
pos4 = onefile.find(DAC + "00")
if (pos1 >= 0) and (pos2 >= 0) and (pos3 >= 0) and (pos4 < 0):
gain_data_file = gain_data_dir + onefile
print gain_data_file
fileinfo = os.stat(gain_data_file)
filelength = fileinfo.st_size
with open(gain_data_file, 'rb') as f:
raw_data = f.read(filelength)
smps = (filelength - 1024) / 2 / 16
if (smps > 100000):
smps = 100000
else:
pass
chn_data = raw_convertor(raw_data, smps, jumbo_flag)
chn_peakmean = []
for chn in range(16):
#for chn in [4]:
np_data = np.array(chn_data[chn])
pedvalue = np.mean(np_data[0:10000])
#maxvalue = np.max(np_data[0:10000])
#print len(np_data)
maxvalue_np = []
for i in range(0, (len(np_data) - 2000) / 1000, 1):
# print np.max(np_data[1500*i:1500*(i+1)])
maxvalue_np.append(np.max(np_data[1000 * i:1000 *
(i + 1)]))
#print maxvalue_np
#maxvalue_np = maxvalue_np.sort()
maxvalue_np = sorted(maxvalue_np)
#print maxvalue_np
maxvalue = maxvalue_np[len(maxvalue_np) / 5]
peaks_index = detect_peaks(x=np_data,
mph=pedvalue + abs(
(maxvalue - pedvalue) * 2 / 3),
mpd=300)
peaks_index_len = len(peaks_index)
if ((peaks_index_len > 150) or (peaks_index_len < 5)):
print "ERROR, too many or too less peaks, please check!!!"
#print maxvalue
#exit()
peaks_value = []
for i in peaks_index:
peaks_value.append(np_data[i])
if len(peaks_value) != 0:
peaksmean = np.mean(peaks_value)
print "# of peaks = %d, mean =%d, delta=%d" % (
len(peaks_value), np.mean(peaks_value),
(np.mean(peaks_value) - pedvalue))
else:
peaksmean = pedvalue
print "NO Peaks"
chn_peakmean.append(peaksmean)
chip_pos = onefile.find("CHIP")
chip_num = int(onefile[chip_pos + 4:chip_pos + 4 + 1], 16)
dac_pos = onefile.find(DAC)
DAC_code = int(onefile[dac_pos + 7:dac_pos + 7 + 2], 16)
sheet_title = onefile[dac_pos - 3:dac_pos - 1]
ws = wb.active
try:
ws = wb.get_sheet_by_name(sheet_title)
except KeyError:
ws = wb.create_sheet(0)
ws.title = sheet_title #onedir[0:30]
for chn in range(16):
ws.cell(column=chn + 1,
row=chip_num + 1 + 16 * DAC_code,
value=chn_peakmean[chn])
wb.save(filename=save_file)
def fft_process_chn(path, onedir = "step1", env = "RT", runno = "run01" , FEMB = "FEMB0", chns = [0], jumbo_flag = False, FEset = "_1E_", one_chn_flg = False):
rms_data_dir = path + "/" + runno + "/" + onedir + "/"
for root, dirs, files in os.walk(rms_data_dir):
break
psum = None
chip_np = []
for chni in chns:
chiptmp = chni // 16
if ( len(np.where(np.array(chip_np) == chiptmp)[0]) == 0 ):
chip_np.append(chiptmp)
fs = 2000000.0
for chip in chip_np:
for onefile in files:
pos1 = onefile.find(FEMB)
pos2 = onefile.find("_RMS")
pos3 = onefile.find(FEset)
if (pos1 >= 0 ) and (pos2 >= 0) and (pos3 >= 0):
chip_num = int(onefile[onefile.find("CHIP")+4])
if (chip_num ==chip):
rms_data_file = rms_data_dir + onefile
fileinfo = os.stat(rms_data_file)
filelength = fileinfo.st_size
print rms_data_file
with open(rms_data_file, 'rb') as f:
raw_data = f.read()
smps = (filelength-1024)/2/16
femb_num = int(onefile[onefile.find("FEMB")+4])
chip_num = int(onefile[onefile.find("CHIP")+4])
tp = int(onefile[onefile.find("CHIP")+6])
chn_data = raw_convertor(raw_data, smps, jumbo_flag)
chipchn0 = chip * 16
for chni in range(16):
curchn = chipchn0 + chni
if ( len(np.where( np.array(chns) == curchn )[0] ) == 1 ):
print "curchn%d"%curchn
savefile = rms_data_dir + "FFT_chn_%X"%chni + onefile[0: pos3] + "_FFT" + onefile[pos3+4:]
onechndata = chn_data[chni]
fft_s = 400000
smp_data = onechndata
cycle = int(len(smp_data) / fft_s )
psd = True
if (psd == True):
f,p = chn_fft_psd(smp_data, fs = fs, fft_s=fft_s , avg_cycle =cycle)
else:
f,p = chn_fft(smp_data, fs = fs, fft_s=fft_s , avg_cycle =cycle)
if (type(psum) == type(None)):
f,p = chn_fft_psd(smp_data, fs = fs, fft_s=fft_s , avg_cycle =cycle)
psum = np.array(p)
else:
psum =psum + np.array(p)
onefilepng = onefile
break
if (one_chn_flg == True):
t_np = np.linspace (0, 100000*0.5, 100000/100)
rawmean = np.mean(smp_data)
rawrms = np.std(smp_data)
rms_info =[ np.array(smp_data[:100000:100])-rawmean, rawmean, rawrms,'r' ]
hpassfreq = 500
hflt_order =3
b,a = butter_hp_flt(fs, hpassfreq, hflt_order)
hw, hh = signal.freqz(b,a, worN= int(fs/2))
hp_paras = [hpassfreq, hflt_order, hw, abs(hh)]
hp_flt_data = signal.filtfilt(b,a, smp_data)
hf,hp = chn_fft_psd(hp_flt_data, fs = fs, fft_s=fft_s , avg_cycle =cycle)
hmean = np.mean(hp_flt_data)
hrms = np.std(hp_flt_data)
h_info =[ np.array(hp_flt_data[:100000:100])-hmean, hmean, hrms, 'g' ]
ppassfreq = 1000
pflt_order =3
b,a = butter_hp_flt(fs, ppassfreq, pflt_order)
pw, ph = signal.freqz(b,a, worN= int(fs/2))
pp_paras = [ppassfreq, pflt_order, pw, abs(ph)]
ps_flt_data = signal.filtfilt(b,a, smp_data)
pf,pp = chn_fft_psd(ps_flt_data, fs = fs, fft_s=fft_s , avg_cycle =cycle)
pmean = np.mean(ps_flt_data)
prms = np.std(ps_flt_data)
p_info =[ np.array(ps_flt_data[:100000:100])-pmean, pmean, prms, 'b' ]
# pstopfreq = 10
# ppassfreq = 1000
# pflt_order = 1
# b,a = butter_bandstop_flt(fs, pstopfreq, ppassfreq, pflt_order)
# pw, ph = signal.freqz(b,a, worN= int(fs/2))
# pp_paras = [pstopfreq, ppassfreq, pflt_order, pw, abs(ph)]
# ps_flt_data = signal.filtfilt(b,a, smp_data)
# pf,pp = chn_fft_psd(ps_flt_data, fs = fs, fft_s=fft_s , avg_cycle =cycle)
# pmean = np.mean(ps_flt_data)
# prms = np.std(ps_flt_data)
# p_info =[ np.array(ps_flt_data[:100000:100])-pmean, pmean, prms ]
#
flt_info = [hp_paras, pp_paras]
chnfft_process_plot(path, runno, onedir, onefilepng, curchn, f, p, hf, hp, pf, pp, rms_info, h_info, p_info, t_np, flt_info, FEset, fs)
return smp_data, f, p, hf, hp, pf, pp
else:
return f, psum
def adc_oft_set(self, femb_addr, en_oft=True):
clk_cs = 1
adc_en_gr = 1
snc_cs = 0
pls_cs = 1
dac_sel = 0
fpga_dac = 0
asic_dac = 0
sg = 0 #sg_tuple[0] #4.7mV/fC
tp = 1 #st_tuple[3] #3us
adc_oft_regs = []
val = 25
if (not (self.jumbo_flag)):
self.femb_config.femb.write_reg_wib_checked(0x1F, 0x1FB)
val = val * 8
else:
self.femb_config.femb.write_reg_wib_checked(0x1F, 0xEFB)
val = val
if (en_oft):
oft_mean_chns = []
print "Pedestal configuration starts..."
for adc_oft in range(4):
print "FEMB%d, EN_GR = 1, ADC_Offset = %d" % (femb_addr,
adc_oft)
self.fe_reg.set_fe_board() # reset the registers value
self.fe_reg.set_fe_board(sts=0,
sg=sg,
st=tp,
smn=0,
sdf=0,
slk0=0,
slk1=0,
swdac=0,
dac=0)
fe_regs = copy.deepcopy(self.fe_reg.REGS)
if (clk_cs == 1):
self.adc_reg.set_adc_board(clk0=1, f0=0) #external clk
adc_clk_regs = copy.deepcopy(self.adc_reg.REGS)
else:
self.adc_reg.set_adc_board(clk0=0, f0=0) #internal clk
adc_clk_regs = copy.deepcopy(self.adc_reg.REGS)
if (adc_en_gr == 1):
self.adc_reg.set_adc_board(d=adc_oft, engr=adc_en_gr)
adc_engr_regs = copy.deepcopy(self.adc_reg.REGS)
else:
self.adc_reg.set_adc_board(engr=adc_en_gr)
adc_engr_regs = copy.deepcopy(self.adc_reg.REGS)
adc_regs = []
for tmpi in range(len(adc_clk_regs)):
adc_regs.append(adc_clk_regs[tmpi] | adc_engr_regs[tmpi])
self.fe_adc_reg.set_board(fe_regs, adc_regs)
fe_adc_regs = copy.deepcopy(self.fe_adc_reg.REGS)
self.femb_config.config_femb(femb_addr, fe_adc_regs, clk_cs,
pls_cs, dac_sel, fpga_dac,
asic_dac)
self.reg_5_value = (self.reg_5_value & 0xFFFFFF00) + (0x00
& 0xFF)
self.femb_config.femb.write_reg_femb_checked(
femb_addr, 5, self.reg_5_value)
self.femb_config.config_femb_mode(femb_addr, pls_cs, dac_sel,
fpga_dac, asic_dac)
mean_chns = []
for asic in range(8):
rawdata = self.femb_config.get_rawdata_packets_femb(
femb_addr, asic, val)
smps = (len(rawdata) - 1024) // 2 // 16
if (smps > 5000):
smps = 5000
chn_data = raw_convertor(rawdata, smps, self.jumbo_flag)
for chn in range(16):
np_data = np.array(chn_data[chn])
np_tmp_data = []
for k in np_data:
m = k % 64
if (m == 62) or (m == 63) or (m == 0) or (
m == 1) or (m == 2):
pass
else:
np_tmp_data.append(k)
if (len(np_tmp_data) < 2):
np_tmp_data = np_data
pedvalue = int(np.mean(np_tmp_data))
mean_chns.append(pedvalue)
oft_mean_chns.append(mean_chns)
##################################################################################
adc_oft_class = ADC_ASIC_REG_MAPPING()
adc_oft_class.set_adc_board()
brd_means = []
for chip in range(8):
chip_means = []
for chn in range(16):
chipchn = (chip * 16) + chn
oftmod64 = []
for adc_oft in range(4):
oftmod64.append(
abs(((oft_mean_chns[adc_oft][chipchn]) % 64) - 32))
oftmod64 = np.array(oftmod64)
tmp = np.where(oftmod64 == (np.min(oftmod64)))
adc_oft_class.set_chn_reg(chip=chip, chn=chn, d=tmp[0][0])
chip_means.append(oft_mean_chns[tmp[0][0]][chipchn])
brd_means.append(chip_means)
adc_oft_regs = copy.deepcopy(adc_oft_class.REGS)
return adc_oft_regs
def asic_dac_cali(self, path, step, femb_addr, sg, tp, adc_oft_regs, yuv_bias_regs, clk_cs=1, pls_cs = 1, dac_sel=1, \
fpga_dac=0, asic_dac=1, slk0 = 0, slk1= 0, val=100):
print "FEMB_DAQ-->Calibration measurement with ASIC \"DAC\" starts"
savepath = self.wib_savepath(path, step)
file_setadc_rec = savepath + step + "_FEMB" + str(femb_addr) + str(
sg) + str(tp) + "ASICDAC_FE_ADC.txt"
if os.path.isfile(file_setadc_rec):
print "%s, file exist!!!" % file_setadc_rec
sys.exit()
else:
for dac in range(3, 64, 1):
self.fe_reg.set_fe_board() # reset the registers value
self.fe_reg.set_fe_board(sts=1,
sg=sg,
st=tp,
smn=0,
sdf=0,
slk0=slk0,
slk1=slk1,
swdac=1,
dac=dac)
fe_regs = copy.deepcopy(self.fe_reg.REGS)
adc_regs = self.adc_clk_engr_config(adc_oft_regs,
clk_cs=clk_cs,
adc_en_gr=1,
adc_offset=0)
fe_bias_regs = self.fe_regs_bias_config(
fe_regs, yuv_bias_regs) #one FEMB
self.fe_adc_reg.set_board(fe_bias_regs, adc_regs)
fe_adc_regs = copy.deepcopy(self.fe_adc_reg.REGS)
self.femb_config.config_femb(femb_addr, fe_adc_regs, clk_cs,
pls_cs, dac_sel, fpga_dac,
asic_dac)
self.reg_5_value = (self.reg_5_value & 0xFFFFFF00) + (0x00
& 0xFF)
self.femb_config.femb.write_reg_femb_checked(
femb_addr, 5, self.reg_5_value)
self.femb_config.config_femb_mode(femb_addr, pls_cs, dac_sel,
fpga_dac, asic_dac)
rawdata = self.femb_config.get_rawdata_packets_femb(femb_addr,
asic=0,
val=100)
smps = (len(rawdata) - 1024) // 2 // 16
chn_data = raw_convertor(rawdata, smps, self.jumbo_flag)
chn_peakmean = []
np_data = np.array(chn_data[self.peak_chn])
pedvalue = np.mean(np_data)
maxvalue = np.max(np_data)
peaks_index = detect_peaks(x=np_data,
mph=pedvalue + abs(
(maxvalue - pedvalue) * 2 / 3),
mpd=800)
peaks_value = []
for i in peaks_index:
peaks_value.append(np_data[i])
peaksmean = np.mean(peaks_value)
if (math.isnan(peaksmean)):
peaksmean = 0
else:
print "ASIC DAC = %d gets maximum ADC bin = %d" % (
dac, peaksmean)
if (peaksmean > 3000):
break
dly_pos = []
self.dly = 1
for dly in range(self.dly, self.dly + 20, 1):
self.reg_5_value = (self.reg_5_value & 0xFFFF00FF) + (
(dly << 8) & 0xFF00)
self.femb_config.femb.write_reg_femb_checked(
femb_addr, 5, self.reg_5_value)
self.femb_config.config_femb_mode(femb_addr, pls_cs, dac_sel,
fpga_dac, asic_dac)
rawdata = self.femb_config.get_rawdata_packets_femb(femb_addr,
asic=0,
val=100)
smps = (len(rawdata) - 1024) // 2 // 16
chn_data = raw_convertor(rawdata, smps, self.jumbo_flag)
chn_peakmean = []
for chn in [self.peak_chn]:
np_data = np.array(chn_data[chn])
pedvalue = np.mean(np_data)
maxvalue = np.max(np_data)
peaks_index = detect_peaks(
x=np_data,
mph=pedvalue + abs((maxvalue - pedvalue) * 2 / 3),
mpd=800)
peaks_value = []
for i in peaks_index:
peaks_value.append(np_data[i])
peaksmean = np.mean(peaks_value)
if (math.isnan(peaksmean)):
peaksmean = 0
dly_pos.append(peaksmean)
max_peak = max(dly_pos)
max_ind = np.where(dly_pos == max_peak)
self.dly = self.dly + max_ind[0][0]
self.reg_5_value = (self.reg_5_value & 0xFFFF00FF) + (
(self.dly << 8) & 0xFF00)
self.femb_config.femb.write_reg_femb_checked(
femb_addr, 5, self.reg_5_value)
self.femb_config.config_femb_mode(femb_addr, pls_cs, dac_sel,
fpga_dac, asic_dac)
print "FEMB_DAQ-->Dly search"
print "FEMB_DAQ-->Best DLY for current configuration is: %d" % self.dly
if sg == 0: #4.7mV/fC
dac_value_np = range(2, 64, 1)
elif sg == 2: #7.8mV/fC
dac_value_np = range(2, 32, 1)
elif sg == 1: #14mV/fC
dac_value_np = range(2, 12, 1)
elif sg == 3: #25mV/fC
dac_value_np = range(2, 10, 1)
for dac in dac_value_np:
self.fe_reg.set_fe_board() # reset the registers value
self.fe_reg.set_fe_board(sts=1,
sg=sg,
st=tp,
smn=0,
sdf=0,
slk0=slk0,
slk1=slk1,
swdac=1,
dac=dac)
fe_regs = copy.deepcopy(self.fe_reg.REGS)
adc_regs = self.adc_clk_engr_config(adc_oft_regs,
clk_cs=clk_cs,
adc_en_gr=1,
adc_offset=0)
fe_bias_regs = self.fe_regs_bias_config(
fe_regs, yuv_bias_regs) #one FEMB
self.fe_adc_reg.set_board(fe_bias_regs, adc_regs)
fe_adc_regs = copy.deepcopy(self.fe_adc_reg.REGS)
self.femb_config.config_femb(femb_addr, fe_adc_regs, clk_cs,
pls_cs, dac_sel, fpga_dac,
asic_dac)
self.reg_5_value = (self.reg_5_value & 0xFFFFFF00) + (0x00
& 0xFF)
self.femb_config.femb.write_reg_femb_checked(
femb_addr, 5, self.reg_5_value)
self.femb_config.config_femb_mode(femb_addr, pls_cs, dac_sel,
fpga_dac, asic_dac)
self.recfile_save(file_setadc_rec, step, femb_addr,
fe_adc_regs)
for chip in range(8):
rawdata = ""
fe_cfg = int((self.fe_adc_reg.REGS[5]) & 0xFF)
fe_cfg_r = int('{:08b}'.format(fe_cfg)[::-1], 2)
filename = savepath + step + "_FEMB" + str(
femb_addr) + "CHIP" + str(chip) + "_" + format(
fe_cfg_r, '02X') + "_ASICDAC" + format(
dac, '02X') + ".bin"
print filename
if os.path.isfile(filename):
print "%s, file exist!!!" % filename
sys.exit()
else:
rawdata = self.femb_config.get_rawdata_packets_femb(
femb_addr, chip, val)
if (rawdata != None):
with open(filename, "wb") as f:
f.write(rawdata)
def ext_dly_search(self,
femb_addr,
pls_cs=1,
dac_sel=1,
fpga_dac=1,
asic_dac=0):
print "FEMB_DAQ-->Start to find proper DLY to locate the peak of shaper"
#set proper ampl, which will let ADC value fall between 0x7ff and 0xb00
ampl = 1
while (ampl < 32):
self.reg_5_value = (self.reg_5_value & 0xFFFFFF00) + (ampl & 0xFF)
self.femb_config.femb.write_reg_femb_checked(
femb_addr, 5, self.reg_5_value)
self.femb_config.config_femb_mode(femb_addr, pls_cs, dac_sel,
fpga_dac, asic_dac)
asic = 0
val = 20
if (not (self.jumbo_flag)):
val = val * 8
else:
val = val
rawdata = self.femb_config.get_rawdata_packets_femb(
femb_addr, asic, val)
smps = (len(rawdata) - 1024) // 2 // 16
chn_data = raw_convertor(rawdata, smps, self.jumbo_flag)
chn_peakmean = []
np_data = np.array(chn_data[self.peak_chn])
pedvalue = np.mean(np_data)
maxvalue = np.max(np_data)
peaks_index = detect_peaks(x=np_data,
mph=pedvalue + abs(
(maxvalue - pedvalue) * 2 / 3),
mpd=800)
peaks_value = []
for i in peaks_index:
peaks_value.append(np_data[i])
peaksmean = np.mean(peaks_value)
if (math.isnan(peaksmean)):
peaksmean = 0
else:
print "FPGA DAC = %d gets maximum ADC bin = %d" % (ampl,
peaksmean)
if (peaksmean > 3000):
break
else:
ampl = ampl + 1
dly_pos = []
self.dly = 1
for dly in range(self.dly, self.dly + 20, 1):
self.reg_5_value = (self.reg_5_value & 0xFFFF00FF) + (
(dly << 8) & 0xFF00)
self.femb_config.femb.write_reg_femb_checked(
femb_addr, 5, self.reg_5_value)
self.femb_config.config_femb_mode(femb_addr, pls_cs, dac_sel,
fpga_dac, asic_dac)
val = 20
if (not (self.jumbo_flag)):
val = val * 8
else:
val = val
rawdata = self.femb_config.get_rawdata_packets_femb(
femb_addr, asic, val)
smps = (len(rawdata) - 1024) // 2 // 16
chn_data = raw_convertor(rawdata, smps, self.jumbo_flag)
chn_peakmean = []
for chn in [self.peak_chn]:
np_data = np.array(chn_data[chn])
pedvalue = np.mean(np_data)
maxvalue = np.max(np_data)
peaks_index = detect_peaks(x=np_data,
mph=pedvalue + abs(
(maxvalue - pedvalue) * 2 / 3),
mpd=800)
peaks_value = []
for i in peaks_index:
peaks_value.append(np_data[i])
peaksmean = np.mean(peaks_value)
if (math.isnan(peaksmean)):
peaksmean = 0
dly_pos.append(peaksmean)
max_peak = max(dly_pos)
max_ind = np.where(dly_pos == max_peak)
self.dly = self.dly + max_ind[0][0]
self.reg_5_value = (self.reg_5_value & 0xFFFF00FF) + (
(self.dly << 8) & 0xFF00)
self.femb_config.femb.write_reg_femb_checked(femb_addr, 5,
self.reg_5_value)
self.femb_config.config_femb_mode(femb_addr, pls_cs, dac_sel, fpga_dac,
asic_dac)
print "FEMB_DAQ-->Dly search"
print "FEMB_DAQ-->Best DLY for current configuration is: %d" % self.dly
