def __init__(self, filename=None): self._root = _Node() if filename is None: from os.path import dirname, join filename = join(dirname(__file__), 'allkeys.txt') # weights = {} #cache of (int, int, int, int) elements match = compile_re( r'^(?P<charList>[0-9A-F]{4,6}(?:[\s]+[0-9A-F]{4,6})*)[\s]*;[\s]*' r'(?P<collElement>(?:[\s]*\[(?:[\*|\.][0-9A-F]{4,6}){3,4}\])+)[\s]*' r'(?:#.*$|$)').match findall_ce = compile_re( r'\[.([^\]]+)\]?').findall # 'ce' means 'collation element' add = self._add with open(filename) as f: for line in f: re_result = match(line) if re_result is not None: group = re_result.group add([int(ch, 16) for ch in group('charList').split()], [ tuple( int(weight, 16) for weight in coll_element.split('.')) for coll_element in findall_ce(group('collElement')) ]) elif not line.startswith(('#', '@')) and line.split(): info('ERROR in line %s:', line)
class Retn(Reti): """ RETN """ regexp = compile_re('^1110110101000101$') def _message_log(self): return 'RETN'
def findCompoundIDByFeatureName(jobID, featureName, db): """ This function queries the MongoDB looking for the associated gene ID for the given gene name @param {String} jobID, the identifier for the running job, necessary to for the temporal caches @param {String} featureName, the name for the feature that we want to map @param {pymongo.Database} db, the open connection with MongoDB database @returns {List} matchedFeatures, a list of translated identifiers @returns {Boolean} found, True if we found at least one translation """ #Check if the id is ath the cache of translation # TODO: change "KEGG" for the proper database or leave it as it is? featureIDs = KeggInformationManager().findInTranslationCache( jobID, featureName, "compound") if (featureIDs != None): return featureIDs, True matchedFeatures = [] try: cursor = db.kegg_compounds.find({ "name": { "$regex": compile_re(".*" + featureName + ".*", IGNORECASE_re) } }) if (cursor.count() > 0): for item in cursor: matchedFeatures.append(item) return matchedFeatures, len(matchedFeatures) > 0 except Exception as ex: return matchedFeatures, False
class LdQN(LdRegisterNumber): """ LD q, n """ regexp = compile_re('^1111110100((?:0|1){3})110((?:0|1){8})$') def _instruction_selector(self, selector): return self._q_selector(selector)
class LdQQ(LdRegisterRegister): """ LD q, q' """ regexp = compile_re('^1111110101((?:0|1){3})((?:0|1){3})$') def _instruction_selector(self, selector): return self._q_selector(selector)
class Rst(Instruction): """ RST p """ regexp = compile_re('^11((?:0|1){3})111$') def _message_log(self, selector): return 'RST {:02X}'.format(self._address_selector(selector)) def _address_selector(self, selector): addresses = { 0b000: 0x00, 0b001: 0x08, 0b010: 0x10, 0b011: 0x18, 0b100: 0x20, 0b101: 0x28, 0b110: 0x30, 0b111: 0x38, } return addresses[selector] def _instruction_logic(self, selector): self._z80.ram.write(self._z80.sp.bits - 1, self._z80.pc.higher.bits) self._z80.ram.write(self._z80.sp.bits - 2, self._z80.pc.lower.bits) self._z80.sp.bits -= 2 self._z80.pc.bits = self._address_selector(selector)
class Neg(Instruction): """ NEG """ regexp = compile_re('^1110110101000100$') def _message_log(self): return 'NEG' def _update_flags(self, instruction_result): self._update_sign_flag(instruction_result) self._update_zero_flag(instruction_result) self._update_half_carry_flag(self._z80.a.bits.lower) self._update_overflow_flag(self._z80.a.bits) self._update_carry_flag(self._z80.a.bits) self._z80.f.set_add_substract_flag() # TODO: Is this behavior correct ? # Half carry will always be 1 because 0x00 is always less than # lower z80.a nibble. The only exception is when z80.a is also 0x00. def _half_carry(self, lower_nibble): return 0x00 < lower_nibble def _overflow(self, bits): return bits is 0x80 def _carry(self, bits): return bits is not 0x00 def _instruction_logic(self): neg_result = 0x00 - self._z80.a.bits self._update_flags(neg_result) self._z80.a.bits = neg_result
class LdRR(LdRegisterRegister): """ LD r, r' """ regexp = compile_re('^01((?:0|1){3})((?:0|1){3})$') def _instruction_selector(self, selector): return self._r_selector(selector)
class Ldi(Instruction): """ LDI """ regexp = compile_re('^1110110110100000$') def _message_log(self): return 'LDI' def _parity(self, instruction_result): return instruction_result != 0x00 def _update_flags(self): self._z80.f.reset_half_carry_flag() self._update_parity_flag(self._z80.bc.bits - 1) self._z80.f.reset_add_substract_flag() def _move_byte(self): self._z80.ram.write(self._z80.de.bits, self._z80.ram.read(self._z80.hl.bits)) self._z80.de.bits += 1 self._z80.hl.bits += 1 self._z80.bc.bits -= 1 def _instruction_logic(self): self._move_byte() self._update_flags()
class Cpi(Cp8Bit): """ CPI """ regexp = compile_re('^1110110110100001$') def _message_log(self): return 'CPI' def _update_flags(self, operands, instruction_result): self._update_sign_flag(instruction_result) self._update_zero_flag(instruction_result) self._update_half_carry_flag(instruction_result) self._update_overflow_flag(operands) self._z80.f.set_add_substract_flag() def _compare(self, operands): cp_result = reduce(lambda n, m: n - m, operands) self._z80.hl.bits += 1 self._z80.bc.bits -= 1 return cp_result def _instruction_logic(self): operands = [self._z80.a.bits, self._z80.ram.read(self._z80.hl.bits)] instruction_result = self._compare(operands) self._update_flags(operands, instruction_result)
class InRIndirectC(Instruction): """ IN r, (C) """ regexp = compile_re('^1110110101((?:0|1){3})000$') def _select_register(self, selector): registers = { 0b000: self._z80.b, 0b001: self._z80.c, 0b010: self._z80.d, 0b011: self._z80.e, 0b100: self._z80.h, 0b101: self._z80.l, 0b111: self._z80.a } return registers[selector] def _message_log(self, selector): register = self._select_register(selector) return 'IN {:}, (C)'.format(register.bits) def _update_flags(self, input_byte): self._update_sign_flag(input_byte) self._update_zero_flag(input_byte) self._z80.f.reset_half_carry_flag() self._update_parity_flag(input_byte) self._z80.f.reset_add_substract_flag() def _instruction_logic(self, selector): register = self._select_register(selector) register.bits = self._z80.device_manager.read(self._z80.c)
class AdcHLSS(Add16Bit): """ ADC HL, ss """ regexp = compile_re('^1110110101((?:0|1){2})1010$') def _message_log(self, selector): register = self._select_register(selector) return 'ADC HL, {:}'.format(register.label) def _instruction_selector(self, selector): return self._ss_selector(selector) def _instruction_logic(self, selector): register = self._select_register(selector) super(AdcHLSS, self)._instruction_logic( [self._z80.a.bits, register.bits, self._z80.f.carry_flag] ) def _update_flags(self, operands, instruction_result): self._update_sign_flag(instruction_result) self._update_zero_flag(instruction_result) self._update_half_carry_flag(operands) self._update_carry_flag(operands) self._update_overflow_flag(operands) self._z80.f.reset_add_substract_flag()
async def func(flt, _, m: Message): if not m.from_user: return False if m.from_user.is_bot: return False if any([m.forward_from_chat, m.forward_from]): return False if dev_cmd and (m.from_user.id not in DEV_LEVEL): # Only devs allowed to use this...! return False if sudo_cmd and (m.from_user.id not in SUDO_LEVEL): # Only sudos and above allowed to use it return False text: str = m.text or m.caption m.command = None if not text: return False regex = "^({prefix})+\\b({regex})\\b(\\b@{bot_name}\\b)?(.*)".format( prefix="|".join(escape(x) for x in flt.prefixes), regex="|".join(flt.commands), bot_name=BOT_USERNAME, ) matches = search(compile_re(regex), text) if matches: m.command = [matches.group(2)] matches = (matches.group(4)).replace( "'", "\\'", ) # fix for shlex qoutation error, majorly in filters db = Disabling(m.chat.id) disable_list = db.get_disabled() status = db.get_action() try: user_status = (await m.chat.get_member(m.from_user.id)).status except ValueError: # i.e. PM user_status = "creator" if str(matches.group(2)) in disable_list and user_status not in { "creator", "administrator", }: try: if status == "del": await m.delete() except RPCError: pass return False for arg in split(matches.strip()): m.command.append(arg) return True return False
def extract_transcript(cleantext): '''Given a ttml transcript remove tags and return clean text.''' cleanr = compile_re('<.*?>') cleantext = sub(cleanr, '', cleantext) cleantext = sub(r'\n\s*\n', '\n', cleantext) cleantext = sub(''', '\'', cleantext) return cleantext
class ExIndirectSPIY(Exchange): """ EX (SP), IY """ regexp = compile_re('^1111110111100011$') def _message_log(self): return 'EX (SP), IY' def _instruction_logic(self): self._swap_register_with_ram_word(self._z80.sp.bits, self._z80.iy)
def _validate(self, address): regexp = compile_re('(\d{1,3}\.){3}\d{1,3}') try: if not regexp.match(address) or not all([int(octet) <= 255 for octet in address.split('.', 3)]): return self._resolve_hostname(address) except ValueError: raise AddressError('Error - Invalid host name or address : \'{:}\'.'.format(address)) return address
class DecIY(Instruction): """ DEC IY """ regexp = compile_re('^1111110100101011$') def _message_log(self): return 'DEC IY' def _instruction_logic(self, selector): self._z80.iy.bits += 1
class IncIX(Instruction): """ INC IX """ regexp = compile_re('^1101110100100011$') def _message_log(self): return 'INC IX' def _instruction_logic(self, selector): self._z80.ix.bits += 1
class OutAIndirectN(Instruction): """ OUT (n), A """ regexp = compile_re('^11010011((?:0|1){8})$') def _message_log(self, address): return 'OUT ({:02X}), A'.format(address) def _instruction_logic(self, address): self._z80.device_manager.write(address, self._z80.a.bits)
class InFIndirectN(Instruction): """ IN F, (n) """ regexp = compile_re('^1110110101110000$') def _message_log(self, address): return 'IN F, ({:02X})'.format(address) def _instruction_logic(self, address): self._z80.f.bits = self._z80.device_manager.read(address)
class OutFIndirectN(Instruction): """ OUT (C), 0 """ regexp = compile_re('^1110110101110001$') def _message_log(self): return 'OUT (C), 0' def _instruction_logic(self, address): self._z80.device_manager.write(self._z80.c.bits, 0x00)
class JpIndirectIX(JpIndirectAddress): """ JP (IX) """ regexp = compile_re('^1101110111101001$') def _message_log(self): return 'JP (IX)' def _instruction_logic(self): super(JpIndirectIX, self)._instruction_logic(self._z80.ix.bits)
class Ex(Exchange): """ EX DE, HL """ regexp = compile_re('^11101011$') def _message_log(self): return 'EX DE, HL' def _instruction_logic(self): self._swap_registers(self._z80.de, self._z80.hl)
class PushIY(Push): """ PUSH IY """ regexp = compile_re('^1111110111100101$') def _message_log(self): return 'PUSH IY' def _instruction_logic(self): super(PushIY, self)._instruction_logic(self._z80.iy)
class LdSPHL(Instruction): """ LD SP, HL """ regexp = compile_re('^11111001$') def _message_log(self): return 'LD SP, HL' def _instruction_logic(self): self._z80.sp.bits = self._z80.hl.bits
class LdSPIY(Instruction): """ LD SP, IY """ regexp = compile_re('^1111110111111001$') def _message_log(self): return 'LD SP, IY' def _instruction_logic(self): self._z80.sp.bits = self._z80.iy.bits
class Im2(Instruction): """ IM 2 """ regexp = compile_re('^1110110101011110$') def _message_log(self): return 'IM 2' def _instruction_logic(self): self._z80.im = 0x02
class CpAN(Cp8Bit): """ CP A, n """ regexp = compile_re('^11111110((?:0|1){8})$') def _message_log(self, n): return 'CP A, {:02X}'.format(n) def _instruction_logic(self, n): super(CpAN, self)._instruction_logic([self._z80.a.bits, n])
class Ei(Instruction): """ EI """ regexp = compile_re('^11111011$') def _message_log(self): return 'EI' def _instruction_logic(self): self._z80.iff1, self._z80.iff2 = 0x01, 0x01
class Halt(Instruction): """ HALT """ regexp = compile_re('^01110110$') def _message_log(self): return 'HALT' def _instruction_logic(self): self._z80.halt()
class Nop(Instruction): """ NOP """ regexp = compile_re('^00000000$') def _message_log(self): return 'NOP' def _instruction_logic(self): pass
from ._bidict import bidict from re import compile as compile_re _LEGALNAMEPAT = '^[a-zA-Z][a-zA-Z0-9_]*$' _LEGALNAMERE = compile_re(_LEGALNAMEPAT) def _empty_namedbidict(mapname, fwdname, invname): """ Create an empty instance of a custom bidict. Used to make :func:`bidict.namedbidict` instances picklable. """ return namedbidict(mapname, fwdname, invname)() def namedbidict(mapname, fwdname, invname, base_type=bidict): """ Allows creating custom named bidict types, analagous to :func:`collections.namedtuple`. """ for name in mapname, fwdname, invname: if not _LEGALNAMERE.match(name): raise ValueError('"%s" does not match pattern %s' % (name, _LEGALNAMEPAT)) for_fwd = invname + '_for' for_inv = fwdname + '_for' __dict__ = {for_fwd: property(lambda self: self), for_inv: base_type.inv} custombidict = type(mapname, (base_type,), __dict__) # support pickling
def bold(s): return MIRC_CONTROL_BOLD + s + MIRC_CONTROL_BOLD def underline(s): return MIRC_CONTROL_UNDERLINE + s + MIRC_CONTROL_UNDERLINE def italicize(s): return MIRC_CONTROL_ITALICIZE + s + MIRC_CONTROL_ITALICIZE RE_COLOR_CODE = r'(\x03(([0-9]{1,2})(,[0-9]{1,2})?|[0-9]{2},[0-9]{1,2}))+' RE_TRAILING_COLOR_CODE = compile_re(RE_COLOR_CODE + r'$') RE_COLOR_CODE = compile_re(RE_COLOR_CODE) # Regarding mIRC color codes: Any valid FG or BG value will cause the text color # to be modified. All of the following will do something: # '\x0399,00', '\x0300,99', '\x0303,3238' (will display '38' in green text) def escape_control_codes(s): ''' Append the appropriate mIRC control character to string s to escape the active string control codes, or append MIRC_CONTROL_CLEARFORMATTING (\x0f) if multiple control codes are in play. e.g.: escape_control_codes('\x02\x1d\x0315TEST STRING') >>> '\x02\x1d\x0315TEST STRING\x0f' escape_control_codes('\x02TEST \x1fSTRI\x02NG')
# character info module. Information about unicode characters. from unicodedata import name from re import compile as compile_re, IGNORECASE from util import Mapping, argumentSplit, functionHelp # build mini database of character names: CHARACTER_DESC = [] for c in xrange(200000): # I think there is like 110000 unicode characters?? I don't know what ordinals they are though try: CHARACTER_DESC.append((c, name(unichr(c)))) except ValueError: pass # U+0430 DESC (CHR) RPLFORMAT = "U+%04X %s (%s)" # hex(ord(u"\u30F5")) REGHEX = compile_re("^[0-9A-F]{4}$", IGNORECASE) def _getname(c): try: return name(c) except ValueError: return "NO NAME" def funicode(event, bot): """ unicode [character(s)/description/hex]. Displays information about provided characters (limit of 3,) or does a search on the character description or provides information on the character indexed by the given hexidecimal.""" arg = event.argument if not arg: return bot.say(functionHelp(funicode)) if REGHEX.match(arg): i = int(arg, 16) u = unichr(i)
from re import compile as compile_re try: from cStringIO import StringIO except ImportError: from StringIO import StringIO from django.conf import settings from django.template import TemplateSyntaxError, Node, Library, Template register = Library() TEMPLATE_DEBUG = settings.TEMPLATE_DEBUG MEDIA_ROOT = settings.MEDIA_ROOT CACHE_DIR = "/tmp" templatevar_re = compile_re("\{\{(.+)\}\}") media_re = compile_re("\{\{MEDIA_ROOT|MEDIA_URL\}\}") class EmbeddedImgNode(Node): """Image node parser for rendering html inline base64 image""" def __init__(self, attributes): self.attrs = {} attrs = self.attrs for attr_value in attributes: try: attr, value = attr_value.split('=', 1) except ValueError, val_err: raise TemplateSyntaxError(u"Syntax Error :", val_err) attrs[attr] = value
time trace ulimit unistd utime utmpx wchar wctype wordexp alloca malloc '''.split() _include_pattern = compile_re(r'^ (/usr/[+\-./0-9@A-Z_a-z]+)$', M) _null_fd = open(devnull, O_RDWR) def main(dest_base='./converted_headers', *args, root=dirname(abspath(__file__))): cc1plus = check_output( ('gcc', '-print-prog-name=cc1plus'), stdin=_null_fd, stderr=_null_fd, ).decode('UTF-8', 'ignore').split('\n',1)[0] includepaths = _include_pattern.findall(check_output( (cc1plus, '-v'), stdin=_null_fd,