def MOD(i):
(l, y, z) = (datafile.block[i].out, datafile.block[i].op1, datafile.block[i].op2)
register.storereg('edx')
datafile.blockout.append("xor edx, edx")
datafile.lineno = datafile.lineno + 1
try :
int(z)
datafile.zprime = z
reg = register.emptyregister(i,['eax', 'edx'])
datafile.blockout.append('mov ' + reg + ", " + z)
datafile.lineno = datafile.lineno + 1
datafile.zprime = reg
except :
if datafile.addressdescriptor[z] == 'eax':
register.storereg(z)
register.getz(z)
pass
register.getreg(l, y, i, 'eax')
try :
int(y)
datafile.yprime = y
except :
pass
register.gety(y)
datafile.blockout.append("idiv " + register.mem(datafile.zprime))
datafile.lineno = datafile.lineno + 1
datafile.L = 'edx' #since the remainder is store in edx
register.update(l)
register_allocator.freereg(y, i)
register_allocator.freereg(z, i)
def DIV(i):
(l, y, z) = (datafile.block[i].out, datafile.block[i].op1, datafile.block[i].op2)
register.storereg('edx')
register.storereg('eax')
datafile.blockout.append("xor edx, edx")
try :
int(z)
reg = register.emptyregister(i,['edx', 'eax'])
datafile.blockout.append('mov ' + reg + ", " + z)
datafile.zprime = reg
except :
if datafile.addressdescriptor[z] == None:
reg = register.emptyregister(i,['edx', 'eax'])
datafile.blockout.append('mov ' + reg + ", " + register.mem(z))
datafile.zprime = reg
try :
int(y)
datafile.yprime = "eax"
datafile.blockout.append("mov eax," + y)
except :
datafile.blockout.append("mov eax," + register.mem(y))
datafile.yprime = "eax"
datafile.L = "eax"
datafile.blockout.append("idiv " +reg)
register.UpdateAddressDescriptor(l)
register.freereg(y, i)
register.freereg(z, i)
def MUL(i):
(y, z, l) = (datafile.block[i].op1, datafile.block[i].op2, datafile.block[i].out)
datafile.zprime = z
register.storereg("edx")
try:
int(z)
datafile.blockout.append("mov edx," + register.mem(datafile.zprime))
except:
if datafile.addressdescriptor[z] != None:
datafile.blockout.append("mov edx," + datafile.addressdescriptor[z])
else:
datafile.blockout.append("mov edx," + register.mem(datafile.zprime))
datafile.yprime = y
register.storereg("eax")
try:
int(y)
datafile.blockout.append("mov eax," + register.mem(datafile.yprime))
except:
if datafile.addressdescriptor[y] != None:
datafile.blockout.append("mov eax," + datafile.addressdescriptor[y])
else:
datafile.blockout.append("mov eax," + register.mem(datafile.yprime))
datafile.blockout.append("imul edx")
datafile.addressdescriptor[l] = "eax"
datafile.registerdescriptor["eax"] = l
register.freereg(y, i)
register.freereg(z, i)
def DIV(i):
(l, y, z) = (datafile.block[i].out, datafile.block[i].op1, datafile.block[i].op2)
register.storereg('edx')
datafile.blockout.append("xor %edx, %edx")
datafile.lineno = datafile.lineno + 1
try :
int(z)
reg = register.emptyregister(i,['edx', 'eax'])
datafile.blockout.append('mov $' + z + ", %" + reg)
datafile.lineno = datafile.lineno + 1
datafile.zprime = reg
except :
if datafile.addressdescriptor[z] == 'eax':
register.storereg(z)
register.getz(z)
pass
register.getreg(l, y, i, 'eax')
try :
int(y)
datafile.yprime = y
except :
pass
register.gety(y)
datafile.blockout.append("idivl " + register.mem(datafile.zprime))
datafile.lineno = datafile.lineno + 1
register.UpdateAddressDescriptor(l)
register.freereg(y, i)
register.freereg(z, i)
def FOPEN(i):
(y,z) = (datafile.block[i].op1,datafile.block[i].op2)
datafile.blockout.append("push ebx\npush ecx\npush edx")
register.storereg("eax")
reg = "eax"
inno = datafile.block[i].instnumber
datafile.blockout.append("xor eax, eax")
datafile.blockout.append("mov "+reg+", "+'str'+str(int(inno-1)))
datafile.blockout.append("push "+reg)
datafile.blockout.append("xor eax, eax")
datafile.blockout.append("mov "+reg+", "+'str'+str(int(inno-2)))
datafile.blockout.append("push "+reg)
datafile.blockout.append("call fopen")
datafile.blockout.append("pop edx\npop ecx\npop ebx")
def PUSH_ADDR(i):
var = datafile.block[i].out
t = False
if(var == "formatin"):
datafile.blockout.append("push formatin")
return
elif(var == "formatout"):
datafile.blockout.append("push formatout")
return
if datafile.addressdescriptor[var] != None :
place = datafile.addressdescriptor[var]
register.storereg(place)
place = register.emptyregister(i)
datafile.blockout.append("lea " + register.mem(place) +', ' + register.mem(var))
datafile.blockout.append("push " + place)
def PRINT(i):
l = datafile.block[i].out
register.storereg("eax")
try :
datafile.addressdescriptor[l]
datafile.blockout.append('push eax\npush ebx\npush ecx\npush edx\n')
datafile.blockout.append('xor eax, eax')
datafile.blockout.append('mov ' + 'eax, ' + datafile.addressdescriptor[l])
datafile.lineno = datafile.lineno + 3
except :
datafile.blockout.append('push eax\npush ebx\npush ecx\npush edx\n')
datafile.blockout.append('xor eax, eax')
datafile.blockout.append('mov ' + 'eax, ' + register.mem(l))
datafile.blockout.append('push eax')
datafile.blockout.append('push message')
datafile.blockout.append('call printf')
datafile.blockout.append('add esp, 8')
datafile.blockout.append('pop edx\npop ecx\npop ebx\npop eax\n')
datafile.lineno = datafile.lineno + 14
def FWRITE(i):
(y,z) = (datafile.block[i].op1,datafile.block[i].op2)
register.storereg("ebx")
register.storereg("ecx")
register.storereg("edx")
datafile.blockout.append("call fprintf")
datafile.blockout.append("add esp,8")
def FREAD(i):
(y,z) = (datafile.block[i].op1,datafile.block[i].op2)
register.storereg("ebx")
register.storereg("ecx")
register.storereg("edx")
datafile.blockout.append("call fscanf")
datafile.blockout.append("add esp,8")