def tr2(self, line):
if self.cpu.status.halted != 1:
raise Exception("cpu not halted")
while True:
self.cpu.mode.single_step = 1
i = self.cpu.ird
pc = self.cpu.pc
if i.mnemonic == 'lw':
eff = i.operands[1].eff
val = unpack(">I", self.cpu.tr_read(eff, 1))[0]
if eff & 0xffff8000 == 0xc0000000:
eff &= 0xffff
b, n, _, _ = reutils.whats_at(eff)
print "%08x: lw %08x from reg %04x (%s.%s)" % (pc, val,
eff, b, n)
else:
print "%08x: lw %08x from %08x" % (pc, val, eff)
elif i.mnemonic == 'sw':
eff = i.operands[1].eff
val = i.operands[0].eff
if eff & 0xffff8000 == 0xc0000000:
eff &= 0xffff
b, n, _, _ = reutils.whats_at(eff)
print "%08x: sw %08x to reg %04x (%s.%s)" % (pc, val, eff,
b, n)
else:
print "%08x: sw %08x to %08x" % (pc, val, eff)
def tr2(self, line):
if self.cpu.status.halted != 1:
raise Exception("cpu not halted")
while True:
self.cpu.mode.single_step = 1
i = self.cpu.ird
pc = self.cpu.pc
if i.mnemonic == 'lw':
eff = i.operands[1].eff
val = unpack(">I", self.cpu.tr_read(eff, 1))[0]
if eff & 0xffff8000 == 0xc0000000:
eff &= 0xffff
b, n, _, _ = reutils.whats_at(eff)
print "%08x: lw %08x from reg %04x (%s.%s)" % (pc, val, eff, b, n)
else:
print "%08x: lw %08x from %08x" % (pc, val, eff)
elif i.mnemonic == 'sw':
eff = i.operands[1].eff
val = i.operands[0].eff
if eff & 0xffff8000 == 0xc0000000:
eff &= 0xffff
b, n, _, _ = reutils.whats_at(eff)
print "%08x: sw %08x to reg %04x (%s.%s)" % (pc, val, eff, b, n)
else:
print "%08x: sw %08x to %08x" % (pc, val, eff)
def reg_finder(self):
dev = self.dev
regs = {}
with open('regs.csv', 'wb') as csvfile:
fns = ['offset', 'block', 'name', 'rw', 'mod_mask', 'o', 't1', 't2']
w = csv.DictWriter(csvfile, fieldnames=fns)
w.writeheader()
for dl in (True, False):
for pl in (True, False):
for hi1k in (True, False):
dev.grc.mode.pcie_dl_sel = 1 if dl else 0
dev.grc.mode.pcie_pl_sel = 1 if pl else 0
dev.grc.mode.pcie_hi1k_en = 1 if hi1k else 0
ss = "%s%s%s" % ("d" if dl else "",
"p" if pl else "",
"h" if hi1k else "")
for i in range(0x7c00, 0x8000, 4):
ofs = "%04x%s" % (i, ss)
bn = reutils.whats_at(i)
regs[ofs] = {'block': 'pcie_win',
'name': 'ofs_%03x' % (i - 0x7c00),
'offset': ofs,
'rw': '',
'mod_mask': '',
'o': '', 't1': '', 't2': ''}
o = dev.reg[i >> 2]
if o == 0xffffffff:
if dev.reg[0] == 0xffffffff:
raise Exception("device quit bus")
if False:
dev.reg[i >> 2] = 0xffffffff
t1 = dev.reg[i >> 2]
dev.reg[i >> 2] = 0
t2 = dev.reg[i >> 2]
dev.reg[i >> 2] = o
regs[ofs]['t1'] = "%08x" % t1
regs[ofs]['t2'] = "%08x" % t2
if (o ^ t1) or (o ^ t2):
regs[ofs]['rw'] = True
regs[ofs]['mod_mask'] = "%08x" % (~(t2 | ~t1))
regs[ofs]['o'] = "%08x" % o
w.writerow(regs[ofs])
csvfile.flush()
for i in range(0x100, 0x7c00, 4):
if i % 0x400 == 0:
print "now at %04x" % i
if 0 == os.system("dmesg -c | grep -q dmar"):
raise Exception("noticed dmar freaking out at %04x" % i)
bn = reutils.whats_at(i)
regs[i] = {'block': bn[0],
'name': bn[1],
'offset': "%04x" % i,
'rw': False,
'mod_mask': '',
'o': '', 't1': '', 't2': ''}
o = dev.reg[i >> 2]
if o == 0xffffffff:
if dev.reg[0] == 0xffffffff:
raise Exception("device quit bus")
if (i < 0x3600 or i > 0x36e8) and (i < 0x6800 or i > 0x68fc):
dev.reg[i >> 2] = 0xffffffff
t1 = dev.reg[i >> 2]
dev.reg[i >> 2] = 0
t2 = dev.reg[i >> 2]
dev.reg[i >> 2] = o
regs[i]['o'] = "%08x" % o
try:
regs[i]['t1'] = "%08x" % t1
regs[i]['t2'] = "%08x" % t2
if (o ^ t1) or (o ^ t2):
regs[i]['rw'] = True
regs[i]['mod_mask'] = "%08x" % (~(t2 | ~t1))
except:
pass
if regs[i]['name'].startswith('ofs') and regs[i]['rw']:
print "Unknown rw register at %04x" % i
w.writerow(regs[i])
return regs
