def spi_controller_top(clock, reset, sck, mosi, miso, ss):
"""SPI top-level for conversion testing"""
glbl = Global(clock, reset)
spibus = SPIBus(sck, mosi, miso, ss)
fifobus = FIFOBus()
cso = spi_controller.cso()
cso.isstatic = True
cfg_inst = cso.instances()
spi_controller.debug = False
spi_inst = spi_controller(glbl, spibus, fifobus, cso=cso)
@always_comb
def fifo_loopback():
fifobus.write_data.next = fifobus.read_data
fifobus.write.next = fifobus.read_valid
fifobus.read.next = not fifobus.empty
return myhdl.instances()
def spi_controller_top(clock, reset, sck, mosi, miso, ss):
"""SPI top-level for conversion testing"""
glbl = Global(clock, reset)
spibus = SPIBus(sck, mosi, miso, ss)
fifobus = FIFOBus()
cso = spi_controller.cso()
cso.isstatic = True
cfg_inst = cso.instances()
spi_controller.debug = False
spi_inst = spi_controller(glbl, spibus, fifobus, cso=cso)
@always_comb
def fifo_loopback():
fifobus.write_data.next = fifobus.read_data
fifobus.write.next = fifobus.read_valid
fifobus.read.next = not fifobus.empty
return myhdl.instances()
def spi_controller_top(clock, sck, mosi, miso, ss):
"""SPI top-level for conversion testing"""
glbl = Global(clock, reset)
spibus = SPIBus(sck, mosi, miso, ss)
fifobus = FIFOBus()
cso = spi_controller.cso()
cso.isstatic = True
cfg_inst = cso.get_generators()
spi_controller.debug = False
spi_inst = spi_controller(glbl, spibus, fifobus, cso=cso)
@always_comb
def fifo_loopback():
fifobus.write_data.next = fifobus.read_data
fifobus.write.next = fifobus.read_valid
fifobus.read.next = not fifobus.empty
reset_dly_cnt = Signal(intbv(0)[5:])
# software reset need for xula2
@always(clock.posedge)
def reset_tst():
'''
For the first 4 clocks the reset is forced to lo
for clock 6 to 31 the reset is set hi
then the reset is lo
'''
if (reset_dly_cnt < 31):
reset_dly_cnt.next = reset_dly_cnt + 1
if (reset_dly_cnt <= 4):
reset.next = 0
if (reset_dly_cnt >= 5):
reset.next = 1
else:
reset.next = 0
return myhdl.instances()
def _bench_spi():
tbdut = spi_controller(glbl, regbus,
fiforx, fifotx, spibus,
base_address=base_address)
tbeep = spiee.gen(clock, reset, spibus)
tbclk = clock.gen(hticks=5)
# grab all the register file outputs
tbmap = regbus.interconnect()
# get a reference to the SPI register file
rf = regbus.regfiles['SPI_000']
# dumpy the registers for the SPI peripheral
print("SPI register file")
for name, reg in rf.registers.items():
print(" {0} {1:04X} {2:04X}".format(name, reg.addr, int(reg)))
print("")
@instance
def tbstim():
yield reset.pulse(33)
yield delay(100)
yield clock.posedge
try:
# ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# loop through the registers and check the default
# values, these are the offset values.
for addr, sig in rf.roregs:
yield regbus.readtrans(addr+ba)
assert regbus.get_read_data() == int(sig), \
"Invalid read-only value"
for addr, sig in rf.rwregs:
# need to skip the FIFO read / write
if addr in (rf.sptx.addr, rf.sprx.addr,):
pass
else:
yield regbus.readtrans(addr+ba)
assert regbus.get_read_data() == int(sig), \
"Invalid default value"
# ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# enable the system
print("enable the SPI core")
yield regbus.writetrans(rf.spst.addr, 0x02) # register data drives fifo
yield regbus.writetrans(rf.spcr.addr, 0x9A) # default plus enable (98 + 02)
print("write to the transmit register")
for data in (0x02, 0x00, 0x00, 0x00, 0x55):
print("\nwriting to sptx {:02x}".format(data))
yield regbus.writetrans(rf.sptx.addr, data)
print("")
yield regbus.readtrans(rf.sptc.addr)
print("TX FIFO count {}".format(regbus.get_read_data()))
yield regbus.readtrans(rf.sprc.addr)
print("RX FIFO count {}".format(regbus.get_read_data()))
yield delay(1000)
print("wait for return bytes")
for ii in range(1000):
yield regbus.readtrans(rf.sprc.addr)
if regbus.get_read_data() == 5:
break
yield delay(10)
# verify bytes received and not timeout
print("RX FIFO count {}".format(regbus.get_read_data()))
assert regbus.get_read_data() == 5
print("read the returned bytes")
for ii in range(5):
yield regbus.readtrans(rf.sprx.addr)
print("spi readback {0}".format(regbus.get_read_data()))
except Exception as err:
print("@W: exception {0}".format(err))
yield delay(100)
traceback.print_exc()
raise err
yield delay(100)
raise StopSimulation
return tbstim, tbdut, tbeep, tbclk, tbmap
def m_test_top(clock, reset, sck, mosi, miso, ss):
# @todo: create a top-level for conversion ...
g_spi = spi_controller()
return g_spi
def bench_spi_cso():
spi_controller.debug = True # enable debug monitors
tbdut = spi_controller(glbl, spibus, fifobus, cso=cso)
tbeep = spiee.process(clock, reset, spibus)
tbclk = clock.gen(hticks=5)
@instance
def tbstim():
yield reset.pulse(33)
yield delay(100)
yield clock.posedge
try:
# enable the SPI core
cso.enable.next = True
cso.bypass_fifo.next = True
cso.loopback.next = True
# write to the transmit FIFO
values = (0x02, 0x00, 0x00, 0x00, 0x55)
for data in values:
cso.tx_byte.next = data
cso.tx_write.next = True
yield clock.posedge
cso.tx_write.next = False
while cso.tx_fifo_count > 0:
yield delay(100)
while cso.rx_fifo_count < 5:
yield delay(100)
ii, nticks = 0, 0
while ii < len(values):
if cso.rx_empty:
cso.rx_read.next = False
else:
cso.rx_read.next = True
if cso.rx_byte_valid:
assert values[ii] == cso.rx_byte, \
"{:<4d}: data mismatch, {:02X} != {:02X}".format(
ii, int(values[ii]), int(cso.rx_byte))
ii += 1
nticks = 0
yield clock.posedge, cso.rx_empty.posedge
cso.rx_read.next = False
if nticks > 30:
raise TimeoutError
nticks += 1
cso.rx_read.next = False
yield clock.posedge
except AssertionError as err:
asserr.next = True
print("@E: assertion {}".format(err))
yield delay(100)
traceback.print_exc()
raise err
raise StopSimulation
# monitor signals for debugging
tx_write, rx_read = Signals(bool(0), 2)
@always_comb
def tbmon():
rx_read.next = cso.rx_read
tx_write.next = cso.tx_write
return tbdut, tbeep, tbclk, tbstim, tbmon
def bench_spi():
tbdut = spi_controller(glbl, spibus, fifobus=fifobus, mmbus=regbus)
tbeep = spiee.gen(clock, reset, spibus)
tbclk = clock.gen(hticks=5)
# grab all the register file outputs
tbmap = regbus.interconnect()
# get a reference to the SPI register file
rf = regbus.regfiles['SPI_000']
# dumpy the registers for the SPI peripheral
print("SPI register file")
for name, reg in rf.registers.items():
print(" {0} {1:04X} {2:04X}".format(name, reg.addr, int(reg)))
print("")
@instance
def tbstim():
yield reset.pulse(33)
yield delay(100)
yield clock.posedge
try:
# ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# loop through the registers and check the default
# values, these are the offset values.
for addr, sig in rf.roregs:
yield regbus.readtrans(addr + ba)
assert regbus.get_read_data() == int(sig), \
"Invalid read-only value"
for addr, sig in rf.rwregs:
# need to skip the FIFO read / write
if addr in (
rf.sptx.addr,
rf.sprx.addr,
):
pass
else:
yield regbus.readtrans(addr + ba)
assert regbus.get_read_data() == int(sig), \
"Invalid default value"
# ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# enable the system
print("enable the SPI core")
yield regbus.writetrans(rf.spst.addr,
0x02) # register data drives fifo
yield regbus.writetrans(rf.spcr.addr,
0x9A) # default plus enable (98 + 02)
print("write to the transmit register")
for data in (0x02, 0x00, 0x00, 0x00, 0x55):
print("\nwriting to sptx {:02x}".format(data))
yield regbus.writetrans(rf.sptx.addr, data)
print("")
yield regbus.readtrans(rf.sptc.addr)
print("TX FIFO count {}".format(regbus.get_read_data()))
yield regbus.readtrans(rf.sprc.addr)
print("RX FIFO count {}".format(regbus.get_read_data()))
yield delay(1000)
print("wait for return bytes")
for ii in range(1000):
yield regbus.readtrans(rf.sprc.addr)
if regbus.get_read_data() == 5:
break
yield delay(10)
# verify bytes received and not timeout
print("RX FIFO count {}".format(regbus.get_read_data()))
assert regbus.get_read_data() == 5
print("read the returned bytes")
for ii in range(5):
yield regbus.readtrans(rf.sprx.addr)
print("spi readback {0}".format(regbus.get_read_data()))
except Exception as err:
print("@W: exception {0}".format(err))
yield delay(100)
traceback.print_exc()
raise err
yield delay(100)
raise StopSimulation
return tbstim, tbdut, tbeep, tbclk, tbmap
def m_test_top(clock, reset, sck, mosi, miso, ss):
# @todo: create a top-level for conversion ...
g_spi = spi_controller()
return g_spi
def bench_spi_cso():
spi_controller.debug = True # enable debug monitors
tbdut = spi_controller(glbl, spibus, fifobus, cso=cso)
tbeep = spiee.gen(clock, reset, spibus)
tbclk = clock.gen(hticks=5)
@instance
def tbstim():
yield reset.pulse(33)
yield delay(100)
yield clock.posedge
try:
# enable the SPI core
cso.enable.next = True
cso.bypass_fifo.next = True
cso.loopback.next = True
# write to the transmit FIFO
values = (0x02, 0x00, 0x00, 0x00, 0x55)
for data in values:
cso.tx_byte.next = data
cso.tx_write.next = True
yield clock.posedge
cso.tx_write.next = False
while cso.tx_fifo_count > 0:
yield delay(100)
while cso.rx_fifo_count < 5:
yield delay(100)
ii, nticks = 0, 0
while ii < len(values):
if cso.rx_empty:
cso.rx_read.next = False
else:
cso.rx_read.next = True
if cso.rx_byte_valid:
assert values[ii] == cso.rx_byte, \
"{:<4d}: data mismatch, {:02X} != {:02X}".format(
ii, int(values[ii]), int(cso.rx_byte))
ii += 1
nticks = 0
yield clock.posedge, cso.rx_empty.posedge
cso.rx_read.next = False
if nticks > 30:
raise TimeoutError
nticks += 1
cso.rx_read.next = False
yield clock.posedge
except AssertionError as err:
asserr.next = True
print("@E: assertion {}".format(err))
yield delay(100)
traceback.print_exc()
raise err
raise StopSimulation
# monitor signals for debugging
tx_write, rx_read = Signals(bool(0), 2)
@always_comb
def tbmon():
rx_read.next = cso.rx_read
tx_write.next = cso.tx_write
return tbdut, tbeep, tbclk, tbstim, tbmon