def icestick(clock, led, pmod, uart_tx, uart_rx):
""" Lattice Icestick example
"""
glbl = Global(clock, None)
tick_inst = glbl_timer_ticks(glbl, include_seconds=True)
# get interfaces to the UART fifos
fbusrtx = FIFOBus(width=8)
# get the UART comm from PC
uart_inst = uartlite(glbl, fbusrtx, uart_tx, uart_rx)
@always_comb
def beh_loopback():
fbusrtx.write_data.next = fbusrtx.read_data
fbusrtx.write.next = (not fbusrtx.full) & fbusrtx.read
lcnt = Signal(modbv(0, min=0, max=4))
@always(clock.posedge)
def beh_led_count():
if glbl.tick_sec:
lcnt.next = lcnt + 1
led.next = (1 << lcnt)
# system to test/interface
# other stuff
return myhdl.instances()
def test_known_prbs7(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
# computed by hand
expected_pattern = (0x3F, 0x10, 0x0C, 0xC5, 0x13, 0xCD, 0x95, 0x2F)
def _bench_prbs7():
tbdut = prbs_generate(glbl, prbs, order=7, initval=0x7F)
tbclk = clock.gen(hticks=8000)
@instance
def tbstim():
yield reset.pulse(32)
# there is one zero at the beginning
yield clock.posedge
for ii, ep in enumerate(expected_pattern):
yield clock.posedge
assert prbs == ep
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(_bench_prbs7, timescale='1ps', args=args)
def test_conversion(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
myhdl.toVerilog.directory = 'output'
myhdl.toVerilog.no_testbench = True
myhdl.toVHDL.directory = 'output'
# convert the generator
myhdl.toVerilog(prbs_generate, glbl, prbs, order=23)
myhdl.toVHDL(prbs_generate, glbl, prbs, order=23)
# convert the checker
locked = Signal(bool(0))
word_count = Signal(intbv(0)[64:])
error_count = Signal(intbv(0)[64:])
myhdl.toVerilog(prbs_check,
glbl,
prbs,
locked,
word_count,
error_count,
order=23)
myhdl.toVHDL(prbs_check,
glbl,
prbs,
locked,
word_count,
error_count,
order=23)
def mm_lt24lcdsys(clock, reset, lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn,
lcd_rdn, lcd_data):
"""
"""
# interfaces
glbl = Global(clock, reset)
lcd = LT24Interface()
resolution = lcd.resolution
color_depth = lcd.color_depth
refresh_rate = 60
vmem = VideoMemory(resolution=resolution, color_depth=color_depth)
# assign the ports to the interface
lcd.assign(lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn, lcd_rdn, lcd_data)
# simulation mode, reduce the dead time between real-world ticks
# modules
gtck = glbl_timer_ticks(glbl, user_timer=16, tick_div=100)
gbar = color_bars(glbl,
vmem,
resolution=resolution,
color_depth=color_depth)
glcd = lt24lcd(glbl, vmem, lcd)
return gtck, gbar, glcd
def convert(args):
glbl = Global(frequency=50e6)
vmem = VideoMemory()
toVerilog(m_color_bars, glbl, vmem, resolution=args.res, width=args.width)
toVHDL(m_color_bars, glbl, vmem, resolution=args.res, width=args.width)
def test_prbs_word_lengths(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
def _bench_prbs():
# currently only order 7, 9, 11, 15, 23, and 31 are coded in
# prbs feedback tap table, limit testing to one of these patterns
tbdut = prbs_generate(glbl, prbs, order=23)
tbclk = clock.gen(hticks=8000)
@instance
def tbstim():
yield reset.pulse(32)
# this test doesn't check the output (bad) simply checks that
# the module doesn't choke on the various word-lengths
for ii in range(27):
yield clock.posedge
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
for wl in [2**ii for ii in range(11)]:
prbs = Signal(intbv(0)[wl:])
run_testbench(_bench_prbs, timescale='1ps', args=args)
def icestick(clock, led, pmod, uart_tx, uart_rx):
""" Lattice Icestick example
"""
glbl = Global(clock, None)
gticks = glbl_timer_ticks(glbl, include_seconds=True)
# get interfaces to the UART fifos
fbustx = FIFOBus(width=8, size=8)
fbusrx = FIFOBus(width=8, size=8)
# get the UART comm from PC
guart = uartlite(glbl, fbustx, fbusrx, uart_tx, uart_rx)
@always_comb
def beh_loopback():
fbusrx.rd.next = not fbusrx.empty
fbustx.wr.next = not fbusrx.empty
fbustx.wdata.next = fbusrx.rdata
lcnt = Signal(modbv(0, min=0, max=4))
@always(clock.posedge)
def beh_led_count():
if glbl.tick_sec:
lcnt.next = lcnt + 1
led.next = (1 << lcnt)
# system to test/interface
# other stuff
return instances()
def xula_vga(
# ~~~[PORTS]~~~
vselect,
hsync, vsync,
red, green, blue,
pxlen, active,
clock,
reset=None,
# ~~~~[PARAMETERS]~~~~
# @todo: replace these parameters with a single VGATimingParameter
resolution=(640, 480,),
color_depth=(8, 8, 8,),
refresh_rate=60,
line_rate=31250
):
"""
(arguments == ports)
Arguments:
vselect:
Parameters:
resolution: the video resolution
color_depth: the color depth of a pixel, the number of bits
for each color component in a pixel.
refresh_rate: the refresh rate of the video
"""
# stub out reset if needed
if reset is None:
reset = ResetSignal(0, active=0, async=False)
@always(clock.posedge)
def reset_stub():
reset.next = not reset.active
else:
reset_stub = None
# create the system-level signals, overwrite clock, reset
glbl = Global(clock=clock, reset=reset)
# VGA inteface
vga = VGA()
# assign the top-level ports to the VGA interface
vga.assign(
hsync=hsync, vsync=vsync,
red=red, green=green, blue=blue,
pxlen=pxlen, active=active
)
# video memory interface
vmem = VideoMemory(color_depth=color_depth)
# color bar generation
bar_inst = color_bars(glbl, vmem, resolution=resolution)
# VGA driver
vga_inst = vga_sync(glbl, vga, vmem, resolution=resolution)
return myhdl.instances()
def testbench_memmap(args=None):
""" """
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, isasync=False)
glbl = Global(clock, reset)
csbus = Barebone(glbl, data_width=8, address_width=16)
@myhdl.block
def bench_memmap():
tbdut = peripheral(csbus)
tbclk = clock.gen()
print(csbus.regfiles)
@instance
def tbstim():
yield reset.pulse(111)
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_memmap)
def fifo_short(clock, reset, clear,
datain, src_rdy_i, dst_rdy_o,
dataout, src_rdy_o, dst_rdy_i):
glbl = Global(clock, reset)
wr = Signal(bool(0))
rd = Signal(bool(0))
args = Namespace(width=36, size=16, name='fifo_2clock_cascade')
fbus = FIFOBus(width=args.width)
# need to update the fbus refernces to reference the Signals in
# the module port list (function arguments).
fbus.write = wr
fbus.write_data = datain
fbus.read = rd
fbus.read_data = dataout
@always_comb
def beh_assign1():
wr.next = src_rdy_i & dst_rdy_o
rd.next = dst_rdy_i & src_rdy_o
@always_comb
def beh_assign2():
dst_rdy_o.next = not fbus.full
src_rdy_o.next = not fbus.empty
fifo_inst = fifo_fast(glbl, fbus, size=args.size)
return myhdl.instances()
def test_spi_models(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
glbl = Global(clock)
ibus = Barebone(glbl)
spibus = SPIBus()
def bench():
tbdut = spi_controller_model(clock, ibus, spibus)
tbspi = SPISlave().process(spibus)
tbclk = clock.gen()
@instance
def tbstim():
yield clock.posedge
yield ibus.writetrans(0x00, 0xBE)
yield delay(100)
yield ibus.readtrans(0x00)
raise StopSimulation
return tbdut, tbspi, tbclk, tbstim
run_testbench(bench, args=args)
def test_ibh(args=None):
args = tb_default_args(args)
numbytes = 13
clock = Clock(0, frequency=50e6)
glbl = Global(clock, None)
led = Signal(intbv(0)[8:])
pmod = Signal(intbv(0)[8:])
uart_tx = Signal(bool(0))
uart_rx = Signal(bool(0))
uart_dtr = Signal(bool(0))
uart_rts = Signal(bool(0))
uartmdl = UARTModel()
@myhdl.block
def bench_ibh():
tbclk = clock.gen()
tbmdl = uartmdl.process(glbl, uart_tx, uart_rx)
tbdut = icestick_blinky_host(clock, led, pmod,
uart_tx, uart_rx,
uart_dtr, uart_rts)
@instance
def tbstim():
yield delay(1000)
# send a write that should enable all five LEDs
pkt = CommandPacket(False, address=0x20, vals=[0xFF])
for bb in pkt.rawbytes:
uartmdl.write(bb)
waitticks = int((1/115200.) / 1e-9) * 10 * 28
yield delay(waitticks)
timeout = 100
yield delay(waitticks)
# get the response packet
for ii in range(PACKET_LENGTH):
rb = uartmdl.read()
while rb is None and timeout > 0:
yield clock.posedge
rb = uartmdl.read()
timeout -= 1
if rb is None:
raise TimeoutError
# the last byte should be the byte written
assert rb == 0xFF
yield delay(1000)
raise StopSimulation
return tbclk, tbmdl, tbdut, tbstim
run_testbench(bench_ibh, args=args)
inst = icestick_blinky_host(
clock, led, pmod,
uart_tx, uart_rx, uart_dtr, uart_rts
)
tb_convert(inst)
def test_adc128s022():
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=False)
glbl = Global(clock, reset)
fifobus = FIFOBus(width=16)
spibus = SPIBus()
channel = Signal(intbv(0, min=0, max=8))
step = 3.3 / 7
analog_channels = [Signal(3.3 - step * ii) for ii in range(0, 8)]
print(analog_channels)
assert len(analog_channels) == 8
def check_empty(clock, fifo):
for ii in range(4000):
if not fifo.empty:
break
yield clock.posedge
@myhdl.block
def bench_adc128s022():
tbdut = adc128s022(glbl, fifobus, spibus, channel)
tbmdl = adc128s022_model(spibus,
analog_channels,
vref_pos=3.3,
vref_neg=0.)
tbclk = clock.gen()
@instance
def tbstim():
sample = intbv(0)[16:]
yield reset.pulse(33)
yield clock.posedge
# check the conversion value for each channel, should get
# smaller and smaller
for ch in range(0, 8):
channel.next = (ch + 1) % 8 # next channel
yield check_empty(clock, fifobus)
# should have a new sample
if not fifobus.empty:
fifobus.read.next = True
sample[:] = fifobus.read_data
yield clock.posedge
fifobus.read.next = False
yield clock.posedge
print("sample {:1X}:{:4d}, fifobus {} \n".format(
int(sample[16:12]), int(sample[12:0]), str(fifobus)))
assert fifobus.empty
else:
print("No sample!")
yield delay(100)
raise StopSimulation
return tbdut, tbmdl, tbclk, tbstim
run_testbench(bench_adc128s022)
def testbench_streamer(args=None):
args = tb_default_args(args)
if not hasattr(args, 'keep'):
args.keep = False
if not hasattr(args, 'bustype'):
args.bustype = 'barebone'
clock = Clock(0, frequency=100e6)
reset = Reset(0, active=1, isasync=False)
glbl = Global(clock, reset)
# @todo: support all stream types ...
upstream = AXI4StreamLitePort(data_width=32)
downstream = AXI4StreamLitePort(data_width=32)
@myhdl.block
def bench_streamer():
tbdut = streamer_top(clock, reset, upstream, downstream, keep=args.keep)
tbclk = clock.gen()
dataout = []
@instance
def tbstim():
yield reset.pulse(42)
downstream.awaccept.next = True
downstream.waccept.next = True
data = [randint(0, (2**32)-1) for _ in range(10)]
for dd in data:
upstream.awvalid.next = True
upstream.awdata.next = 0xA
upstream.wvalid.next = True
upstream.wdata.next = dd
yield clock.posedge
upstream.awvalid.next = False
upstream.wvalid.next = False
# @todo: wait the appropriate delay given the number of
# @todo: streaming registers
yield delay(100)
print(data)
print(dataout)
assert False not in [di == do for di, do in zip(data, dataout)]
raise StopSimulation
@always(clock.posedge)
def tbcap():
if downstream.wvalid:
dataout.append(int(downstream.wdata))
return tbdut, tbclk, tbstim, tbcap
run_testbench(bench_streamer, args=args)
inst = streamer_top(clock, reset, upstream, downstream)
tb_convert(inst)
def mm_vgasys(
# ~~~[PORTS]~~~
clock,
reset,
vselect,
hsync,
vsync,
red,
green,
blue,
pxlen,
active,
# ~~~~[PARAMETERS]~~~~
resolution=(
640,
480,
),
color_depth=(
8,
8,
8,
),
refresh_rate=60,
line_rate=31250):
# create the system-level signals, overwrite clock, reset
glbl = Global(clock=clock, reset=reset)
# VGA interface
vga = VGA(hsync=hsync,
vsync=vsync,
red=red,
green=green,
blue=blue,
pxlen=pxlen,
active=active)
# video memory interface
vmem = VideoMemory(color_depth=color_depth)
# instances of modules
gbar = color_bars(glbl,
vmem,
resolution=resolution,
color_depth=color_depth)
gvga = vga_sync(glbl,
vga,
vmem,
resolution=resolution,
refresh_rate=refresh_rate,
line_rate=line_rate)
return gvga, gbar
def regfilesys(clock, reset):
"""
"""
glbl = Global(clock, reset)
csrbus = AXI4Lite(glbl, data_width=32, address_width=32)
cio = Signal(intbv(0)[8:])
mminst = memmap_component(glbl, csrbus, cio)
return mminst
def parallella_serdes(
clock,
# porcupine board breakout
serial_tx_p,
serial_tx_n,
serial_rx_p,
serial_rx_n,
led,
reset=None):
"""
"""
assert len(led) == 8
nbanks = len(serial_tx_p)
assert (len(serial_tx_p) == len(serial_tx_n) == len(serial_rx_p) ==
len(serial_rx_n))
glbl = Global(clock, reset)
# signal interface to the prbs generate / check
locked = [Signal(bool(0)) for _ in range(nbanks)]
inject_error = [Signal(bool(0)) for _ in range(nbanks)]
word_count = [Signal(intbv(0)[64:]) for _ in range(nbanks)]
error_count = [Signal(intbv(0)[64:]) for _ in range(nbanks)]
prbsi = [Signal(intbv(0)[1:]) for _ in range(nbanks)]
prbso = [Signal(intbv(0)[1:]) for _ in range(nbanks)]
# diff buffers for the diff signals
obuf = output_diff_buffer(prbso, serial_tx_p, serial_tx_n)
ibuf = input_diff_buffer(serial_rx_p, serial_rx_n, prbsi)
insts = []
for bank in range(nbanks):
gg = prbs_generate(glbl, prbso[bank], inject_error[bank], order=23)
gc = prbs_check(glbl,
prbsi[bank],
locked[bank],
word_count[bank],
error_count[bank],
order=23)
for gg in (
gg,
gc,
):
insts.append(gg)
locks = ConcatSignal(*reversed(locked))
@always_comb
def led_assign():
led.next = concat("1010", locks[4:])
return ibuf, obuf, insts, led_assign
def testbench_streamer(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=100e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
# @todo: support all stream types ...
upstream = AXI4StreamLitePort(data_width=32)
downstream = AXI4StreamLitePort(data_width=32)
def _bench_streamer():
tbdut = streamer_top(clock, reset, upstream, downstream, keep=args.keep)
tbclk = clock.gen()
dataout = []
@instance
def tbstim():
yield reset.pulse(42)
downstream.awaccept.next = True
downstream.waccept.next = True
data = [randint(0, (2**32)-1) for _ in range(10)]
for dd in data:
upstream.awvalid.next = True
upstream.awdata.next = 0xA
upstream.wvalid.next = True
upstream.wdata.next = dd
yield clock.posedge
upstream.awvalid.next = False
upstream.wvalid.next = False
# @todo: wait the appropriate delay given the number of
# @todo: streaming registers
yield delay(100)
print(data)
print(dataout)
assert False not in [di == do for di, do in zip(data, dataout)]
raise StopSimulation
@always(clock.posedge)
def tbcap():
if downstream.wvalid:
dataout.append(int(downstream.wdata))
return tbdut, tbclk, tbstim, tbcap
run_testbench(_bench_streamer, args=args)
myhdl.toVerilog.name = "{}".format(streamer_top.__name__)
if args.keep:
myhdl.toVerilog.name += '_keep'
myhdl.toVerilog.directory = 'output'
myhdl.toVerilog(streamer_top, clock, reset, upstream, downstream)
def test_spi_slave(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
spibus, fifobus = SPIBus(), FIFOBus()
# monitor the FIFOBus signals
data = Signal(intbv(0)[8:])
rd, wr, full, empty = Signals(bool(0), 4)
@myhdl.block
def bench_spi_slave():
tbdut = spi_slave_fifo(glbl, spibus, fifobus)
tbclk = clock.gen()
@instance
def tbstim():
yield reset.pulse(40)
yield delay(1000)
yield clock.posedge
# @todo: make generic
# @todo: random_sequence = [randint(0, fifobus.write_data.max) for _ in range(ntx)]
yield spibus.writeread(0x55)
yield spibus.writeread(0xAA)
yield spibus.writeread(0xCE)
assert spibus.get_read_data() == 0x55
yield spibus.writeread(0x01)
assert spibus.get_read_data() == 0xAA
yield spibus.writeread(0x01)
assert spibus.get_read_data() == 0xCE
raise StopSimulation
@always_comb
def tb_fifo_loopback():
if not fifobus.full:
fifobus.write.next = not fifobus.empty
fifobus.read.next = not fifobus.empty
fifobus.write_data.next = fifobus.read_data
# monitors
@always_comb
def tbmon():
data.next = fifobus.read_data
rd.next = fifobus.read
wr.next = fifobus.write
full.next = fifobus.full
empty.next = fifobus.empty
return tbdut, tbclk, tbstim, tb_fifo_loopback, tbmon
run_testbench(bench_spi_slave, args=args)
def test_memmap_command_bridge(args=None):
nloops = 37
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
fbtx, fbrx = FIFOBus(), FIFOBus()
memmap = Barebone(glbl, data_width=32, address_width=28)
fbtx.clock = clock
fbrx.clock = clock
def _bench_command_bridge():
tbclk = clock.gen()
tbdut = memmap_command_bridge(glbl, fbtx, fbrx, memmap)
tbfii = fifo_fast(clock, reset, fbtx)
tbfio = fifo_fast(clock, reset, fbrx)
# @todo: add other bus types
tbmem = memmap_peripheral_bb(clock, reset, memmap)
# save the data read ...
read_value = []
@instance
def tbstim():
yield reset.pulse(32)
try:
# test a single address
pkt = CommandPacket(True, 0x0000)
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [0])
pkt = CommandPacket(False, 0x0000, [0x5555AAAA])
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [0x5555AAAA])
# test a bunch of random addresses
for ii in range(nloops):
randaddr = randint(0, (2**20) - 1)
randdata = randint(0, (2**32) - 1)
pkt = CommandPacket(False, randaddr, [randdata])
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [randdata])
except Exception as err:
print("Error: {}".format(str(err)))
traceback.print_exc()
yield delay(2000)
raise StopSimulation
return tbclk, tbdut, tbfii, tbfio, tbmem, tbstim
run_testbench(_bench_command_bridge, args=args)
def catboard_blinky_host(clock, led, uart_tx, uart_rx):
"""
The LEDs are controlled from the RPi over the UART
to the FPGA.
"""
glbl = Global(clock, None)
ledreg = Signal(intbv(0)[8:])
# create the timer tick instance
tick_inst = glbl_timer_ticks(glbl, include_seconds=True)
# create the interfaces to the UART
fbustx = FIFOBus(width=8, size=4)
fbusrx = FIFOBus(width=8, size=4)
# create the memmap (CSR) interface
memmap = Barebone(glbl, data_width=32, address_width=32)
# create the UART instance.
uart_inst = uartlite(glbl,
fbustx,
fbusrx,
serial_in=uart_rx,
serial_out=uart_tx)
# create the packet command instance
cmd_inst = command_bridge(glbl, fbusrx, fbustx, memmap)
@always_seq(clock.posedge, reset=None)
def beh_led_control():
memmap.done.next = not (memmap.write or memmap.read)
if memmap.write and memmap.mem_addr == 0x20:
ledreg.next = memmap.write_data
@always_comb
def beh_led_read():
if memmap.read and memmap.mem_addr == 0x20:
memmap.read_data.next = ledreg
else:
memmap.read_data.next = 0
# blink one of the LEDs
tone = Signal(intbv(0)[8:])
@always_seq(clock.posedge, reset=None)
def beh_assign():
if glbl.tick_sec:
tone.next = (~tone) & 0x1
led.next = ledreg | tone[5:]
return (tick_inst, uart_inst, cmd_inst, beh_led_control, beh_led_read,
beh_assign)
def test_xula_vga(args=None):
args = tb_default_args(args)
resolution = (64, 48,)
refresh_rate = 60
line_rate = 31250
color_depth = (3, 4, 3,)
clock = Clock(0, frequency=12e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
vga = VGA(color_depth=color_depth)
vga_hsync, vga_vsync = Signals(bool(0), 2)
vga_red, vga_green, vga_blue = Signals(intbv(0)[6:], 3)
vselect = Signal(bool(0))
pxlen, active = Signals(bool(0), 2)
@myhdl.block
def bench():
tbdut = xula_vga(
clock, reset,
vselect, vga_hsync, vga_vsync,
vga_red, vga_green, vga_blue,
pxlen, active,
resolution=resolution, color_depth=color_depth,
refresh_rate=refresh_rate, line_rate=line_rate
)
tbclk = clock.gen()
mdl = VGADisplay(frequency=clock.frequency,
resolution=resolution,
refresh_rate=refresh_rate,
line_rate=line_rate,
color_depth=color_depth)
tbmdl = mdl.process(glbl, vga)
@instance
def tbstim():
yield delay(100000)
raise StopSimulation
return tbdut, tbclk, tbmdl, tbstim
# run the above stimulus, the above is not self checking it simply
# verifies the code will simulate.
run_testbench(bench, args=args)
portmap = dict(vselect=vselect, hsync=vga_hsync, vsync=vga_vsync,
red=vga_red, green=vga_green, blue=vga_blue,
clock=clock)
# convert the module, check for any conversion errors
tb_convert(xula_vga, **portmap)
def _bench_vgasys():
# top-level VGA system
tbdut = mm_vgasys(clock,
reset,
vselect,
vga.hsync,
vga.vsync,
vga.red,
vga.green,
vga.blue,
vga.pxlen,
vga.active,
resolution=resolution,
color_depth=color_depth,
refresh_rate=refresh_rate,
line_rate=line_rate)
# group global signals
glbl = Global(clock=clock, reset=reset)
# a display for each dut
mvd = VGADisplay(frequency=clock.frequency,
resolution=resolution,
refresh_rate=refresh_rate,
line_rate=line_rate,
color_depth=color_depth)
# connect VideoDisplay model to the VGA signals
tbvd = mvd.process(glbl, vga)
# clock generator
tbclk = clock.gen()
@instance
def tbstim():
reset.next = reset.active
yield delay(18)
reset.next = not reset.active
# Wait till a full screen has been updated
while mvd.update_cnt < 3:
yield delay(1000)
print("display updates complete")
time.sleep(1)
# @todo: verify video system memory is correct!
# @todo: (self checking!). Read one of the frame
# @todo: png's and verify a couple bars are expected
raise StopSimulation
return tbclk, tbvd, tbstim, tbdut
def testbench_nameofwhatsbeingtested(args=None):
""" """
# if no arguments were passed get the default arguments, one of
# the reasons this is done this way is to avoid conflicts with
# the py.test test runner, when executed with py.test no CLI
# arguments are expected (although the "test_*" might set specific
# arguments for a test.
args = tb_default_args(args)
if not hasattr(args, 'num_loops'):
args.num_loops = 10
# create signals, models, etc. that are needed for the various
# stimulus (a testbench may have multiple stimulus tests).
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, isasync=False)
glbl = Global(clock, reset)
sigin = Signal(intbv(0)[8:])
sigout = Signal(intbv(0)[8:])
# create a test/stimulus function, this function is passed
# to the `run_testbench` function. A single function is used
# so the signals in the stimulus can be traced.
@myhdl.block
def bench_nameofwhatsbeingtested():
""" """
# instantiate design under test, etc.
tbdut = some_module(glbl, sigin, sigout)
tbclk = clock.gen()
@instance
def tbstim():
yield reset.pulse(30)
yield clock.posedge
# perform stimulus and checking
for ii in range(args.num_loops):
sigin.next = randint(0, 255)
yield clock.posedge # on the edge the new input is capture
yield delay(1) # after the edge the output is available
print(" sigin: {:02X}, sigout: {:02X}".format(
int(sigin), int(sigout)))
assert sigout == sigin
raise StopSimulation
# return the generators (instances() could be used)
return tbdut, tbclk, tbstim
run_testbench(bench_nameofwhatsbeingtested, args=args)
def testbench_uart(args=None):
# @todo: get numbytes from args
numbytes = 7
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=True)
glbl = Global(clock, reset)
mdlsi, mdlso = Signal(bool(1)), Signal(bool(1))
uartmdl = UARTModel()
fifotx = FIFOBus()
fiforx = FIFOBus()
def _bench_uart():
tbmdl = uartmdl.process(glbl, mdlsi, mdlso)
tbdut = uartlite(glbl, fifotx, fiforx, mdlso, mdlsi)
tbclk = clock.gen()
@always_comb
def tblpbk():
fifotx.wdata.next = fiforx.rdata
fifotx.wr.next = not fiforx.empty
fiforx.rd.next = not fiforx.empty
@instance
def tbstim():
yield reset.pulse(33)
yield delay(1000)
yield clock.posedge
for ii in range(numbytes):
wb = randint(0, 255)
print("send {:02X}".format(wb))
uartmdl.write(wb)
timeout = ((clock.frequency / uartmdl.baudrate) * 40)
rb = uartmdl.read()
while rb is None and timeout > 0:
yield clock.posedge
rb = uartmdl.read()
timeout -= 1
if rb is None:
raise TimeoutError
print("received {:02X}".format(rb))
assert rb == wb, "{:02X} != {:02X}".format(rb, wb)
yield delay(100)
raise StopSimulation
return tbdut, tbmdl, tbclk, tblpbk, tbstim
run_testbench(_bench_uart, args=args)
def tb_ticks(args=None):
user_ms = 16
hticks = 5
clock = Clock(0, frequency=10e3)
reset = Reset(0, active=0, async=True)
glbl = Global(clock, reset)
def _bench_ticks():
tbdut = glbl_timer_ticks(glbl,
include_seconds=True,
user_timer=user_ms)
tbclk = clock.gen(hticks=hticks)
@instance
def tbstim():
yield reset.pulse(40)
# sync up, start 1 second in (slow clock)
yield glbl.tick_sec.posedge
tickstart = now()
yield glbl.tick_ms.posedge
tickms1 = now()
yield glbl.tick_ms.posedge
tickms2 = now()
yield glbl.tick_user.posedge
tickuser1 = now()
yield glbl.tick_user.posedge
tickuser2 = now()
yield glbl.tick_sec.posedge
ticksec1 = now()
yield glbl.tick_sec.posedge
ticksec2 = now()
# @todo: figure out if the sim ticks are correct
# 10k*10 per ms
sim_tick_ms = (clock.frequency / 1000) * (hticks * 2)
assert (tickms2 - tickms1) == sim_tick_ms
assert (tickuser2 - tickuser1) == sim_tick_ms * user_ms
assert (ticksec2 - ticksec1) == sim_tick_ms * 1000
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(_bench_ticks)
def test_lt24lcd(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=True)
glbl = Global(clock, reset)
lcd_on = Signal(bool(0))
lcd_resetn = Signal(bool(0))
lcd_csn = Signal(bool(0))
lcd_rs = Signal(bool(0))
lcd_wrn = Signal(bool(0))
lcd_rdn = Signal(bool(0))
lcd_data = Signal(intbv(0)[16:])
lcd = LT24Interface()
resolution = lcd.resolution
color_depth = lcd.color_depth
# assign the ports to the interface
lcd.assign(lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn,
lcd_rdn, lcd_data)
mvd = LT24LCDDisplay()
@myhdl.block
def bench_lt24lcdsys():
tbdut = mm_lt24lcdsys(
clock, reset, lcd_on, lcd_resetn,
lcd_csn, lcd_rs, lcd_wrn, lcd_rdn, lcd_data
)
tbvd = mvd.process(glbl, lcd) # LCD display model
tbclk = clock.gen()
@instance
def tbstim():
yield reset.pulse(33)
yield clock.posedge
timeout = 33000
while mvd.update_cnt < 3 and timeout > 0:
yield delay(1000)
timeout -= 1
yield delay(100)
print("{:<10d}: simulation real time {}".format(now(), mvd.get_time()))
raise StopSimulation
return tbdut, tbvd, tbclk, tbstim
run_testbench(bench_lt24lcdsys)
def spi_slave_led(clock, sck, mosi, miso, cs, leds ,out):
glbl = Global(clock)
spibus = SPIBus(sck=sck, mosi=mosi, miso=miso, ss=cs)
fifobus = FIFOBus()
div = divisor (clock, clk_div, 10)
fifobus.write_clock=clock
fifobus.read_clock=clock
rtl = recv_to_led(clock, fifobus, leds,out)
tbdut = spi_slave_fifo(glbl, spibus, fifobus)
@always_comb
def map():
spibus.csn.next = cs
return myhdl.instances()
def test_conversion(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
# convert the generator
inst = prbs_generate(glbl, prbs, order=23)
inst.convert(hdl='Verilog', testbench=False, directory='output')
# convert the checker
locked = Signal(bool(0))
word_count = Signal(intbv(0)[64:])
error_count = Signal(intbv(0)[64:])
inst = prbs_check(glbl, prbs, locked, word_count, error_count, order=23)
inst.convert(hdl='Verilog', testbench=False, directory='output')
def de0nano_lt24lcd(clock, reset, led,
# LT24 LCD display signals
lcd_on, lcd_resetn, lcd_csn, lcd_rs,
lcd_wrn, lcd_rdn, lcd_data
):
"""
The port names are the same as those in the board definition
(names in the user manual) for automatic mapping by the
rhea.build automation.
"""
# signals and interfaces
glbl = Global(clock, reset)
# ----------------------------------------------------------------
# global ticks
gtick = glbl_timer_ticks(glbl, include_seconds=True,
user_timer=16)
heartbeat = Signal(bool(0))
@always_seq(clock.posedge, reset=reset)
def rtl_leds():
if glbl.tick_sec:
heartbeat.next = not heartbeat
led.next = concat(intbv(0)[7:], heartbeat)
# ----------------------------------------------------------------
# LCD dislay
lcd = LT24Interface()
resolution, color_depth = lcd.resolution, lcd.color_depth
lcd.assign(lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn,
lcd_rdn, lcd_data)
# color bars and the interface between video source-n-sink
vmem = VideoMemory(resolution=resolution, color_depth=color_depth)
gbar = color_bars(glbl, vmem, resolution=resolution,
color_depth=color_depth)
# LCD video driver
glcd = lt24lcd(glbl, vmem, lcd)
gens = gtick, rtl_leds, gbar, glcd
return gens
