buf_size = wi * b - 1 # 4800 - 1 = 4799 hx8kboard = HX8KBoard() hx8kboard.Clock.on() hx8kboard.J2[9].output().on() hx8kboard.J2[10].output().on() hx8kboard.J2[11].output().on() hx8kboard.J2[12].output().on() main = hx8kboard.main() # "test" data init = [m.uint(i, 16) for i in range(16)] printf = mantle.Counter(4, has_ce=True) rom = ROM16(4, init, printf.O) # baud for uart output clock = mantle.CounterModM(103, 8) baud = clock.COUT bit_counter = mantle.Counter(5, has_ce=True) m.wire(baud, bit_counter.CE) load = mantle.Decode(0, 5)(bit_counter.O) valid_counter = mantle.CounterModM(buf_size, 13, has_ce=True) m.wire(load & baud, valid_counter.CE) valid_list = [wi * (b - 1) + i * a - 1 for i in range(1, wo + 1)] # len = 16
def definition(cam):
edge_f = falling(cam.SCK)
edge_r = rising(cam.SCK)
# ROM to store commands
rom_index = mantle.Counter(4, has_ce=True)
rom = ROM16(4, init, rom_index.O)
# Message length is 16 bits, setup counter to generate done signal
# after EOM
done_counter = mantle.Counter(5, has_ce=True, has_reset=True)
count = done_counter.O
done = mantle.Decode(16, 5)(count)
# State machine to generate run signal (enable)
run = mantle.DFF(has_ce=True)
run_n = mantle.LUT3([0, 0, 1, 0, 1, 0, 1, 0])
run_n(done, trigger, run)
run(run_n)
m.wire(edge_f, run.CE)
# Reset the message length counter after done
run_reset = mantle.LUT2(I0 | ~I1)(done, run)
done_counter(CE=edge_r, RESET=run_reset)
# State variables for high-level state machine
ready = mantle.LUT2(~I0 & I1)(run, edge_f)
start = mantle.ULE(4)(rom_index.O, m.uint(3, 4))
burst = mantle.UGE(4)(rom_index.O, m.uint(9, 4))
# Shift register to store 16-bit command|data to send
mosi = mantle.PISO(16, has_ce=True)
# SPI enable is negative of load-don't load and shift out data at the
# same time
enable = mantle.LUT3(I0 & ~I1 & ~I2)(trigger, run, burst)
mosi(~burst, rom.O, enable)
m.wire(edge_f, mosi.CE)
# Shit register to read in 8-bit data
miso = mantle.SIPO(8, has_ce=True)
miso(cam.MISO)
valid = mantle.LUT2(~I0 & I1)(enable, edge_r)
m.wire(valid, miso.CE)
# Capture done state variable
cap_done = mantle.SRFF(has_ce=True)
cap_done(mantle.EQ(8)(miso.O, m.bits(0x08, 8)), 0)
m.wire(enable & edge_r, cap_done.CE)
# Use state variables to determine what commands are sent (how)
increment = mantle.LUT4(I0 & (I1 | I2) & ~I3)(
ready, start, cap_done, burst)
m.wire(increment, rom_index.CE)
# wire outputs
m.wire(enable, cam.EN)
m.wire(mosi.O, cam.MOSI)
m.wire(miso.O, cam.DATA)
m.wire(burst, cam.VALID)
# --------------------------UART OUTPUT---------------------------- #
# run UART at 2x SPI rate to allow it to keep up
baud = edge_r | edge_f
# reset when SPI burst read (image transfer) begins
ff = mantle.FF(has_ce=True)
m.wire(edge_r, ff.CE)
u_reset = mantle.LUT2(I0 & ~I1)(burst, ff(burst))
# UART data out every 8 bits
u_counter = mantle.CounterModM(8, 3, has_ce=True, has_reset=True)
u_counter(CE=edge_r, RESET=u_reset)
load = burst & rising(u_counter.COUT)
uart = UART(8)
uart(CLK=cam.CLK, BAUD=baud, DATA=miso, LOAD=load)
# wire output
m.wire(uart, cam.UART)
# generate signal for when transfer is done
data_count = mantle.Counter(18, has_ce=True)
tx_done = mantle.SRFF(has_ce=True)
# transfer has size 153600 bytes, first 2 bytes are ignored
tx_done(mantle.EQ(18)(data_count.O, m.bits(153602, 18)), 0)
m.wire(load, tx_done.CE)
m.wire(load, data_count.CE)
# wire output
m.wire(tx_done, cam.DONE)
num_data = [uint(img_list[i], 16) for i in range(16)] # decrease the frequency to avoid timing violation counter = Counter(4) sclk = counter.O[-1] rom_idx = Counter(4, has_ce=True) full = SRFF(has_ce=True) check = EQ(4)(rom_idx.O, bits(15, 4)) full(check, 0) wire(falling(sclk), full.CE) rom_ce = rising(sclk) & ~full.O wire(rom_ce, rom_idx.CE) rom = ROM16(4, num_data, rom_idx.O) pipeline = Pipeline() wire(sclk, pipeline.CLK) wire(rom.O, pipeline.DATA) wire(rom_idx.O, pipeline.WADDR) wire(full.O, pipeline.RUN) wire(pipeline.O[:4], bits([main.D1, main.D2, main.D3, main.D4])) # light 5 indicates the end of prediction wire(pipeline.D, main.D5) # mem = MEM() # mem = ReadRom() # wire(sclk, mem.CLK)
addr = rom_idx.O[:4] bit_counter = mantle.Counter(5, has_ce=True) m.wire(rising(sclk), bit_counter.CE) we = mantle.Decode(0, 5)(bit_counter.O) load = rising(we) full = mantle.SRFF(has_ce=True) check = mantle.EQ(5)(rom_idx.O, m.bits(16, 5)) full(check, 0) m.wire(falling(sclk), full.CE) rom_ce = load & ~full.O m.wire(rom_ce, rom_idx.CE) rom = ROM16(4, num_data, addr) uart = UART(4) uart(CLK=main.CLKIN, BAUD=baud, DATA=addr, LOAD=load) pipeline = Pipeline() m.wire(sclk, pipeline.CLK) m.wire(rom.O, pipeline.DATA) m.wire(addr, pipeline.WADDR) m.wire(we, pipeline.WE) m.wire(full.O, pipeline.RUN) m.wire(pipeline.O[:4], m.bits([main.D1, main.D2, main.D3, main.D4])) # light 5 indicates the end of prediction m.wire(pipeline.D, main.D5)
array(int2seq(0x4200, 16)),
array(int2seq(0x4300, 16)),
array(int2seq(0x4400, 16)), # Read image length
array(int2seq(0x3CFF, 16)),
array(int2seq(0x0000, 16)), # burst read
array(int2seq(0x0000, 16)),
array(int2seq(0x0000, 16)),
array(int2seq(0x0000, 16)),
array(int2seq(0x0000, 16)),
array(int2seq(0x0000, 16)),
array(int2seq(0x0000, 16))
]
# ROM to store commands
rom_index = Counter(4, has_ce=True, has_reset=True)
rom = ROM16(4, init, rom_index.O)
data = array([
rom.O[0], rom.O[1], rom.O[2], rom.O[3], rom.O[4], rom.O[5], rom.O[6],
rom.O[7], rom.O[8], rom.O[9], rom.O[10], rom.O[11], rom.O[12], rom.O[13],
rom.O[14], rom.O[15]
])
# Message length is 16 bits, setup counter to generate done signal after EOM
done_counter = Counter(5, has_ce=True, has_reset=True)
count = done_counter.O
done = Decode(16, 5)(count)
# State machine to generate run signal (enable)
run = DFF(has_ce=True)
run_n = LUT3([0, 0, 1, 0, 1, 0, 1, 0])