###############################################################################
# Bench Settings
###############################################################################
FSW_IP = '192.168.1.109'
SMW_IP = '192.168.1.114'
###############################################################################
### Overhead: Import and create objects
###############################################################################
from rssd.VSA.ADemod_K7 import VSA
from rssd.VSG.Common import VSG
from rssd.FileIO import FileIO
OFile = FileIO().makeFile(__file__)
SMW = VSG().jav_Open(SMW_IP,OFile) # Create SMW Object
FSW = VSA().jav_Open(FSW_IP,OFile) # Create FSW Object
###############################################################################
### Function Definition
###############################################################################
def MeasRelPhase(FSW, SMW, x):
count = 0
leaveLoop = 0
while True:
SMW.Set_PhaseDelta((x-1)*10) # Initial Phase Shift
SMW.delay(Delay/1000)
FSW.write('INIT:IMM') # Initiate Sweep
SMW.delay(Delay/1000)
for i in range(NumMkrs + 2):
SMW.delay(Delay/1000)
SMW.Set_PhaseDelta((x)*10) # Initial Phase Shift
def setUp(self): #run before each test
self.FSW = VSA().jav_OpenTest(host)
self.FSW.Init_ADemod()
class TestGeneral(unittest.TestCase):
def setUp(self): #run before each test
self.FSW = VSA().jav_OpenTest(host)
self.FSW.Init_ADemod()
def tearDown(self): #Run after each test
self.assertEqual(self.FSW.jav_Error()[0],'0')
self.FSW.jav_Close()
###############################################################################
### <Test>
###############################################################################
def test_FSW_ADemod(self):
self.FSW.Set_Adem_dbw(3e6)
self.FSW.Set_Adem_LPassStat('OFF')
self.FSW.Set_Adem_LPassStat('ON')
self.FSW.Set_Adem_LPassAbsolute('3kHz')
self.FSW.Set_Adem_LPassManual(1e6)
self.FSW.Set_Adem_LPassRelative('5PCT')
getVal = self.FSW.Get_Adem_dbw()
if self.FSW.connected: self.assertEqual(getVal, 3e6)
def test_FSW_ADemod_PM(self):
self.FSW.Set_Freq(28e9) # RF Freq
self.FSW.Set_Adem_dbw(200e3) # Demod BW
self.FSW.Set_Adem_Coupling('AC') # Coupling
self.FSW.Set_Adem_PM_Unit('DEG') # Units
self.FSW.Set_Adem_PM_Scale(4) # Y Scaling
self.FSW.Set_Adem_PM_RefPos(50) # Phase Reference Position
self.FSW.Set_Adem_PM_RefVal(1) # Phase Reference Value
self.FSW.Set_In_YIG('ON') # YIG ON
class TestGeneral(unittest.TestCase):
def setUp(self): #run before each test
self.FSW = VSA().jav_OpenTest(host)
self.FSW.Init_ADemod()
def tearDown(self): #Run after each test
self.assertEqual(self.FSW.jav_Error()[0],'0')
self.FSW.jav_Close()
###############################################################################
### <Test>
###############################################################################
def test_FSW_ADemod(self):
self.FSW.Set_Adem_dbw(3e6)
self.FSW.Set_Adem_LPassStat('OFF')
self.FSW.Set_Adem_LPassStat('ON')
self.FSW.Set_Adem_LPassAbsolute('3kHz')
self.FSW.Set_Adem_LPassManual(1e6)
self.FSW.Set_Adem_LPassRelative('5PCT')
getVal = self.FSW.Get_Adem_dbw()
if self.FSW.connected: self.assertEqual(getVal, 3e6)
# Bench Settings
##########################################################
FSW_IP = '192.168.1.109'
SMW_IP = '192.168.1.114'
##########################################################
### Code Overhead: Import and create objects
##########################################################
from rssd.VSA.ADemod_K7 import VSA
from rssd.VSG.Common import VSG
from rssd.FileIO import FileIO
import time
OFile = FileIO().makeFile(__file__)
SMW = VSG().jav_Open(SMW_IP, OFile) #Create SMW Object
FSW = VSA().jav_Open(FSW_IP, OFile) #Create FSW Object
##########################################################
### Function Definition
##########################################################
def MeasRelPhase(FSW, SMW, x):
count = 0
leaveLoop = 0
while True:
SMW.Set_PhaseDelta((x - 1) * 10) #Initial Phase Shift
time.sleep(Delay / 1000) #Wait for phase settling
FSW.write('INIT:IMM') #Initiate Sweep
time.sleep(Delay / 1000) #Wait
for i in range(NumMkrs + 2):
time.sleep(Delay / 1000) #Wait
def test_VSA_5GNR(self):
from rssd.VSA.NR5G_K144 import VSA #pylint:disable=E0611,E0401
self.FSW = VSA()
self.assertEqual(self.FSW.Model,"FSW")
def test_VSA_Transient(self):
from rssd.VSA.Transient_K60 import VSA #pylint:disable=E0611,E0401
self.FSW = VSA()
self.assertEqual(self.FSW.Model,"FSW")
def test_VSA_NoiseFigure(self):
from rssd.VSA.NoiseFigure_K30 import VSA #pylint:disable=E0611,E0401
self.FSW = VSA()
self.assertEqual(self.FSW.Model,"FSW")
def test_VSA_LTE(self):
from rssd.VSA.LTE_K100 import VSA #pylint:disable=E0611,E0401
self.FSW = VSA()
self.assertEqual(self.FSW.Model,"FSW")
def test_VSA_Common(self):
from rssd.VSA.Common import VSA #pylint:disable=E0611,E0401
self.FSW = VSA()
self.assertEqual(self.FSW.Model,"FSW")
def test_VSA_ADemod(self):
from rssd.VSA.ADemod_K7 import VSA #pylint:disable=E0611,E0401
self.FSW = VSA()
self.assertEqual(self.FSW.Model,"FSW")
def test_VSA_WLAN(self):
from rssd.VSA.WLAN_K91 import VSA #pylint:disable=E0611,E0401
self.FSW = VSA()
self.assertEqual(self.FSW.Model,"FSW")