def test_ram_can_store_values(): mar = MemoryAddressRegister() ram = RandomAccessMemory(mar) # store address for ram in register mar.clock(data=0x0F, con=['lm']) assert mar.value == 0x0F # clock data into ram at the address set above ram.clock(data=0xAB, con=['lr']) assert ram.data() == None assert ram.data(['er']) == 0xAB # don't clock data into ram at the address set above ram.clock(data=0xAA) assert ram.data(['er']) == 0xAB
def test_memory_address_register_latches_data_on_lm(): mar = MemoryAddressRegister() assert mar.data() == None mar.clock(data=0x0F, con=['lm']) assert mar.value == 0x0F mar.clock(data=0x03, con=['lm']) assert mar.value == 0x03 mar.clock(data=0x0C, con=[]) assert mar.value == 0x03
def test_dma_reader(): program = [1, 2, 3, 4, 5, 6] mar = MemoryAddressRegister() ram = RandomAccessMemory(mar) switches = SwitchBoard(ram, mar) switches.load_program(program) dma = DMAReader(ram, mar) for orig, read in zip(program, dma.read_ram().flatten()): assert orig == read
def test_switches_can_initialize_ram(): program = [0xFA, 0x12] mar = MemoryAddressRegister() ram = RandomAccessMemory(mar) switches = SwitchBoard(ram, mar) switches.load_program(program) # set ram address mar.clock(data=0x00, con=['lm']) assert ram.data(['er']) == 0xFA mar.clock(data=0x01, con=['lm']) assert ram.data(['er']) == 0x12 mar.clock(data=0x00, con=['lm']) assert ram.data(['er']) == 0xFA
def test_t1_transfers_instruction_from_ram_to_instruction_register(): reg_i = RegisterInstruction() clock = Clock(reg_i) mar = MemoryAddressRegister() ram = RandomAccessMemory(mar) clock.add_component(mar) clock.add_component(ram) clock.add_component(reg_i) # reset CPU clock.reset() # contrive for test switches = SwitchBoard(ram, mar) program = [0xFA, 0x12] switches.load_program(program) mar.clock(data=0x01, con=['lm']) # get the second instruction next clock.t_state = 1 # apply single clock cycle clock.step() assert reg_i.value == 0x12
def test_addresses_must_be_8_bit(): mar = MemoryAddressRegister() ram = RandomAccessMemory(mar) bitmax = 0xFF # store address for ram in register mar.clock(data=bitmax, con=['lm']) assert mar.value == bitmax with pytest.raises(ValueError): mar.clock(data=bitmax + 1, con=['lm'])
def test_t0_transfers_pc_to_mar(): clock = Clock() pc = ProgramCounter() mar = MemoryAddressRegister() clock.add_component(pc) clock.add_component(mar) # reset CPU clock.reset() # contrive for test pc.clock(data=0x0C, con=['lp']) clock.t_state = 0 # apply single clock cycle clock.step() assert mar.value == 0x0C
def test_dma_reader_handler(): program = [1, 2, 3, 4, 5, 6] mar = MemoryAddressRegister() ram = RandomAccessMemory(mar) switches = SwitchBoard(ram, mar) switches.load_program(program) dma = DMAReader(ram, mar) called = False def test_handler(result): nonlocal called called = True dma.connect_dma_handler(test_handler) assert called == False dma.clock(con=[]) assert called == False dma.clock(con=['dma']) assert called == True