def pktSendDMA(toPort, pkt):
f = simLib.fDMA()
pktLen = len(pkt)
# convert packet to string
strpkt = ""
count = 1
for x in str(pkt):
strpkt += "%02x"%ord(x)
if count < 4:
count += 1
else:
strpkt += "\n"
count = 1
# pad packet if needed
if len(pkt)%4 != 0:
count -= 1
while count != 4:
strpkt += '00'
count += 1
# increment counter
SentPktsDMAcount[toPort-1] += 1
# write packet
f.write("// Packet " + str(SentPktsDMAcount[toPort-1]) + " at port " +
str(toPort) + "\n")
f.write("%08x"%pktLen + " // Length without CRC\n")
f.write(str.rstrip(strpkt))
f.write('\neeeeffff // End of pkt marker for pkt ' +
str(SentPktsDMAcount[toPort-1]) + ' (this is not sent).\n')
simReg.regDMA(toPort, len(pkt))
def pktSendDMA(toPort, pkt):
f = simLib.fDMA()
pktLen = len(pkt)
# convert packet to string
strpkt = ""
count = 1
for x in str(pkt):
strpkt += "%02x"%ord(x)
if count < 4:
count += 1
else:
strpkt += "\n"
count = 1
# pad packet if needed
if len(pkt)%4 != 0:
count -= 1
while count != 4:
strpkt += '00'
count += 1
# increment counter
SentPktsDMAcount[toPort-1] += 1
# write packet
f.write("// Packet " + str(SentPktsDMAcount[toPort-1]) + " at port " +
str(toPort) + "\n")
f.write("%08x"%pktLen + " // Length without CRC\n")
f.write(str.rstrip(strpkt))
f.write('\neeeeffff // End of pkt marker for pkt ' +
str(SentPktsDMAcount[toPort-1]) + ' (this is not sent).\n')
simReg.regDMA(toPort, len(pkt))
def nftest_send_dma(ifaceName, pkt, exp = True):
sent_dma[ifaceName].append(pkt)
if sim:
for pkt_s in pkt:
pkt_s.tuser_sport = 1 << (int(ifaceName[2:3])%4*2 + 1) # PCI ports are odd-numbered
for i in range(len(pkt)):
simPkt.pktSendDMA(int(ifaceName[2:3])+1, pkt)
f = simLib.fDMA()
axitools.axis_dump( pkt, f, 256, 1e-9 )
else:
hwPktLib.send(iface_map[ifaceName], pkt, exp)
def nftest_send_dma(ifaceName, pkt):
sent_dma[ifaceName].append(pkt)
if sim:
for pkt_s in pkt:
pkt_s.tuser_sport = 1 << (int(ifaceName[2:3])%4*2 + 1) # PCI ports are odd-numbered
for i in range(len(pkt)):
simPkt.pktSendDMA(int(ifaceName[2:3])+1, pkt)
f = simLib.fDMA()
axitools.axis_dump( pkt, f, 256, 1e-9 )
else:
hwPktLib.send(iface_map[ifaceName], pkt)
def barrier():
for i in range(NUM_PORTS): # 0,1,2,3
simLib.fPort(i + 1).write("# BARRIER\n")
simLib.fPort(i + 1).write("B " + "%d\n" % CMD_BARRIER)
simLib.fPort(i + 1).write("# EXPECTED\n")
simLib.fPort(i + 1).write("N " + "%d\n" % (numExpectedPktsPHY[i]))
simLib.fPort(i + 1).write("# SENT\n")
simLib.fPort(i + 1).write("S " + "%d\n\n" % (numSendPktsPHY[i]))
simLib.fDMA().write("# BARRIER\n")
simLib.fDMA().write("B " + "%d\n" % CMD_BARRIER)
simLib.fDMA().write("# EXPECTED\n")
simLib.fDMA().write("N " + "%d\n" % (numExpectedPktsDMA[0]))
simLib.fDMA().write("# SENT\n")
simLib.fDMA().write("S " + "%d\n\n" % (numSendPktsDMA[0]))
simLib.fregstim().write("# BARRIER\n")
simLib.fregstim().write("B " + "%d\n" % CMD_BARRIER_REG)
for i in range(NUM_PORTS):
simLib.fregstim().write("# Interface " + "%d\n" % (i))
simLib.fregstim().write("N " + "%d\n" % (numExpectedPktsPHY[i]))
simLib.fregstim().write("S " + "%d\n" % (numSendPktsPHY[i]))
simLib.fregstim().write("# DMA\n")
simLib.fregstim().write("N " + "%d\n" % (numExpectedPktsDMA[i]))
simLib.fregstim().write("S " + "%d\n" % (numSendPktsDMA[i]))
resetBarrier()
def barrier():
for i in range(NUM_PORTS): # 0,1,2,3
simLib.fPort(i + 1).write("# BARRIER\n")
simLib.fPort(i + 1).write("B " + "%d\n"%CMD_BARRIER)
simLib.fPort(i + 1).write("# EXPECTED\n")
simLib.fPort(i + 1).write("N " + "%d\n"%(numExpectedPktsPHY[i]))
simLib.fPort(i + 1).write("# SENT\n")
simLib.fPort(i + 1).write("S " + "%d\n\n"%(numSendPktsPHY[i]))
simLib.fDMA().write("# BARRIER\n")
simLib.fDMA().write("B " + "%d\n"%CMD_BARRIER)
simLib.fDMA().write("# EXPECTED\n")
simLib.fDMA().write("N " + "%d\n"%(numExpectedPktsDMA[0]))
simLib.fDMA().write("# SENT\n")
simLib.fDMA().write("S " + "%d\n\n"%(numSendPktsDMA[0]))
simLib.fregstim().write("# BARRIER\n")
simLib.fregstim().write("B " + "%d\n"%CMD_BARRIER_REG)
for i in range(NUM_PORTS):
#if numSendPktsPHY[i] == 0:
# simLib.fregstim().write("")
#else:
#if numExpectedPktsPHY[i] == numSendPktsPHY[i]:
# simLib.fregstim().write("N " + "%d\n"%(numSendPktsPHY[i]))
# simLib.fregstim().write("N " + "%d\n"%(numExpectedPktsPHY[i]))
#else:
simLib.fregstim().write("# Interface " + "%d\n"%(i))
#simLib.fregstim().write("S " + "%d\n"%(numSendPktsPHY[i]))
simLib.fregstim().write("N " + "%d\n"%(numExpectedPktsPHY[i]))
simLib.fregstim().write("S " + "%d\n"%(numSendPktsPHY[i]))
#if numSendPktsDMA[i] == 0:
# simLib.fregstim().write("")
# else:
simLib.fregstim().write("# DMA\n")
#simLib.fregstim().write("S " + "%d\n"%(numSendPktsDMA[i]))
simLib.fregstim().write("N " + "%d\n"%(numExpectedPktsDMA[i]))
simLib.fregstim().write("S " + "%d\n"%(numSendPktsDMA[i]))
#simLib.fregexpect().write("# BARRIER\n")
#simLib.fregexpect().write("B " + "%d\n"%CMD_BARRIER_REG)
resetBarrier()