def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
import sram
debug.info(1, "Testing sample 8bit, 128word SRAM, 2 banks")
a = sram.sram(word_size=8,
num_words=128,
num_banks=2,
name="test_sram1")
OPTS.check_lvsdrc = True
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.nominal_corner_only = False
OPTS.netlist_only = True
from characterizer import lib
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=2,
num_words=16,
num_banks=1)
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing analytical timing for sample 2 bit, 16 words SRAM with 1 bank")
# This doesn't have to use the factory since worst case
# it will just replaece the top-level module of the same name
s = sram(c, name="sram_2_16_1_{0}".format(OPTS.tech_name))
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
#Set the corners. Lib will create a power set of the lists.
if OPTS.tech_name == "scn4m_subm":
OPTS.process_corners = ["TT", "SS", "FF"]
OPTS.supply_voltages = [5.0]
OPTS.temperatures = [25]
elif OPTS.tech_name == "freepdk45":
OPTS.process_corners = ["TT", "SS", "FF"]
OPTS.supply_voltages = [1.0]
OPTS.temperatures = [25]
lib(out_dir=OPTS.openram_temp, sram=s.s, sp_file=tempspice, use_model=True)
# get all of the .lib files generated
files = os.listdir(OPTS.openram_temp)
nametest = re.compile("\.lib$", re.IGNORECASE)
lib_files = filter(nametest.search, files)
# and compare them with the golden model
for filename in lib_files:
newname = filename.replace(".lib","_analytical.lib")
libname = "{0}/{1}".format(OPTS.openram_temp,filename)
golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),newname)
self.assertTrue(self.isapproxdiff(libname,golden,0.15))
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.analytical_delay = False
OPTS.trim_netlist = True
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import lib
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),
-1)
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=2, num_words=16, num_banks=1)
c.words_per_row = 1
debug.info(
1,
"Testing pruned timing for sample 2 bit, 16 words SRAM with 1 bank"
)
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
lib(out_dir=OPTS.openram_temp,
sram=s.s,
sp_file=tempspice,
use_model=False)
# get all of the .lib files generated
files = os.listdir(OPTS.openram_temp)
nametest = re.compile("\.lib$", re.IGNORECASE)
lib_files = filter(nametest.search, files)
# and compare them with the golden model
for filename in lib_files:
newname = filename.replace(".lib", "_pruned.lib")
libname = "{0}/{1}".format(OPTS.openram_temp, filename)
golden = "{0}/golden/{1}".format(
os.path.dirname(os.path.realpath(__file__)), newname)
self.assertTrue(self.isapproxdiff(libname, golden, 0.40))
reload(characterizer)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
OPTS.use_pex = False
import sram
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram.sram(word_size=OPTS.config.word_size,
num_words=OPTS.config.num_words,
num_banks=OPTS.config.num_banks,
name="test_sram1")
OPTS.check_lvsdrc = True
import delay
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.addr_size
probe_data = s.word_size - 1
debug.info(
1,
"Probe address {0} probe data {1}".format(probe_address,
probe_data))
d = delay.delay(s, tempspice)
data = d.analyze(probe_address, probe_data)
if OPTS.tech_name == "freepdk45":
self.assertTrue(isclose(data['delay1'], 0.013649))
self.assertTrue(isclose(data['delay0'], 0.22893))
self.assertTrue(isclose(data['min_period1'], 0.078582763671875))
self.assertTrue(isclose(data['min_period0'], 0.25543212890625))
elif OPTS.tech_name == "scn3me_subm":
self.assertTrue(isclose(data['delay1'], 1.5335))
self.assertTrue(isclose(data['delay0'], 2.2635000000000005))
self.assertTrue(isclose(data['min_period1'], 1.53564453125))
self.assertTrue(isclose(data['min_period0'], 2.998046875))
else:
self.assertTrue(False) # other techs fail
os.remove(tempspice)
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import lib
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=2,
num_words=16,
num_banks=1)
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
# This doesn't have to use the factory since worst case
# it will just replaece the top-level module of the same name
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
lib(out_dir=OPTS.openram_temp, sram=s.s, sp_file=tempspice, use_model=False)
# get all of the .lib files generated
files = os.listdir(OPTS.openram_temp)
nametest = re.compile("\.lib$", re.IGNORECASE)
lib_files = filter(nametest.search, files)
# and compare them with the golden model
for filename in lib_files:
libname = "{0}/{1}".format(OPTS.openram_temp,filename)
golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),filename)
self.assertTrue(self.isapproxdiff(libname,golden,0.40))
reload(characterizer)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4, num_words=16, num_banks=1)
c.words_per_row = 1
c.recompute_sizes()
debug.info(
1,
"Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks"
.format(OPTS.num_rw_ports, OPTS.num_r_ports, OPTS.num_w_ports,
c.word_size, c.num_words, c.words_per_row, c.num_banks))
a = sram(c, "sram")
self.local_check(a, final_verification=True)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.spice_name = "hspice"
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
debug.info(
1, "Trimming disabled for this test. Simulation could be slow.")
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import model_check
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4, num_words=16, num_banks=1)
c.words_per_row = 1
c.recompute_sizes()
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram(c, name="sram1")
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.s.addr_size
probe_data = s.s.word_size - 1
debug.info(
1, "Probe address {0} probe data bit {1}".format(
probe_address, probe_data))
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0],
OPTS.temperatures[0])
mc = model_check(s.s, tempspice, corner)
import tech
loads = [tech.spice["msflop_in_cap"] * 4]
slews = [tech.spice["rise_time"] * 2]
sram_data = mc.analyze(probe_address, probe_data, slews, loads)
#Combine info about port into all data
#debug.info(1,"Data:\n{}".format(wl_data))
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
OPTS.spice_name = "hspice"
OPTS.analytical_delay = False
import characterizer
reload(characterizer)
from characterizer import delay
import sram
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram.sram(word_size=OPTS.config.word_size,
num_words=OPTS.config.num_words,
num_banks=OPTS.config.num_banks,
name="sram_func_test")
OPTS.check_lvsdrc = True
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.addr_size
probe_data = s.word_size - 1
debug.info(
1,
"Probe address {0} probe data {1}".format(probe_address,
probe_data))
d = delay.delay(s, tempspice)
d.set_probe(probe_address, probe_data)
# This will exit if it doesn't find a feasible period
import tech
load = tech.spice["FF_in_cap"] * 4
slew = tech.spice["rise_time"] * 2
feasible_period = d.find_feasible_period(load, slew)
os.remove(tempspice)
OPTS.analytical_delay = True
reload(characterizer)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
OPTS.bitcell = "pbitcell"
# testing layout of bank using pbitcell with 1 RW port (a 6T-cell equivalent)
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
c = sram_config(word_size=4, num_words=16, num_banks=1)
c.words_per_row = 1
debug.info(1, "Single bank, no column mux with control logic")
a = sram(c, "sram1")
self.local_check(a, final_verification=True)
"""
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import functional, delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=32,
num_banks=1)
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Functional test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
f = functional(s.s, tempspice, corner)
d = delay(s.s, tempspice, corner)
feasible_period = self.find_feasible_test_period(d, s.s, f.load, f.slew)
f.num_cycles = 10
(fail, error) = f.run()
self.assertTrue(fail,error)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = False
OPTS.spice_name="" # Unset to use any simulator
OPTS.analytical_delay = False
# This is a hack to reload the characterizer __init__ with the spice version
import characterizer
reload(characterizer)
from characterizer import delay
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
import sram
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram.sram(word_size=OPTS.word_size,
num_words=OPTS.num_words,
num_banks=OPTS.num_banks,
name="sram_func_test")
OPTS.check_lvsdrc = True
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.addr_size
probe_data = s.word_size - 1
debug.info(1, "Probe address {0} probe data {1}".format(probe_address, probe_data))
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
d = delay.delay(s,tempspice,corner)
d.set_probe(probe_address,probe_data)
# This will exit if it doesn't find a feasible period
import tech
load = tech.spice["msflop_in_cap"]*4
slew = tech.spice["rise_time"]*2
feasible_period = d.find_feasible_period(load,slew)
os.remove(tempspice)
OPTS.analytical_delay = True
reload(characterizer)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = False
OPTS.spice_name="" # Unset to use any simulator
OPTS.analytical_delay = False
OPTS.trim_netlist = False
# This is a hack to reload the characterizer __init__ with the spice version
import characterizer
reload(characterizer)
from characterizer import lib
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
import sram
debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram.sram(word_size=2,
num_words=16,
num_banks=1,
name="sram_2_16_1_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = True
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
lib.lib(out_dir=OPTS.openram_temp, sram=s, sp_file=tempspice, use_model=False)
# get all of the .lib files generated
files = os.listdir(OPTS.openram_temp)
nametest = re.compile("\.lib$", re.IGNORECASE)
lib_files = filter(nametest.search, files)
# and compare them with the golden model
for filename in lib_files:
libname = "{0}/{1}".format(OPTS.openram_temp,filename)
golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),filename)
self.isapproxdiff(libname,golden,0.40)
OPTS.analytical_delay = True
OPTS.trim_netlist = True
reload(characterizer)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = False
OPTS.spice_name = "" # Unset to use any simulator
OPTS.analytical_delay = False
OPTS.trim_netlist = False
# This is a hack to reload the characterizer __init__ with the spice version
import characterizer
reload(characterizer)
from characterizer import lib
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),
-1)
import sram
debug.info(
1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram.sram(word_size=2,
num_words=OPTS.num_words,
num_banks=OPTS.num_banks,
name="sram_2_16_1_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = True
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
filename = s.name + ".lib"
libname = OPTS.openram_temp + filename
lib.lib(libname=libname, sram=s, spfile=tempspice, use_model=False)
# let's diff the result with a golden model
golden = "{0}/golden/{1}".format(
os.path.dirname(os.path.realpath(__file__)), filename)
self.isapproxdiff(libname, golden, 0.15)
OPTS.analytical_delay = True
OPTS.trim_netlist = True
reload(characterizer)
globals.end_openram()
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.netlist_only = True
from characterizer import lib
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=2, num_words=16, num_banks=1)
c.words_per_row = 1
c.recompute_sizes()
debug.info(
1,
"Testing analytical timing for sample 2 bit, 16 words SRAM with 1 bank"
)
# This doesn't have to use the factory since worst case
# it will just replaece the top-level module of the same name
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
lib(out_dir=OPTS.openram_temp,
sram=s.s,
sp_file=tempspice,
use_model=True)
# get all of the .lib files generated
files = os.listdir(OPTS.openram_temp)
nametest = re.compile("\.lib$", re.IGNORECASE)
lib_files = filter(nametest.search, files)
# and compare them with the golden model
for filename in lib_files:
newname = filename.replace(".lib", "_analytical.lib")
libname = "{0}/{1}".format(OPTS.openram_temp, filename)
golden = "{0}/golden/{1}".format(
os.path.dirname(os.path.realpath(__file__)), newname)
self.assertTrue(self.isapproxdiff(libname, golden, 0.15))
globals.end_openram()
def runTest(self):
globals.init_AMC("config_20_{0}".format(OPTS.tech_name))
import sram
debug.info(1, "Testing LEF for a sample sram")
s = sram.sram(word_size=4,
words_per_row=1,
num_rows=64,
num_subanks=4,
branch_factors=(1, 4),
bank_orientations=("H", "H"),
name="sram3")
gdsfile = s.name + ".gds"
leffile = s.name + ".lef"
gdsname = OPTS.AMC_temp + gdsfile
lefname = OPTS.AMC_temp + leffile
s.gds_write(gdsname)
s.lef_write(lefname)
globals.end_AMC()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=2, num_words=16, num_banks=1)
c.words_per_row = 1
c.recompute_sizes()
debug.info(
1, "Testing Verilog for sample 2 bit, 16 words SRAM with 1 bank")
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
vfile = s.name + ".v"
vname = OPTS.openram_temp + vfile
s.verilog_write(vname)
# let's diff the result with a golden model
golden = "{0}/golden/{1}".format(
os.path.dirname(os.path.realpath(__file__)), vfile)
self.assertTrue(self.isdiff(vname, golden))
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
import sram
import lib
debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
total_size = 1024
for word_size in [1,2,4,8,16,32,64]:
num_words = total_size/word_size# OPTS.config.num_words
s = sram.sram(word_size=word_size,
num_words=num_words,
num_banks=OPTS.config.num_banks,
name="sram_2_16_1_{0}".format(OPTS.tech_name))
delay = s.analytical_model(0.1)
OPTS.check_lvsdrc = True
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
filename = s.name + ".lib"
libname = OPTS.openram_temp + filename
use_model = True
lib.lib(libname,s,tempspice,use_model)
# let's diff the result with a golden model
golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),filename)
# Randomly decided 10% difference between spice simulators is ok.
if use_model != True:
self.assertEqual(isapproxdiff(libname,golden,0.10),True)
os.system("rm {0}".format(libname))
globals.end_openram()
def runTest(self):
globals.init_AMC("config_20_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = False
import sram
debug.info(1, "Testing Verilog for a sample sram")
s = sram.sram(word_size=2,
words_per_row=1,
num_rows=64,
num_subanks=4,
branch_factors=(1, 4),
bank_orientations=("H", "H"),
name="sram")
OPTS.check_lvsdrc = True
vfile = s.name + ".v"
vname = OPTS.AMC_temp + vfile
s.verilog_write(vname)
globals.end_AMC()
def runTest(self):
globals.init_AMC("config_20_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = False
# This is a hack to reload the characterizer __init__ with the spice version
import characterizer
reload(characterizer)
from characterizer import functional_test
import sram
import tech
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram.sram(word_size=2,
words_per_row=1,
num_rows=32,
num_subanks=2,
branch_factors=(1, 2),
bank_orientations=("H", "H"),
name="sram")
tempspice = OPTS.AMC_temp + "sram.sp"
s.sp_write(tempspice)
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0],
OPTS.temperatures[0])
size = (s.addr_size, s.word_size)
#at least 4 simulation is needed to calculate delays for each operation
T = functional_test.functional_test(size,
corner,
name=s.name,
w_per_row=s.w_per_row,
num_rows=s.num_rows,
load=tech.spice["input_cap"],
slew=tech.spice["rise_time"])
globals.end_AMC()
def runTest(self):
globals.init_AMC("config_20_{0}".format(OPTS.tech_name))
global calibre
import calibre
OPTS.check_lvsdrc = False
import sram
debug.info(1, "SRAM Test")
""" range of acceptable value:
word_size in any number greater than 1
word_per_row in [1, 2, 4]
num_rows in [32, 64, 128, 256, 512]
num_subanks in [1, 2, 4, 8]
# In banch_factor, first num is no. of outter_banks and second num is no. of
inner_banks, e.g (2, 4) means each one of two outter_bank has 4 inner_banks
branch_factors in [(1,1), (1,2), (1,4), (2,4), (4,4)]
# In bank_orientations, first value is orientaion of outter_banks
and second value is orientaion of inner_banks, e.g ("V", "H")
means outter_banks are placed vertically and inner_banks are place horizontally
bank_orientations in [("H", "H"), ("V", "H"), ("H", "V"), ("V", "V")] """
a = sram.sram(word_size=16,
words_per_row=2,
num_rows=64,
num_subanks=4,
branch_factors=(4, 4),
bank_orientations=("H", "H"),
name="sram")
self.local_check(a)
# return it back to it's normal state
OPTS.check_lvsdrc = True
globals.end_AMC()
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
from supply_router import supply_router as router
if False:
from control_logic import control_logic
cell = control_logic(16)
layer_stack = ("metal3", "via3", "metal4")
rtr = router(layer_stack, cell)
self.assertTrue(rtr.route())
else:
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4, num_words=32, num_banks=1)
c.words_per_row = 1
sram = sram(c, "sram1")
cell = sram.s
self.local_check(cell, True)
# fails if there are any DRC errors on any cells
globals.end_openram()
def runTest(self):
globals.init_AMC("config_20_{0}".format(OPTS.tech_name))
global calibre
import calibre
OPTS.check_lvsdrc = False
# Only print banner here so it's not in unit tests
print_banner()
# Output info about this run
report_status()
# Start importing design modules after we have the config file
import tech
import sram
# Keep track of running stats
start_time = datetime.datetime.now()
print_time("Start",start_time)
# import SRAM test generation
s = sram.sram(word_size=OPTS.word_size,
words_per_row=OPTS.words_per_row,
num_rows=OPTS.num_rows,
num_subanks=OPTS.num_subanks,
branch_factors=OPTS.branch_factors,
bank_orientations=OPTS.bank_orientations,
name="sram2")
# return it back to it's normal state
self.local_check(s)
OPTS.check_lvsdrc = True
print_time("End",datetime.datetime.now(), start_time)
globals.end_AMC()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
import sram
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram.sram(word_size=OPTS.config.word_size,
num_words=OPTS.config.num_words,
num_banks=OPTS.config.num_banks,
name="test_sram1")
OPTS.check_lvsdrc = True
import delay
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.addr_size
probe_data = s.word_size - 1
debug.info(
1,
"Probe address {0} probe data {1}".format(probe_address,
probe_data))
d = delay.delay(s, tempspice)
d.set_probe(probe_address, probe_data)
# This will exit if it doesn't find a feasible period
feasible_period = d.find_feasible_period(2.0)
os.remove(tempspice)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
OPTS.analytical_delay = False
OPTS.trim_netlist = False
import characterizer
reload(characterizer)
from characterizer import lib
import sram
debug.info(
1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram.sram(word_size=2,
num_words=OPTS.config.num_words,
num_banks=OPTS.config.num_banks,
name="sram_2_16_1_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = True
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
filename = s.name + ".lib"
libname = OPTS.openram_temp + filename
lib.lib(libname=libname, sram=s, spfile=tempspice, use_model=False)
# let's diff the result with a golden model
golden = "{0}/golden/{1}".format(
os.path.dirname(os.path.realpath(__file__)), filename)
self.assertEqual(isapproxdiff(libname, golden, 0.25), True)
OPTS.analytical_delay = True
OPTS.trim_netlist = True
reload(characterizer)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.spice_name = "ngspice"
OPTS.analytical_delay = False
OPTS.trim_netlist = False
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import delay
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),
-1)
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=1, num_words=16, num_banks=1)
c.words_per_row = 1
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram(c, name="sram1")
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.s.addr_size
probe_data = s.s.word_size - 1
debug.info(
1, "Probe address {0} probe data bit {1}".format(
probe_address, probe_data))
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0],
OPTS.temperatures[0])
d = delay(s.s, tempspice, corner)
import tech
loads = [tech.spice["msflop_in_cap"] * 4]
slews = [tech.spice["rise_time"] * 2]
data = d.analyze(probe_address, probe_data, slews, loads)
if OPTS.tech_name == "freepdk45":
golden_data = {
'delay_hl0': [2.584251],
'delay_lh0': [0.22870469999999998],
'leakage_power': 0.0009567935,
'min_period': 4.844,
'read0_power0': [0.0547588],
'read1_power0': [0.051159970000000006],
'slew_hl0': [0.08164099999999999],
'slew_lh0': [0.025474979999999998],
'write0_power0': [0.06513271999999999],
'write1_power0': [0.058057000000000004]
}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {
'delay_hl0': [3.644147],
'delay_lh0': [1.629815],
'leakage_power': 0.0009299118999999999,
'min_period': 4.688,
'read0_power0': [16.28732],
'read1_power0': [15.75155],
'slew_hl0': [0.6722473],
'slew_lh0': [0.3386347],
'write0_power0': [18.545450000000002],
'write1_power0': [16.81084]
}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(data.keys()) == len(golden_data.keys()))
self.assertTrue(self.check_golden_data(data, golden_data, 0.25))
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.spice_name = "ngspice"
OPTS.analytical_delay = False
OPTS.netlist_only = True
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=1, num_words=16, num_banks=1)
c.words_per_row = 1
c.recompute_sizes()
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram(c, name="sram1")
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.s.addr_size
probe_data = s.s.word_size - 1
debug.info(
1, "Probe address {0} probe data bit {1}".format(
probe_address, probe_data))
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0],
OPTS.temperatures[0])
d = delay(s.s, tempspice, corner)
import tech
loads = [tech.spice["msflop_in_cap"] * 4]
slews = [tech.spice["rise_time"] * 2]
data, port_data = d.analyze(probe_address, probe_data, slews, loads)
#Combine info about port into all data
data.update(port_data[0])
if OPTS.tech_name == "freepdk45":
golden_data = {
'delay_hl': [0.221699],
'delay_lh': [0.221699],
'leakage_power': 0.001467648,
'min_period': 0.605,
'read0_power': [0.3879335],
'read1_power': [0.3662724],
'slew_hl': [0.08562444999999999],
'slew_lh': [0.08562444999999999],
'write0_power': [0.3362456],
'write1_power': [0.3372035]
}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {
'delay_hl': [1.7951730000000001],
'delay_lh': [1.7951730000000001],
'leakage_power': 0.001669513,
'min_period': 3.594,
'read0_power': [17.03022],
'read1_power': [16.55897],
'slew_hl': [0.7079951],
'slew_lh': [0.7079951],
'write0_power': [15.16726],
'write1_power': [16.13527]
}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(data.keys()) == len(golden_data.keys()))
self.assertTrue(self.check_golden_data(data, golden_data, 0.25))
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.spice_name = "ngspice"
OPTS.analytical_delay = False
OPTS.netlist_only = True
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=1, num_words=16, num_banks=1)
c.words_per_row = 1
c.recompute_sizes()
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram(c, name="sram1")
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.s.addr_size
probe_data = s.s.word_size - 1
debug.info(
1, "Probe address {0} probe data bit {1}".format(
probe_address, probe_data))
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0],
OPTS.temperatures[0])
d = delay(s.s, tempspice, corner)
import tech
loads = [tech.spice["msflop_in_cap"] * 4]
slews = [tech.spice["rise_time"] * 2]
data, port_data = d.analyze(probe_address, probe_data, slews, loads)
#Combine info about port into all data
data.update(port_data[0])
if OPTS.tech_name == "freepdk45":
golden_data = {
'delay_bl': [0.2003652],
'delay_br': [0.198698],
'delay_hl': [0.2108836],
'delay_lh': [0.2108836],
'leakage_power': 0.001564799,
'min_period': 0.508,
'read0_power': [0.43916689999999997],
'read1_power': [0.4198608],
'slew_hl': [0.0455126],
'slew_lh': [0.0455126],
'volt_bl': [0.6472883],
'volt_br': [1.114024],
'write0_power': [0.40681890000000004],
'write1_power': [0.4198608]
}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {
'delay_bl': [1.3937359999999999],
'delay_br': [1.2596429999999998],
'delay_hl': [1.5747600000000002],
'delay_lh': [1.5747600000000002],
'leakage_power': 0.00195795,
'min_period': 3.281,
'read0_power': [14.92874],
'read1_power': [14.369810000000001],
'slew_hl': [0.49631959999999997],
'slew_lh': [0.49631959999999997],
'volt_bl': [4.132618],
'volt_br': [5.573099],
'write0_power': [13.79953],
'write1_power': [14.369810000000001]
}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(data.keys()) == len(golden_data.keys()))
self.assertTrue(self.check_golden_data(data, golden_data, 0.25))
globals.end_openram()
debug.info(1, "Output file is " + OPTS.out_name + ".(sp|gds|v|lib|lef)")
print "Technology: %s" % (OPTS.tech_name)
print "Word size: {0}\nWords: {1}\nBanks: {2}".format(word_size, num_words,
num_banks)
# only start importing modules after we have the config file
import calibre
import sram
print "Start: ", datetime.datetime.now()
# import SRAM test generation
s = sram.sram(word_size=word_size,
num_words=num_words,
num_banks=num_banks,
name=OPTS.out_name)
# Measure design area
# Not working?
#cell_size = s.gds.measureSize(s.name)
#print "Area:", cell_size[0] * cell_size[1]
# Output the files for the resulting SRAM
spname = OPTS.out_path + s.name + ".sp"
print "SP: Writing to {0}".format(spname)
s.sp_write(spname)
gdsname = OPTS.out_path + s.name + ".gds"
print "GDS: Writing to {0}".format(gdsname)
def func_test(self, bank_num):
import sram
import tech
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
OPTS.check_lvsdrc = False
OPTS.use_pex = True
s = sram.sram(word_size=OPTS.word_size,
num_words=OPTS.num_words,
num_banks=OPTS.num_banks,
name="test_sram1")
OPTS.check_lvsdrc = True
OPTS.use_pex = False
tempspice = OPTS.openram_temp + "temp.sp"
tempgds = OPTS.openram_temp + "temp.gds"
s.sp_write(tempspice)
s.gds_write(tempgds)
self.assertFalse(verify.run_drc(s.name, tempgds))
self.assertFalse(verify.run_lvs(s.name, tempgds, tempspice))
self.assertFalse(
verify.run_pex(s.name,
tempgds,
tempspice,
output=OPTS.openram_temp + "temp_pex.sp"))
import sp_file
stimulus_file = OPTS.openram_temp + "stimulus.sp"
a_stimulus = sp_file.sp_file(stimulus_file)
self.write_stimulus(a_stimulus)
simulator_file = OPTS.openram_temp + "simulator.sp"
a_simulator = sp_file.sp_file(simulator_file)
self.write_simulator(a_simulator)
result_file = OPTS.openram_temp + "result"
import os
if OPTS.spice_name == "hspice":
cmd = "hspice -mt 2 -i {0} > {1} ".format(simulator_file,
result_file)
else:
cmd = "ngspice -b -i {0} > {1} ".format(simulator_file,
result_file)
os.system(cmd)
import re
sp_result = open(result_file, "r")
contents = sp_result.read()
key = "vr1"
val = re.search(r"{0}(\s*)=(\s*)(\d*(.).*)(\s*)(from)".format(key),
contents)
val = val.group(3)
value1 = float(self.convert_voltage_unit(val))
key = "vr2"
val = re.search(r"{0}(\s*)=(\s*)(\d*(.).*)(\s*)(from)".format(key),
contents)
val = val.group(3)
value2 = float(self.convert_voltage_unit(val))
self.assertTrue(round(value1) > 0.5 * tech.spice["supply_voltage"])
self.assertTrue(round(value2) < 0.5 * tech.spice["supply_voltage"])
OPTS.check_lvsdrc = True
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = False
OPTS.spice_name = "hspice"
OPTS.analytical_delay = False
# This is a hack to reload the characterizer __init__ with the spice version
import characterizer
reload(characterizer)
from characterizer import delay
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),
-1)
import sram
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram.sram(word_size=OPTS.word_size,
num_words=OPTS.num_words,
num_banks=OPTS.num_banks,
name="sram1")
OPTS.check_lvsdrc = True
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.addr_size
probe_data = s.word_size - 1
debug.info(
1,
"Probe address {0} probe data {1}".format(probe_address,
probe_data))
d = delay.delay(s, tempspice)
import tech
loads = [tech.spice["FF_in_cap"] * 4]
slews = [tech.spice["rise_time"] * 2]
data = d.analyze(probe_address, probe_data, slews, loads)
#print data
if OPTS.tech_name == "freepdk45":
golden_data = {
'read1_power': 0.0345742,
'read0_power': 0.03526189999999999,
'write0_power': 0.0270014,
'delay1': [0.0573107],
'delay0': [0.07055809999999998],
'min_period': 0.234,
'write1_power': 0.0376625,
'slew0': [0.0284344],
'slew1': [0.0189185]
}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {
'read1_power': 11.2474,
'read0_power': 11.3148,
'write0_power': 6.9064,
'delay1': [1.0298],
'delay0': [1.4102],
'min_period': 4.063,
'write1_power': 11.6964,
'slew0': [1.3118],
'slew1': [0.9816656]
}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(data.keys()) == len(golden_data.keys()))
# Check each result
for k in data.keys():
if type(data[k]) == list:
for i in range(len(data[k])):
self.isclose(data[k][i], golden_data[k][i], 0.15)
else:
self.isclose(data[k], golden_data[k], 0.15)
# reset these options
OPTS.check_lvsdrc = True
OPTS.analytical_delay = True
reload(characterizer)
globals.end_openram()
