def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.bitcell = "pbitcell" OPTS.replica_bitcell = "replica_pbitcell" OPTS.dummy_bitcell = "dummy_pbitcell" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 debug.info(2, "Testing 4x4 array for pbitcell") a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1]) self.local_check(a) OPTS.bitcell = "pbitcell" OPTS.replica_bitcell = "replica_pbitcell" OPTS.dummy_bitcell = "dummy_pbitcell" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 factory.reset() debug.info(2, "Testing 4x4 array for pbitcell") a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 0], left_rbl=[0]) self.local_check(a) globals.end_openram()
def runTest(self): config_file = "{}/tests/configs/config".format( os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) import replica_pbitcell OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 factory.reset() debug.info(2, "Checking replica bitcell using pbitcell (small cell)") tx = replica_pbitcell.replica_pbitcell(name="rpbc") self.local_check(tx) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 1 factory.reset() debug.info(2, "Checking replica bitcell using pbitcell (large cell)") tx = replica_pbitcell.replica_pbitcell(name="rpbc") self.local_check(tx) globals.end_openram()
def runTest(self): config_file = "{}/tests/configs/config".format( os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # check single level column mux in multi-port OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 1 factory.reset() debug.info(2, "Checking column mux for pbitcell (innermost connections)") tx = factory.create(module_type="column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0") self.local_check(tx) factory.reset() debug.info(2, "Checking column mux for pbitcell (outermost connections)") tx = factory.create(module_type="column_mux", tx_size=8, bitcell_bl="bl2", bitcell_br="br2") self.local_check(tx) globals.end_openram()
def runTest(self): globals.init_openram("config_{0}".format(OPTS.tech_name)) # check precharge array in single port debug.info(2, "Checking 3 column precharge") pc = factory.create(module_type="precharge_array", columns=3) self.local_check(pc) # check precharge array in multi-port OPTS.bitcell = "bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 factory.reset() debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell") pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0") self.local_check(pc) # debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)") # pc = precharge_array.precharge_array(name="pre3", columns=3, bitcell_bl="bl0", bitcell_br="br0") # self.local_check(pc) # debug.info(2, "Checking 3 column precharge array for pbitcell (outermost connections)") # pc = precharge_array.precharge_array(name="pre4", columns=3, bitcell_bl="bl2", bitcell_br="br2") # self.local_check(pc) globals.end_openram()
def runTest(self): globals.init_openram("config_{0}".format(OPTS.tech_name)) # check single level column mux in single port debug.info(2, "Checking column mux") tx = factory.create(module_type="single_level_column_mux", tx_size=8) self.local_check(tx) # check single level column mux in multi-port OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 1 factory.reset() debug.info(2, "Checking column mux for pbitcell (innermost connections)") tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0") self.local_check(tx) factory.reset() debug.info(2, "Checking column mux for pbitcell (outermost connections)") tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl2", bitcell_br="br2") self.local_check(tx) globals.end_openram()
def runTest(self): config_file = "{}/tests/configs/config".format( os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) #check sense amp array for multi-port OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 factory.reset() debug.info( 2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)" ) a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2) self.local_check(a) debug.info( 2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)" ) a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4) self.local_check(a) globals.end_openram()
def runTest(self): config_file = "{}/tests/configs/config".format( os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # check precharge array in multi-port OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 globals.setup_bitcell() factory.reset() debug.info( 2, "Checking 3 column precharge array for 1RW/1R bitcell (port 0)") pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0") self.local_check(pc) debug.info( 2, "Checking 3 column precharge array for 1RW/1R bitcell (port 1)") pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0", column_offset=1) self.local_check(pc) globals.end_openram()
def runTest(self): globals.init_openram("config_{0}".format(OPTS.tech_name)) # check write driver array for single port debug.info(2, "Testing write_driver_array for columns=8, word_size=8") a = factory.create(module_type="write_driver_array", columns=8, word_size=8) self.local_check(a) debug.info(2, "Testing write_driver_array for columns=16, word_size=8") a = factory.create(module_type="write_driver_array", columns=16, word_size=8) self.local_check(a) # check write driver array for multi-port OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 factory.reset() debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)") a = factory.create(module_type="write_driver_array", columns=8, word_size=8) self.local_check(a) debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)") a = factory.create(module_type="write_driver_array", columns=16, word_size=8) self.local_check(a) globals.end_openram()
def runTest(self): config_file = "{}/tests/configs/config".format( os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # check write driver array for multi-port OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 factory.reset() debug.info( 2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)" ) a = factory.create(module_type="write_driver_array", columns=8, word_size=8) self.local_check(a) debug.info( 2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)" ) a = factory.create(module_type="write_driver_array", columns=16, word_size=8) self.local_check(a) globals.end_openram()
def runTest(self): config_file = "{}/tests/configs/config".format( os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # check single level column mux array in multi-port OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 1 factory.reset() debug.info(1, "Testing sample for 2-way column_mux_array in multi-port") a = factory.create(module_type="column_mux_array", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) debug.info(1, "Testing sample for 4-way column_mux_array in multi-port") a = factory.create(module_type="column_mux_array", columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) debug.info( 1, "Testing sample for 8-way column_mux_array in multi-port (innermost connections)" ) a = factory.create(module_type="column_mux_array", columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) debug.info( 1, "Testing sample for 8-way column_mux_array in multi-port (outermost connections)" ) a = factory.create(module_type="column_mux_array", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2", column_offset=3) self.local_check(a) globals.end_openram()
def runTest(self): globals.init_openram("config_{0}".format(OPTS.tech_name)) # Doesn't require hierarchical decoder # debug.info(1, "Testing 4 row sample for hierarchical_decoder") # a = hierarchical_decoder.hierarchical_decoder(name="hd1, rows=4) # self.local_check(a) # Doesn't require hierarchical decoder # debug.info(1, "Testing 8 row sample for hierarchical_decoder") # a = hierarchical_decoder.hierarchical_decoder(name="hd2", rows=8) # self.local_check(a) # check hierarchical decoder for single port debug.info(1, "Testing 16 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", rows=16) self.local_check(a) debug.info(1, "Testing 32 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", rows=32) self.local_check(a) debug.info(1, "Testing 128 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", rows=128) self.local_check(a) debug.info(1, "Testing 512 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", rows=512) self.local_check(a) # check hierarchical decoder for multi-port OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 factory.reset() debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)") a = factory.create(module_type="hierarchical_decoder", rows=16) self.local_check(a) debug.info(1, "Testing 32 row sample for hierarchical_decoder (multi-port case)") a = factory.create(module_type="hierarchical_decoder", rows=32) self.local_check(a) debug.info(1, "Testing 128 row sample for hierarchical_decoder (multi-port case)") a = factory.create(module_type="hierarchical_decoder", rows=128) self.local_check(a) debug.info(1, "Testing 512 row sample for hierarchical_decoder (multi-port case)") a = factory.create(module_type="hierarchical_decoder", rows=512) self.local_check(a) globals.end_openram()
def runTest(self): globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=16, num_words=32, num_banks=2) c.words_per_row = 1 c.recompute_sizes() debug.info( 1, "Layout test for {}rw,{}r,{}w sram " "with {} bit words, {} words, {} words per " "row, {} banks".format(OPTS.num_rw_ports, OPTS.num_r_ports, OPTS.num_w_ports, c.word_size, c.num_words, c.words_per_row, c.num_banks)) factory.reset() a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) c.num_words = 64 c.words_per_row = 2 c.recompute_sizes() debug.info( 1, "Layout test for {}rw,{}r,{}w sram " "with {} bit words, {} words, {} words per " "row, {} banks".format(OPTS.num_rw_ports, OPTS.num_r_ports, OPTS.num_w_ports, c.word_size, c.num_words, c.words_per_row, c.num_banks)) factory.reset() a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) c.num_words = 128 c.words_per_row = 4 c.recompute_sizes() debug.info( 1, "Layout test for {}rw,{}r,{}w sram " "with {} bit words, {} words, {} words per " "row, {} banks".format(OPTS.num_rw_ports, OPTS.num_r_ports, OPTS.num_w_ports, c.word_size, c.num_words, c.words_per_row, c.num_banks)) factory.reset() a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) c.word_size = 2 c.num_words = 256 c.words_per_row = 8 c.recompute_sizes() debug.info( 1, "Layout test for {}rw,{}r,{}w sram " "with {} bit words, {} words, {} words per " "row, {} banks".format(OPTS.num_rw_ports, OPTS.num_r_ports, OPTS.num_w_ports, c.word_size, c.num_words, c.words_per_row, c.num_banks)) factory.reset() a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) globals.end_openram()
def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # check wordline driver for multi-port OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 factory.reset() debug.info(2, "Checking driver (multi-port case)") tx = factory.create(module_type="wordline_driver_array", rows=8, cols=64) self.local_check(tx) globals.end_openram()
def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # check hierarchical decoder for multi-port OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 globals.setup_bitcell() factory.reset() debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)") a = factory.create(module_type="hierarchical_decoder", num_outputs=16) self.local_check(a) factory.reset() debug.info(1, "Testing 17 row sample for hierarchical_decoder (multi-port case)") a = factory.create(module_type="hierarchical_decoder", num_outputs=17) self.local_check(a) factory.reset() debug.info(1, "Testing 23 row sample for hierarchical_decoder (multi-port case)") a = factory.create(module_type="hierarchical_decoder", num_outputs=23) self.local_check(a) debug.info(1, "Testing 32 row sample for hierarchical_decoder (multi-port case)") a = factory.create(module_type="hierarchical_decoder", num_outputs=32) self.local_check(a) factory.reset() debug.info(1, "Testing 65 row sample for hierarchical_decoder (multi-port case)") a = factory.create(module_type="hierarchical_decoder", num_outputs=65) self.local_check(a) debug.info(1, "Testing 128 row sample for hierarchical_decoder (multi-port case)") a = factory.create(module_type="hierarchical_decoder", num_outputs=128) self.local_check(a) factory.reset() debug.info(1, "Testing 341 row sample for hierarchical_decoder (multi-port case)") a = factory.create(module_type="hierarchical_decoder", num_outputs=341) self.local_check(a) debug.info(1, "Testing 512 row sample for hierarchical_decoder (multi-port case)") a = factory.create(module_type="hierarchical_decoder", num_outputs=512) self.local_check(a) globals.end_openram()
def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) import sense_amp_array # check sense amp array for single port debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2") a = sense_amp_array.sense_amp_array(name="sa1", word_size=4, words_per_row=2) self.local_check(a) debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4") a = sense_amp_array.sense_amp_array(name="sa2", word_size=4, words_per_row=4) self.local_check(a) # check sense amp array for multi-port OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 factory.reset() debug.info( 2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)" ) a = sense_amp_array.sense_amp_array(name="sa3", word_size=4, words_per_row=2) self.local_check(a) debug.info( 2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)" ) a = sense_amp_array.sense_amp_array(name="sa4", word_size=4, words_per_row=4) self.local_check(a) globals.end_openram()
def init_openram(config_file, is_unit_test=True): """Initialize the technology, paths, simulators, etc.""" check_versions() debug.info(1,"Initializing OpenRAM...") setup_paths() read_config(config_file, is_unit_test) import_tech() init_paths() from sram_factory import factory factory.reset() setup_bitcell() # Reset the static duplicate name checker for unit tests. import hierarchy_design hierarchy_design.hierarchy_design.name_map=[] global OPTS global CHECKPOINT_OPTS # This is a hack. If we are running a unit test and have checkpointed # the options, load them rather than reading the config file. # This way, the configuration is reloaded at the start of every unit test. # If a unit test fails, we don't have to worry about restoring the old config values # that may have been tested. if is_unit_test and CHECKPOINT_OPTS: OPTS.__dict__ = CHECKPOINT_OPTS.__dict__.copy() return # Import these to find the executables for checkpointing import characterizer import verify # Make a checkpoint of the options so we can restore # after each unit test if not CHECKPOINT_OPTS: CHECKPOINT_OPTS = copy.copy(OPTS)
def runTest(self): config_file = "{}/tests/configs/config".format( os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 globals.setup_bitcell() c = sram_config(word_size=4, num_words=16) c.words_per_row = 1 factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create("port_data", sram_config=c, port=0) self.local_check(a) a = factory.create("port_data", sram_config=c, port=1) self.local_check(a) c.num_words = 32 c.words_per_row = 2 factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create("port_data", sram_config=c, port=0) self.local_check(a) a = factory.create("port_data", sram_config=c, port=1) self.local_check(a) c.num_words = 64 c.words_per_row = 4 factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create("port_data", sram_config=c, port=0) self.local_check(a) a = factory.create("port_data", sram_config=c, port=1) self.local_check(a) c.word_size = 2 c.num_words = 128 c.words_per_row = 8 factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create("port_data", sram_config=c, port=0) self.local_check(a) a = factory.create("port_data", sram_config=c, port=1) self.local_check(a) globals.end_openram()
def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) import precharge import tech # check precharge in single port debug.info(2, "Checking precharge for handmade bitcell") tx = precharge.precharge(name="precharge_driver", size=1) self.local_check(tx) # check precharge in multi-port OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 1 factory.reset() debug.info(2, "Checking precharge for pbitcell (innermost connections)") tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl0", bitcell_br="br0") self.local_check(tx) debug.info(2, "Checking precharge for pbitcell (innermost connections)") tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl1", bitcell_br="br1") self.local_check(tx) debug.info(2, "Checking precharge for pbitcell (outermost connections)") tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl2", bitcell_br="br2") self.local_check(tx) globals.end_openram()
def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # check precharge array in multi-port OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 globals.setup_bitcell() debug.info(2, "Checking precharge for 1rw1r port 0") tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl0", bitcell_br="br0") self.local_check(tx) factory.reset() debug.info(2, "Checking precharge for 1rw1r port 1") tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1") self.local_check(tx) globals.end_openram()
def runTest(self): globals.init_openram("config_{0}".format(OPTS.tech_name)) # check wordline driver for single port debug.info(2, "Checking driver") tx = factory.create(module_type="wordline_driver", rows=8, cols=32) self.local_check(tx) # check wordline driver for multi-port OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 factory.reset() debug.info(2, "Checking driver (multi-port case)") tx = factory.create(module_type="wordline_driver", rows=8, cols=64) self.local_check(tx) globals.end_openram()
def runTest(self): config_file = "{}/tests/configs/config".format( os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "bitcell_1w_1r" OPTS.replica_bitcell = "replica_bitcell_1w_1r" OPTS.dummy_bitcell = "dummy_bitcell_1w_1r" OPTS.num_rw_ports = 0 OPTS.num_r_ports = 1 OPTS.num_w_ports = 1 c = sram_config(word_size=4, num_words=16) c.words_per_row = 1 factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create(module_type="bank", sram_config=c) self.local_check(a) c.num_words = 32 c.words_per_row = 2 factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create(module_type="bank", sram_config=c) self.local_check(a) c.num_words = 64 c.words_per_row = 4 factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create(module_type="bank", sram_config=c) self.local_check(a) c.word_size = 2 c.num_words = 128 c.words_per_row = 8 factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create(module_type="bank", sram_config=c) self.local_check(a) globals.end_openram()
def runTest(self): globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" OPTS.dummy_bitcell="dummy_pbitcell" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 c = sram_config(word_size=4, num_words=16) c.words_per_row=1 factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create(module_type="bank", sram_config=c) self.local_check(a) c.num_words=32 c.words_per_row=2 factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create(module_type="bank", sram_config=c) self.local_check(a) c.num_words=64 c.words_per_row=4 factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create(module_type="bank", sram_config=c) self.local_check(a) c.word_size=2 c.num_words=128 c.words_per_row=8 factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create(module_type="bank", sram_config=c) self.local_check(a) globals.end_openram()
def runTest(self): config_file = "{}/tests/configs/config".format( os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "pbitcell" # testing layout of bank using pbitcell with 1 RW port (a 6T-cell equivalent) OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 c = sram_config(word_size=4, num_words=16) c.num_banks = 2 c.words_per_row = 1 factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create("bank", sram_config=c) self.local_check(a) c.num_words = 32 c.words_per_row = 2 factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create("bank", sram_config=c) self.local_check(a) c.num_words = 64 c.words_per_row = 4 factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create("bank", sram_config=c) self.local_check(a) c.word_size = 2 c.num_words = 128 c.words_per_row = 8 factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create("bank", sram_config=c) self.local_check(a) globals.end_openram()
def runTest(self): globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.bitcell = "pbitcell" OPTS.replica_bitcell = "replica_pbitcell" OPTS.dummy_bitcell = "dummy_pbitcell" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 debug.info(2, "Testing 4x4 array for pbitcell") a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=1, bitcell_ports=[0, 1]) self.local_check(a) OPTS.bitcell = "pbitcell" OPTS.replica_bitcell = "replica_pbitcell" OPTS.dummy_bitcell = "dummy_pbitcell" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 factory.reset() debug.info(2, "Testing 4x4 array for pbitcell") a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=0, bitcell_ports=[0]) self.local_check(a) globals.end_openram()
def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) import replica_bitline stages = 4 fanout = 4 rows = 13 OPTS.bitcell = "bitcell_1rw_1r" OPTS.replica_bitcell = "replica_bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 factory.reset() debug.info( 2, "Testing 1rw 1r RBL with {0} FO4 stages, {1} rows".format( stages, rows)) a = replica_bitline.replica_bitline(name="rbl1", delay_fanout_list=stages * [fanout], bitcell_loads=rows) self.local_check(a) # check replica bitline in pbitcell multi-port OPTS.bitcell = "pbitcell" OPTS.replica_bitcell = "replica_pbitcell" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 factory.reset() debug.info( 2, "Testing RBL pbitcell 1rw with {0} FO4 stages, {1} rows".format( stages, rows)) a = replica_bitline.replica_bitline(name="rbl2", delay_fanout_list=stages * [fanout], bitcell_loads=rows) self.local_check(a) OPTS.num_rw_ports = 1 OPTS.num_w_ports = 1 OPTS.num_r_ports = 1 factory.reset() debug.info( 2, "Testing RBL pbitcell 1rw 1w 1r with {0} FO4 stages, {1} rows". format(stages, rows)) a = replica_bitline.replica_bitline(name="rbl3", delay_fanout_list=stages * [fanout], bitcell_loads=rows) self.local_check(a) globals.end_openram()
def runTest(self): globals.init_openram("config_{0}".format(OPTS.tech_name)) import replica_pbitcell OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 factory.reset() debug.info(2, "Checking replica bitcell using pbitcell (small cell)") tx = replica_pbitcell.replica_pbitcell(name="rpbc") self.local_check(tx) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 1 factory.reset() debug.info(2, "Checking replica bitcell using pbitcell (large cell)") tx = replica_pbitcell.replica_pbitcell(name="rpbc") self.local_check(tx) globals.end_openram()
def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=4, num_words=16, num_spare_cols=3) c.words_per_row=1 factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create("bank", sram_config=c) self.local_check(a) c.num_words=32 c.words_per_row=2 factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create("bank", sram_config=c) self.local_check(a) c.num_words=64 c.words_per_row=4 factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create("bank", sram_config=c) self.local_check(a) c.word_size=2 c.num_words=128 c.words_per_row=8 factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create("bank", sram_config=c) self.local_check(a) globals.end_openram()
def runTest(self): globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, num_words=16) c.words_per_row=1 factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create("bank", sram_config=c) self.local_check(a) c.num_words=32 c.words_per_row=2 factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create("bank", sram_config=c) self.local_check(a) c.num_words=64 c.words_per_row=4 factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create("bank", sram_config=c) self.local_check(a) c.word_size=2 c.num_words=128 c.words_per_row=8 factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create("bank", sram_config=c) self.local_check(a) globals.end_openram()
def runTest(self): config_file = "{}/tests/configs/config".format( os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # check precharge in single port debug.info(2, "Checking precharge for handmade bitcell") tx = factory.create(module_type="precharge", size=1) self.local_check(tx) # check precharge in multi-port OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 1 factory.reset() debug.info(2, "Checking precharge for pbitcell (innermost connections)") tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl0", bitcell_br="br0") self.local_check(tx) factory.reset() debug.info(2, "Checking precharge for pbitcell (innermost connections)") tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1") self.local_check(tx) factory.reset() debug.info(2, "Checking precharge for pbitcell (outermost connections)") tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl2", bitcell_br="br2") self.local_check(tx) globals.end_openram()
def runTest(self): globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, num_words=16) c.words_per_row = 1 factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create("port_data", sram_config=c, port=0) self.local_check(a) c.num_words = 32 c.words_per_row = 2 factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create("port_data", sram_config=c, port=0) self.local_check(a) c.num_words = 64 c.words_per_row = 4 factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create("port_data", sram_config=c, port=0) self.local_check(a) c.word_size = 2 c.num_words = 128 c.words_per_row = 8 factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create("port_data", sram_config=c, port=0) self.local_check(a) OPTS.bitcell = "bitcell_1w_1r" OPTS.num_rw_ports = 0 OPTS.num_r_ports = 1 OPTS.num_w_ports = 1 c.num_words = 16 c.words_per_row = 1 factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create("port_data", sram_config=c, port=0) self.local_check(a) a = factory.create("port_data", sram_config=c, port=1) self.local_check(a) c.num_words = 32 c.words_per_row = 2 factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create("port_data", sram_config=c, port=0) self.local_check(a) a = factory.create("port_data", sram_config=c, port=1) self.local_check(a) c.num_words = 64 c.words_per_row = 4 factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create("port_data", sram_config=c, port=0) self.local_check(a) a = factory.create("port_data", sram_config=c, port=1) self.local_check(a) c.word_size = 2 c.num_words = 128 c.words_per_row = 8 factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create("port_data", sram_config=c, port=0) self.local_check(a) a = factory.create("port_data", sram_config=c, port=1) self.local_check(a) globals.end_openram()