Exemple #1
0
def main(args):
    print('\nStarting SST FooProjBar')

    # Makes dummys and sets parameters.
    dummys = []
    for dummy_id in range(args.num_dummys):
        dummy = sst.Component('Dummy_{}'.format(dummy_id), 'fooprojbar.Dummy')
        dummy.addParam('num_dummys', args.num_dummys)
        if args.initial_events != None:
            dummy.addParam('initial_events', args.initial_events)
        if args.total_events != None:
            dummy.addParam('total_events', args.total_events)
        dummys.append(dummy)

    # Connects all dummys to all other dummys via links.
    port_nums = [0] * args.num_dummys
    for dummy_a in range(args.num_dummys):
        for dummy_b in range(dummy_a + 1, args.num_dummys):
            assert dummy_a < dummy_b
            link_name = 'link_{}_{}'.format(dummy_a, dummy_b)
            link = sst.Link(link_name, '1ns')
            link.connect(
                (dummys[dummy_a], 'port_{}'.format(port_nums[dummy_a])),
                (dummys[dummy_b], 'port_{}'.format(port_nums[dummy_b])))
            port_nums[dummy_a] += 1
            port_nums[dummy_b] += 1

    # Limits the verbosity of statistics to any with a load level from 0-7.
    sst.setStatisticLoadLevel(7)

    # Determines where statistics should be sent.
    sst.setStatisticOutput('sst.statOutputCSV')
    sst.setStatisticOutputOption('filepath', args.stats_file)

    # Enables statistics on both dummys.
    sst.enableAllStatisticsForComponentType('fooprojbar.Dummy')
Exemple #2
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    "debug_level": 10,
    "backing": "none",
    "backend.access_time": "50ns",
    "clock": "1GHz",
    "backend.mem_size": "512MiB",
    "memNIC.network_bw": "50GB/s",
    "memNIC.network_address": 3,
    "memNIC.addr_range_start": 128,
    "memNIC.interleave_size": "128B",
    "memNIC.interleave_step": "256B"
})

# Enable statistics
sst.setStatisticLoadLevel(7)
sst.setStatisticOutput("sst.statOutputConsole")
sst.enableAllStatisticsForComponentType("memHierarchy.Scratchpad")
sst.enableAllStatisticsForComponentType("memHierarchy.MemController")

# Define the simulation links
link_cpu0_l1 = sst.Link("link_cpu0_l1")
link_cpu0_l1.connect((comp_cpu0, "mem_link", "100ps"),
                     (comp_l1_0, "high_network_0", "100ps"))
link_cpu1_l1 = sst.Link("link_cpu1_l1")
link_cpu1_l1.connect((comp_cpu1, "mem_link", "100ps"),
                     (comp_l1_1, "high_network_0", "100ps"))
link_l1_scratch0 = sst.Link("link_cpu0_scratch0")
link_l1_scratch0.connect((comp_l1_0, "low_network_0", "100ps"),
                         (comp_scratch0, "cpu", "100ps"))
link_l1_scratch1 = sst.Link("link_cpu1_scratch1")
link_l1_scratch1.connect((comp_l1_1, "low_network_0", "100ps"),
                         (comp_scratch1, "cpu", "100ps"))
      #"debug_level" : 10,
      "backing" : "none",
      "backend.access_time" : "50ns",
      "clock" : "1GHz",
      "backend.mem_size" : "512MiB",
      "memNIC.network_bw" : "50GB/s",
      "memNIC.network_address" : 3,
      "memNIC.addr_range_start" : 128,
      "memNIC.interleave_size" : "128B",
      "memNIC.interleave_step" : "256B"
})

# Enable statistics
sst.setStatisticLoadLevel(7)
sst.setStatisticOutput("sst.statOutputConsole")
sst.enableAllStatisticsForComponentType("memHierarchy.Scratchpad")
sst.enableAllStatisticsForComponentType("memHierarchy.MemController")


# Define the simulation links
link_cpu0_l1 = sst.Link("link_cpu0_l1")
link_cpu0_l1.connect( (comp_cpu0, "mem_link", "100ps"), (comp_l1_0, "high_network_0", "100ps") )
link_cpu1_l1 = sst.Link("link_cpu1_l1")
link_cpu1_l1.connect( (comp_cpu1, "mem_link", "100ps"), (comp_l1_1, "high_network_0", "100ps") )
link_l1_l2_0 = sst.Link("link_l1_l2_0")
link_l1_l2_0.connect( (comp_l1_0, "low_network_0", "100ps"), (comp_l2_0, "high_network_0", "100ps") )
link_l1_l2_1 = sst.Link("link_l1_l2_1")
link_l1_l2_1.connect( (comp_l1_1, "low_network_0", "100ps"), (comp_l2_1, "high_network_0", "100ps") )
link_l2_scratch0 = sst.Link("link_cpu0_scratch0")
link_l2_scratch0.connect( (comp_l2_0, "low_network_0", "100ps"), (comp_scratch0, "cpu", "100ps") )
link_l2_scratch1 = sst.Link("link_cpu1_scratch1")
Exemple #4
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    "backend": "memHierarchy.simpleDRAM",
    "clock": "1GHz",
    "max_requests_per_cycle": 1,
    "backing": "none",
    "backend.tCAS": 3,  # 11@800MHz roughly coverted to 200MHz
    "backend.tRCD": 3,
    "backend.tRP": 3,
    "backend.cycle_time": "5ns",
    "backend.row_size": "8KiB",
    "backend.row_policy": "open"
})

# Enable statistics
sst.setStatisticLoadLevel(7)
sst.setStatisticOutput("sst.statOutputConsole")
sst.enableAllStatisticsForComponentType("memHierarchy.Cache")
sst.enableAllStatisticsForComponentType("memHierarchy.MemController")
sst.enableAllStatisticsForComponentType("memHierarchy.DirectoryController")

# Define the simulation links
link_c0_l1cache = sst.Link("link_c0_l1cache")
link_c0_l1cache.connect((comp_cpu0, "mem_link", "1000ps"),
                        (comp_c0_l1cache, "high_network_0", "1000ps"))
link_c0L1cache_bus = sst.Link("link_c0L1cache_bus")
link_c0L1cache_bus.connect((comp_c0_l1cache, "low_network_0", "10000ps"),
                           (comp_n0_bus, "high_network_0", "10000ps"))
link_c1_l1cache = sst.Link("link_c1_l1cache")
link_c1_l1cache.connect((comp_cpu1, "mem_link", "1000ps"),
                        (comp_c1_l1cache, "high_network_0", "1000ps"))
link_c1L1cache_bus = sst.Link("link_c1L1cache_bus")
link_c1L1cache_bus.connect((comp_c1_l1cache, "low_network_0", "10000ps"),
Exemple #5
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      "debug" : "0"
})
comp_memory = sst.Component("memory", "memHierarchy.MemController")
comp_memory.addParams({
      "coherence_protocol" : "MSI",
      "debug" : "0",
      "backend.mem_size" : "512",
      "printStats" : "1",
      "clock" : "1GHz",
      "backend.access_time" : "100 ns"
})

# Enable statistics
sst.setStatisticLoadLevel(7)
sst.setStatisticOutput("sst.statOutputConsole")
sst.enableAllStatisticsForComponentType("memHierarchy.Cache")
sst.enableAllStatisticsForComponentType("memHierarchy.MemController")


# Define the simulation links
link_cpu0_l1cache_link = sst.Link("link_cpu0_l1cache_link")
link_cpu0_l1cache_link.connect( (comp_cpu0, "mem_link", "1000ps"), (comp_c0_l1cache, "high_network_0", "1000ps") )
link_c0_l1_l2_link = sst.Link("link_c0_l1_l2_link")
link_c0_l1_l2_link.connect( (comp_c0_l1cache, "low_network_0", "1000ps"), (comp_bus, "high_network_0", "10000ps") )
link_cpu1_l1cache_link = sst.Link("link_cpu1_l1cache_link")
link_cpu1_l1cache_link.connect( (comp_cpu1, "mem_link", "1000ps"), (comp_c1_l1cache, "high_network_0", "1000ps") )
link_c1_l1_l2_link = sst.Link("link_c1_l1_l2_link")
link_c1_l1_l2_link.connect( (comp_c1_l1cache, "low_network_0", "1000ps"), (comp_bus, "high_network_1", "10000ps") )
link_bus_l2cache = sst.Link("link_bus_l2cache")
link_bus_l2cache.connect( (comp_bus, "low_network_0", "10000ps"), (comp_l2cache, "high_network_0", "1000ps") )
link_mem_bus_link = sst.Link("link_mem_bus_link")
Exemple #6
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memory = memreorder.setSubComponent("backend", "memHierarchy.simpleDRAM")
memory.addParams({
    "mem_size": "512MiB",
    "tCAS": 3,  # 11@800MHz roughly coverted to 200MHz
    "tRCD": 3,
    "tRP": 3,
    "cycle_time": "5ns",
    "row_size": "8KiB",
    "row_policy": "open"
})

# Enable statistics
sst.setStatisticLoadLevel(7)
sst.setStatisticOutput("sst.statOutputConsole")
for a in componentlist:
    sst.enableAllStatisticsForComponentType(a)

# Define the simulation links
link_c0_l1cache = sst.Link("link_c0_l1cache")
link_c0_l1cache.connect((iface0, "port", "100ps"),
                        (comp_c0_l1cache, "high_network_0", "100ps"))
link_c0L1cache_bus = sst.Link("link_c0L1cache_bus")
link_c0L1cache_bus.connect((comp_c0_l1cache, "low_network_0", "200ps"),
                           (comp_n0_bus, "high_network_0", "200ps"))
link_c1_l1cache = sst.Link("link_c1_l1cache")
link_c1_l1cache.connect((iface1, "port", "100ps"),
                        (comp_c1_l1cache, "high_network_0", "100ps"))
link_c1L1cache_bus = sst.Link("link_c1L1cache_bus")
link_c1L1cache_bus.connect((comp_c1_l1cache, "low_network_0", "100ps"),
                           (comp_n0_bus, "high_network_1", "200ps"))
link_bus_n0L2cache = sst.Link("link_bus_n0L2cache")
Exemple #7
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    "L1": "1",
    "cache_size": "%dKiB" % options.cacheSz
})

comp_memctrl = sst.Component("memory", "memHierarchy.MemController")
comp_memctrl.addParams({
    "debug": 0,
    "debug_level": 10,
    "backing": "malloc",
    "clock": "1GHz",
    "addr_range_start": 0,
})
memory = comp_memctrl.setSubComponent("backend", "memHierarchy.simpleMem")
memory.addParams({
    "mem_size": "512MiB",
    "access_time": "200 ns",
})

# Enable statistics
sst.setStatisticLoadLevel(7)
sst.setStatisticOutput("sst.statOutputConsole")
sst.enableAllStatisticsForComponentType("memHierarchy.Cache")

# Define the simulation links
link_gna_cache = sst.Link("link_gna_mem")
link_gna_cache.connect((comp_gna, "mem_link", "1000ps"),
                       (comp_l1cache, "high_network_0", "1000ps"))
link_mem_bus_link = sst.Link("link_mem_bus_link")
link_mem_bus_link.connect((comp_l1cache, "low_network_0", "50ps"),
                          (comp_memctrl, "direct_link", "50ps"))
component1.addParams(params1)

### Enable statistics
## Limit the verbosity of statistics to any with a load level from 0-4
# This component's statistics range from 1-4 (see sst-info)
sst.setStatisticLoadLevel(4)

## Determine where statistics should be sent. By default this script uses CSV, other options are
# commented out below. Output locations are case-insensitive (e.g., statOutputCSV = statoutputcsv).

# Default: Output to CSV. Filename and seperator can be specified
sst.setStatisticOutput("sst.statOutputCSV", {
    "filepath": "./basicStatistics0.csv",
    "seperator": ","
})

# Option: Output to the terminal
#sst.setStatisticOutput("sst.statoutputconsole")

# Option: Output to a text file
#sst.setStatisticOutput("sst.statOutputTXT", { "filepath" : "./basicStatistics0.txt" } )

# Option: Output to HDF5. Requires sst-core to be configured with HDF5 library.
#sst.setStatisticOutput("sst.statoutputhd5f")

# Option: Output to JSON
#sst.setStatisticOutput("sst.statOutputJSON", { "filepath" : "./basicStatistics0.json" } )

## Enable statistics on the components
sst.enableAllStatisticsForComponentType("simpleElementExample.basicStatistics")
Exemple #9
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            print "[ %d ]  %s" % (x, y)
        output = int(raw_input())
        if output not in statoutputs:
            print "Bad answer.  try again."
            sys.exit(1)
        
        sst.setStatisticOutput(statoutputs[output]);
        if (output != 1):
            print "Filename for stats output:"
            filename = raw_input()
            sst.setStatisticOutputOptions({
                    "filepath" : filename,
                    "separator" : ", "
                    })

        endPoint.enableAllStatistics(rate)


    topo.prepParams()
    endPoint.prepParams()
    topo.setEndPoint(endPoint)
    topo.build()

    if ( stats != 0 ):
        sst.enableAllStatisticsForComponentType("merlin.hr_router", {"type":"sst.AccumulatorStatistic",
                                                                     "rate":rate});
        #stats.append("port%d_send_bit_count"%l)
        #stats.append("port%d_send_packet_count"%l)
        #stats.append("port%d_xbar_stalls"%l)

            print "[ %d ]  %s" % (x, y)
        output = int(raw_input())
        if output not in statoutputs:
            print "Bad answer.  try again."
            sys.exit(1)

        sst.setStatisticOutput(statoutputs[output])
        if (output != 1):
            print "Filename for stats output:"
            filename = raw_input()
            sst.setStatisticOutputOptions({
                "filepath": filename,
                "separator": ", "
            })

        endPoint.enableAllStatistics(rate)

    topo.prepParams()
    endPoint.prepParams()
    topo.setEndPoint(endPoint)
    topo.build()

    if (stats != 0):
        sst.enableAllStatisticsForComponentType("merlin.hr_router", {
            "type": "sst.AccumulatorStatistic",
            "rate": rate
        })
        #stats.append("port%d_send_bit_count"%l)
        #stats.append("port%d_send_packet_count"%l)
        #stats.append("port%d_xbar_stalls"%l)
Exemple #11
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        for z in range(num_endpoints):
            rtr.addLink(
                getLink("rtr_%d_%d" % (x, y), "ep%d_%d_%d" % (z, x, y)),
                "local%d" % (z), "800ps")
            if add_no_cut:
                getLink("rtr_%d_%d" % (x, y),
                        "ep%d_%d_%d" % (z, x, y)).setNoCut()
            ep = sst.Component("ep%d_%d_%d" % (z, x, y), "merlin.test_nic")
            ep.addParams({
                "num_peers": num_peers,
                "link_bw": "1GB/s",
                "linkcontrol_type": "kingsley.linkcontrol",
                "message_size": msg_size,
                "num_messages": "%d" % (num_messages)
            })
            sub = ep.setSubComponent("networkIF", "kingsley.linkcontrol")
            sub.addParam("link_bw", "1GB/s")
            sub.addLink(
                getLink("rtr_%d_%d" % (x, y), "ep%d_%d_%d" % (z, x, y)),
                "rtr_port", "800ps")

sst.setStatisticLoadLevel(9)

sst.setStatisticOutput("sst.statOutputCSV")
sst.setStatisticOutputOptions({"filepath": "stats.csv", "separator": ", "})

sst.enableAllStatisticsForComponentType("kingsley.noc_mesh", {
    "type": "sst.AccumulatorStatistic",
    "rate": "0ns"
})
Exemple #12
0
component0 = sst.Component("c0", "simpleElementExample.example1")
component1 = sst.Component("c1", "simpleElementExample.example1")

### Parameterize the components.
# Run 'sst-info simpleElementExample.example0' at the command line
# to see parameter documentation
params = {
    "eventsToSend": 50,  # Required parameter, error if not provided
    "eventSize": 32  # Optional parameter, defaults to 16 if not provided
}
component0.addParams(params)
component1.addParams(params)

### Link the components via their 'port' ports
link = sst.Link("component_link")
link.connect((component0, "port", "1ns"), (component1, "port", "1ns"))

### Enable statistics
# Limit the verbosity of statistics to any with a load level from 0-7
sst.setStatisticLoadLevel(7)

# Determine where statistics should be sent
sst.setStatisticOutput("sst.statOutputConsole")

# Enable statistics on both components
sst.enableAllStatisticsForComponentType("simpleElementExample.example1")

# Because the link latency is ~1ns and the components send one event
# per cycle on a 1GHz clock, the simulation time should be just over eventsToSend ns
# The statistics output will change if eventSize is changed.
            })
            ep.addLink(getLink("rtr.%d.%d"%(x-1,y), "ep0.%d.%d"%(x,y)), "rtr", "800ps")


        # Add endpoints
        for z in xrange(num_endpoints):
            rtr.addLink(getLink("rtr.%d.%d"%(x,y), "ep%d.%d.%d"%(z,x,y)), "local%d"%(z), "800ps")
            if add_no_cut:
                getLink("rtr.%d.%d"%(x,y), "ep%d.%d.%d"%(z,x,y)).setNoCut()
            ep = sst.Component("ep%d.%d.%d"%(z,x,y), "merlin.test_nic")
            ep.addParams({
                "num_peers" : num_peers,
                "link_bw" : "1GB/s",
                "linkcontrol_type" : "kingsley.linkcontrol",
                "message_size" : msg_size,
                "num_messages" : "%d"%(num_messages)
                
            })
            ep.addLink(getLink("rtr.%d.%d"%(x,y), "ep%d.%d.%d"%(z,x,y)), "rtr", "800ps")


sst.setStatisticLoadLevel(9)

sst.setStatisticOutput("sst.statOutputCSV");
sst.setStatisticOutputOptions({
    "filepath" : "stats.csv",
    "separator" : ", "
})

sst.enableAllStatisticsForComponentType("kingsley.noc_mesh", {"type":"sst.AccumulatorStatistic","rate":"0ns"})
Exemple #14
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        link = sst.Link("mem_link_" + str(next_memory_ctrl_id))
        link.connect((mem, "direct_link", params.link_latency),
                     (dc, "memory", params.link_latency))

        link = sst.Link("dc_link_" + str(next_memory_ctrl_id))
        link.connect((dc, "network", params.link_latency),
                     (router_map["rtr." + str(next_network_id)], "port2",
                      params.link_latency))

        next_network_id = next_network_id + 1
        next_memory_ctrl_id = next_memory_ctrl_id + 1

# Enable SST Statistics Outputs for this simulation
sst.setStatisticLoadLevel(4)
sst.enableAllStatisticsForAllComponents({"type": "sst.AccumulatorStatistic"})
sst.enableAllStatisticsForComponentType("macsimComponent.macsimComponent")
sst.enableAllStatisticsForComponentType("memHierarchy.Cache")
sst.enableAllStatisticsForComponentType("memHierarchy.MemController")

sst.setStatisticOutput("sst.statOutputCSV")
sst.setStatisticOutputOptions({
    "filepath": "sst-ring.stat.csv",
    "separator": ",",
    "outputtopheader": 1,
    "outputsimtime": 1,
    "outputrank": 1
})

print "Completed configuring ring topology"
    "backend.tCAS" : 3,
    "backend.tRCD" : 3,
    "backend.tRP" : 3,
    "backend.cycle_time" : "5ns",
    "backend.row_size" : "8KiB",
    "backend.row_policy" : "closed",
    "memNIC.network_address" : "2",
    "memNIC.network_bw" : "25GB/s",
    "memNIC.network_input_buffer_size" : "2KiB",
    "memNIC.network_output_buffer_size" : "2KiB",
})

# Enable statistics
sst.setStatisticLoadLevel(7)
sst.setStatisticOutput("sst.statOutputConsole")
sst.enableAllStatisticsForComponentType("memHierarchy.Cache")
sst.enableAllStatisticsForComponentType("memHierarchy.MemController")
sst.enableAllStatisticsForComponentType("memHierarchy.DirectoryController")
sst.enableAllStatisticsForComponentType("memHierarchy.simpleDRAM")


# Define the simulation links
link_c0_l1cache = sst.Link("link_c0_l1cache")
link_c0_l1cache.connect( (comp_cpu0, "mem_link", "1000ps"), (comp_c0_l1cache, "high_network_0", "1000ps") )
link_c0L1cache_bus = sst.Link("link_c0L1cache_bus")
link_c0L1cache_bus.connect( (comp_c0_l1cache, "low_network_0", "10000ps"), (comp_n0_bus, "high_network_0", "10000ps") )
link_c1_l1cache = sst.Link("link_c1_l1cache")
link_c1_l1cache.connect( (comp_cpu1, "mem_link", "1000ps"), (comp_c1_l1cache, "high_network_0", "1000ps") )
link_c1L1cache_bus = sst.Link("link_c1L1cache_bus")
link_c1L1cache_bus.connect( (comp_c1_l1cache, "low_network_0", "10000ps"), (comp_n0_bus, "high_network_1", "10000ps") )
link_bus_n0L2cache = sst.Link("link_bus_n0L2cache")