def write_stimulus(self, period, load, slew):
"""Creates a stimulus file for simulations to probe a certain bitcell, given an address and data-position of the data-word
(probe-address form: '111010000' LSB=0, MSB=1)
(probe_data form: number corresponding to the bit position of data-bus, begins with position 0)
"""
self.check_arguments()
# obtains list of time-points for each rising clk edge
self.obtain_cycle_times(period)
# creates and opens stimulus file for writing
temp_stim = "{0}/stim.sp".format(OPTS.openram_temp)
self.sf = open(temp_stim, "w")
self.sf.write(
"* Stimulus for period of {0}n load={1} slew={2}\n\n".format(
period, load, slew))
# include files in stimulus file
model_list = tech.spice["fet_models"] + [self.sram_sp_file]
stimuli.write_include(stim_file=self.sf, models=model_list)
# add vdd/gnd statements
self.sf.write("* Global Power Supplies\n")
stimuli.write_supply(self.sf)
# instantiate the sram
self.sf.write("* Instantiation of the SRAM\n")
stimuli.inst_sram(stim_file=self.sf,
abits=self.addr_size,
dbits=self.word_size,
sram_name=self.name)
self.sf.write("* SRAM output loads\n")
for i in range(self.word_size):
self.sf.write("CD{0} D[{0}] 0 {1}f\n".format(i, load))
# add access transistors for data-bus
self.sf.write(
"* Transmission Gates for data-bus and control signals\n")
stimuli.inst_accesstx(stim_file=self.sf, dbits=self.word_size)
# generate data and addr signals
self.sf.write("* Generation of data and address signals\n")
for i in range(self.word_size):
if i == self.probe_data:
stimuli.gen_data(stim_file=self.sf,
clk_times=self.cycle_times,
sig_name="DATA[{0}]".format(i),
period=period,
slew=slew)
else:
stimuli.gen_constant(stim_file=self.sf,
sig_name="D[{0}]".format(i),
v_val=self.gnd)
stimuli.gen_addr(self.sf,
clk_times=self.cycle_times,
addr=self.probe_address,
period=period,
slew=slew)
# generate control signals
self.sf.write("* Generation of control signals\n")
stimuli.gen_csb(self.sf, self.cycle_times, period, slew)
stimuli.gen_web(self.sf, self.cycle_times, period, slew)
stimuli.gen_oeb(self.sf, self.cycle_times, period, slew)
self.sf.write("* Generation of global clock signal\n")
stimuli.gen_pulse(stim_file=self.sf,
sig_name="CLK",
v1=self.gnd,
v2=self.vdd,
offset=period,
period=period,
t_rise=slew,
t_fall=slew)
self.write_measures(period)
# run until the last cycle time
stimuli.write_control(self.sf, self.cycle_times[-1])
self.sf.close()
def write_stimulus(self, feasible_period, target_period, data_value):
"""Creates a stimulus file for simulations to probe a certain bitcell, given an address and data-position of the data-word
(probe-address form: '111010000' LSB=0, MSB=1)
(probe_data form: number corresponding to the bit position of data-bus, begins with position 0)
"""
self.check_arguments()
# obtains list of time-points for each rising clk edge
self.obtain_cycle_times(slow_period=feasible_period,
fast_period=target_period)
# creates and opens stimulus file for writing
temp_stim = "{0}/stim.sp".format(OPTS.openram_temp)
self.sf = open(temp_stim, "w")
self.sf.write(
"* Stimulus data value of {0} for target period of {1}n\n".format(
data_value, target_period))
self.sf.write("\n")
# include files in stimulus file
model_list = tech.spice["fet_models"] + [self.sram_sp_file]
stimuli.write_include(stim_file=self.sf, models=model_list)
self.sf.write("\n")
# add vdd/gnd statements
self.sf.write("* Global Power Supplies\n")
stimuli.write_supply(stim_file=self.sf,
vdd_name=tech.spice["vdd_name"],
gnd_name=tech.spice["gnd_name"],
vdd_voltage=tech.spice["supply_voltage"],
gnd_voltage=tech.spice["gnd_voltage"])
self.sf.write("\n")
# instantiate the sram
self.sf.write("* Instantiation of the SRAM\n")
stimuli.inst_sram(stim_file=self.sf,
abits=self.addr_size,
dbits=self.word_size,
sram_name=self.name)
self.sf.write("\n")
# create a buffer and an inverter
self.sf.write("* Buffers and inverter Initialization\n")
# FIXME: We should replace the clock buffer with the same
# 2x buffer for control signals. This needs the buffer to be
# added to the control logic though.
stimuli.create_buffer(stim_file=self.sf,
buffer_name="clk1_buffer",
size=[1, 4])
self.sf.write("\n")
stimuli.create_buffer(stim_file=self.sf,
buffer_name="clk2_buffer",
size=[8, 16])
self.sf.write("\n")
stimuli.create_buffer(stim_file=self.sf,
buffer_name="buffer",
size=[1, 2])
self.sf.write("\n")
stimuli.create_inverter(stim_file=self.sf)
self.sf.write("\n")
# add a buffer for each signal and an inverter for WEb
signal_list = []
for i in range(self.word_size):
signal_list.append("D[{0}]".format(i))
for j in range(self.addr_size):
signal_list.append("A[{0}]".format(j))
for k in tech.spice["control_signals"]:
signal_list.append(k)
self.sf.write("*Buffers for each generated signal and Inv for WEb\n")
stimuli.add_buffer(stim_file=self.sf,
buffer_name="buffer",
signal_list=signal_list)
stimuli.add_buffer(stim_file=self.sf,
buffer_name="clk1_buffer",
signal_list=["clk"])
stimuli.add_buffer(stim_file=self.sf,
buffer_name="clk2_buffer",
signal_list=["clk_buf"])
stimuli.add_buffer(stim_file=self.sf,
buffer_name="buffer",
signal_list=["WEb_trans"])
stimuli.add_inverter(stim_file=self.sf, signal_list=["WEb_trans"])
self.sf.write("\n")
# add access transistors for data-bus
self.sf.write("* Transmission Gates for data-bus\n")
stimuli.add_accesstx(stim_file=self.sf, dbits=self.word_size)
self.sf.write("\n")
# generate data and addr signals
self.sf.write("*Generation of data and address signals\n")
if data_value == tech.spice["supply_voltage"]:
v_val = tech.spice["gnd_voltage"]
else:
v_val = tech.spice["supply_voltage"]
for i in range(self.word_size):
if i == self.probe_data:
stimuli.gen_data_pwl(stim_file=self.sf,
key_times=self.cycle_times,
sig_name="D[{0}]".format(i),
data_value=data_value,
feasible_period=feasible_period,
target_period=target_period,
t_rise=tech.spice["rise_time"],
t_fall=tech.spice["fall_time"])
else:
stimuli.gen_constant(stim_file=self.sf,
sig_name="D[{0}]".format(i),
v_ref=tech.spice["gnd_voltage"],
v_val=v_val)
stimuli.gen_addr_pwl(stim_file=self.sf,
key_times=self.cycle_times,
addr=self.probe_address,
feasible_period=feasible_period,
target_period=target_period,
t_rise=tech.spice["rise_time"],
t_fall=tech.spice["fall_time"])
self.sf.write("\n")
# generate control signals
self.sf.write("*Generation of control signals\n")
# CSb
(x_list, y_list) = stimuli.gen_csb_pwl(key_times=self.cycle_times,
feasible_period=feasible_period,
target_period=target_period,
t_rise=tech.spice["rise_time"],
t_fall=tech.spice["fall_time"])
stimuli.gen_pwl(stim_file=self.sf,
sig_name="CSb",
x_list=x_list,
y_list=y_list)
# WEb
(x_list, y_list) = stimuli.gen_web_pwl(key_times=self.cycle_times,
feasible_period=feasible_period,
target_period=target_period,
t_rise=tech.spice["rise_time"],
t_fall=tech.spice["fall_time"])
stimuli.gen_pwl(stim_file=self.sf,
sig_name="WEb",
x_list=x_list,
y_list=y_list)
# OEb
(x_list, y_list) = stimuli.gen_oeb_pwl(key_times=self.cycle_times,
feasible_period=feasible_period,
target_period=target_period,
t_rise=tech.spice["rise_time"],
t_fall=tech.spice["fall_time"])
stimuli.gen_pwl(stim_file=self.sf,
sig_name="OEb",
x_list=x_list,
y_list=y_list)
# WEb_transmission_gate
(x_list,
y_list) = stimuli.gen_web_trans_pwl(key_times=self.cycle_times,
feasible_period=feasible_period,
target_period=target_period,
t_rise=tech.spice["rise_time"],
t_fall=tech.spice["fall_time"])
stimuli.gen_pwl(stim_file=self.sf,
sig_name="WEb_trans",
x_list=x_list,
y_list=y_list)
self.sf.write("\n")
self.write_clock()
self.write_measures(data_value)
self.write_control()
self.sf.close()
def write_stimulus(self, period, load, slew):
""" Creates a stimulus file for simulations to probe a bitcell at a given clock period.
Address and bit were previously set with set_probe().
Input slew (in ns) and output capacitive load (in fF) are required for charaterization.
"""
self.check_arguments()
# obtains list of time-points for each rising clk edge
self.obtain_cycle_times(period)
# creates and opens stimulus file for writing
temp_stim = "{0}/stim.sp".format(OPTS.openram_temp)
self.sf = open(temp_stim, "w")
self.sf.write("* Stimulus for period of {0}n load={1}fF slew={2}ns\n\n".format(period,load,slew))
# include files in stimulus file
model_list = tech.spice["fet_models"] + [self.sram_sp_file]
stimuli.write_include(stim_file=self.sf, models=model_list)
# add vdd/gnd statements
self.sf.write("\n* Global Power Supplies\n")
stimuli.write_supply(self.sf)
# instantiate the sram
self.sf.write("\n* Instantiation of the SRAM\n")
stimuli.inst_sram(stim_file=self.sf,
abits=self.addr_size,
dbits=self.word_size,
sram_name=self.name)
self.sf.write("\n* SRAM output loads\n")
for i in range(self.word_size):
self.sf.write("CD{0} d[{0}] 0 {1}f\n".format(i,load))
# add access transistors for data-bus
self.sf.write("\n* Transmission Gates for data-bus and control signals\n")
stimuli.inst_accesstx(stim_file=self.sf, dbits=self.word_size)
# generate data and addr signals
self.sf.write("\n* Generation of data and address signals\n")
for i in range(self.word_size):
if i == self.probe_data:
self.gen_data(clk_times=self.cycle_times,
sig_name="data[{0}]".format(i),
period=period,
slew=slew)
else:
stimuli.gen_constant(stim_file=self.sf,
sig_name="d[{0}]".format(i),
v_val=self.gnd)
self.gen_addr(clk_times=self.cycle_times,
addr=self.probe_address,
period=period,
slew=slew)
# generate control signals
self.sf.write("\n* Generation of control signals\n")
self.gen_csb(self.cycle_times, period, slew)
self.gen_web(self.cycle_times, period, slew)
self.gen_oeb(self.cycle_times, period, slew)
self.sf.write("\n* Generation of global clock signal\n")
stimuli.gen_pulse(stim_file=self.sf,
sig_name="CLK",
v1=self.gnd,
v2=self.vdd,
offset=period,
period=period,
t_rise=slew,
t_fall=slew)
self.write_measures(period)
# run until the end of the cycle time
stimuli.write_control(self.sf,self.cycle_times[-1] + period)
self.sf.close()