class Machine:
def __init__(self, instructions):
self.memory = Memory(instructions)
self.pc = [96]
self.preIssue = PreIssue()
self.hazard = HazardUnit(self.preIssue)
self.registers = [0] * 32
self.cache = Cache(self.memory)
self.cycleCount = 0
self.shouldBreak = [False]
self.preAlu = PreALU()
self.postAlu = PostALU()
self.alu = ALU(hazard = self.hazard, registers = self.registers, preAlu = self.preAlu, postAlu = self.postAlu)
self.preMem = PreMEM()
self.postMem = PostMEM()
self.mem = MEM(cache = self.cache, registers = self.registers, hazard = self.hazard, preMem = self.preMem, postMem = self.postMem)
self.issue = Issue(registers = self.registers, hazard = self.hazard, preIssue = self.preIssue, preMem = self.preMem, preAlu = self.preAlu)
self.wb = WB(registers = self.registers, hazard = self.hazard, postMem = self.postMem, postAlu = self.postAlu)
self.fetch = IF(cache = self.cache, pc = self.pc, registers = self.registers, preIssue = self.preIssue, trigger = self.shouldBreak, hazard = self.hazard, issue = self.issue)
def cycle(self):
#execute in reverse order
self.cache.memoryRead()
self.wb.execute()
self.mem.execute()
self.alu.execute()
self.issue.execute()
self.fetch.execute()
self.cycleCount += 1 #increment counter
def executeMix(self, f = None, *args): #f is a function to be run on the machine between each cycle
self.cycleCount = 0
while not self.shouldBreak[0] or len(self.hazard) != 0:
#bp()
self.cycle()
if self.shouldBreak[0] and len(self.hazard) == 0:
self.cache.writeToMemory()
if f != None:
f(*args)
def __init__(self, instructions): self.memory = Memory(instructions) self.pc = [96] self.preIssue = PreIssue() self.hazard = HazardUnit(self.preIssue) self.registers = [0] * 32 self.cache = Cache(self.memory) self.cycleCount = 0 self.shouldBreak = [False] self.preAlu = PreALU() self.postAlu = PostALU() self.alu = ALU(hazard = self.hazard, registers = self.registers, preAlu = self.preAlu, postAlu = self.postAlu) self.preMem = PreMEM() self.postMem = PostMEM() self.mem = MEM(cache = self.cache, registers = self.registers, hazard = self.hazard, preMem = self.preMem, postMem = self.postMem) self.issue = Issue(registers = self.registers, hazard = self.hazard, preIssue = self.preIssue, preMem = self.preMem, preAlu = self.preAlu) self.wb = WB(registers = self.registers, hazard = self.hazard, postMem = self.postMem, postAlu = self.postAlu) self.fetch = IF(cache = self.cache, pc = self.pc, registers = self.registers, preIssue = self.preIssue, trigger = self.shouldBreak, hazard = self.hazard, issue = self.issue)