def main( ):
testUtil.runCycles( 10000000 )
#PutMemAdu Test
data = os.urandom(80)
data = [ord(c) for c in data]
testMemProcUtil.putmem(0x08000000, data, 0xA5)
# GetMemAdu test
readData = testMemProcUtil.getmem(0x08000000, 80, 0xA5)
if(data == readData):
print ("Success - Write-Read ADU")
else:
print data
print readData
raise Exception('data mistmach')
# Partial Write test
readData = testMemProcUtil.getmem(0x08000000, 40, 0xA5)
data = os.urandom(8)
data = [ord(c) for c in data]
testMemProcUtil.putmem(0x08000008, data, 0xA5)
readBackData = testMemProcUtil.getmem(0x08000000, 40, 0xA5)
sandwichData = readData[:8]+data+readData[len(data)+8:]
if(sandwichData == readBackData):
print ("Success - Write_Part-Read ADU")
else:
print readData
print data
print readBackData
print sandwichData
raise Exception('data mistmach')
def getmem(addr, len, flags):
testUtil.runCycles(RUN_CYCLES)
req = (getsingleword(6) + [0, 0, 0xA4, 0x01] + getsingleword(flags) +
getdoubleword(addr) + getsingleword(len))
testUtil.writeUsFifo(req)
testUtil.writeEot()
# read data
data = []
lenExp = len
if (flags & 0x0008):
lenExp += int(len / 8)
if (flags & 0x0010):
lenExp += int(len / 8)
for i in range(0, int(-(-float(lenExp) // 4))):
data += list(testUtil.readDsEntryReturnVal())
readLen = testUtil.readDsEntryReturnVal()
if (getsingleword(lenExp) != list(readLen)):
print getsingleword(lenExp)
print list(readLen)
raise Exception("Invalid Length")
expResp = [
0xc0, 0xde, 0xa4, 0x01, 0x0, 0x0, 0x0, 0x0, 0x00, 0x0, 0x0, 0x03
]
testUtil.readDsFifo(expResp)
testUtil.readEot()
return data[:lenExp]
def main():
try:
testUtil.runCycles(10000000)
# Send a partial chip-op
testUtil.writeUsFifo(TESTDATA)
testUtil.resetFifo()
# Make sure both the upstream and downstrem FIFOs are clear after the reset
testUtil.waitTillUsFifoEmpty()
testUtil.waitTillDsFifoEmpty()
# Now send a complete chip-op on the upstream FIFO
testUtil.writeUsFifo(TESTDATA_FULL)
testUtil.writeEot()
testUtil.resetFifo()
# Make sure both the upstream and downstrem FIFOs are clear after the reset
testUtil.waitTillUsFifoEmpty()
testUtil.waitTillDsFifoEmpty()
# Now send a get capabilities chip-op, so that in response, the DS FIFO
# gets full before we do a reset
testUtil.writeUsFifo(TESTDATA_2)
testUtil.writeEot()
testUtil.resetFifo()
# Make sure both the upstream and downstrem FIFOs are clear after the reset
testUtil.waitTillUsFifoEmpty()
testUtil.waitTillDsFifoEmpty()
except:
print("\nTest completed with error(s), Raise error")
raise
print("\nTest completed with no errors")
def main():
# Run Simics initially
testUtil.runCycles(100000000)
print "\n Execute SBE Test - negative testcase - less size\n"
getCapabilities(0x08000000, 30, 0x00020019)
print "\n Execute SBE Test - negative testcase - not multiple of PBA\n"
getCapabilities(0x08000000, 129, 0x00020019)
print "\n Execute SBE Test - positive testcase \n"
getCapabilities(0x08000000, 128, 0)
testUtil.runCycles(100000000)
# read capabilities memory
readData = testMemUtil.getmem(0x08000000, 128, 0x02)
# ignore first 20 bytes which is a dynamic data
readData = readData[28:]
# get only valid data
readData = readData[:len(capMsg)]
if (capMsg == readData):
print("Success - PSU get capabilities")
else:
print capMsg
print readData
raise Exception('data mistmach')
def main():
testUtil.runCycles(10000000)
testUtil.writeUsFifo(TESTDATA)
testUtil.writeEot()
testUtil.runCycles(10000000)
testUtil.readDsFifo(EXPDATA)
testUtil.readEot()
def main():
testUtil.runCycles(10000000)
# Put Occ Sram test - Linear - Can be tested over Normal
# Debug mode
testUtil.writeUsFifo(PUTSRAM_OCC_CNTLDATA)
# Write 32 bytes of data 8 times => 32*8 = 256 = 0x100
i_cnt = 0
while i_cnt < 8:
testUtil.writeUsFifo(PUTSRAM_OCC_TESTDATA)
i_cnt = i_cnt + 1
testUtil.writeEot()
# Read the expected data for put sram
testUtil.readDsFifo(PUTSRAM_OCC_EXP_CNTLDATA)
testUtil.readEot()
# Get Sram Linear
testUtil.writeUsFifo(GETSRAM_OCC_CNTLDATA)
testUtil.writeEot()
# Read the Expected Data for get Sram
i_cnt = 0
while i_cnt < 8:
testUtil.readDsFifo(GETSRAM_OCC_EXP_TESTDATA)
i_cnt = i_cnt + 1
testUtil.readDsFifo(GETSRAM_OCC_EXP_CNTLDATA)
testUtil.readEot()
def putmem(addr, data, flags, ecc=0):
lenInBytes = len(data)
if (len(data) < 8):
data = data + [0] * (4 - len(data))
totalLen = 5 + len(data) / 4
coreChipletId = 0x00
if (flags & 0x0040):
# LCO mode is set, so chiplet id - 0x20
coreChipletId = 0x20
req = (
getsingleword(totalLen) + [0, 0, 0xA4, 0x02] + [coreChipletId, ecc] +
gethalfword(flags)
#0,0,0x0,0xA5] #CoreChipletId/EccByte/Flags -> NoEccOverride/CacheInhibit/FastMode/NoTag/NoEcc/AutoIncr/Adu/Proc
+ getdoubleword(addr) + getsingleword(lenInBytes) # length of data
+ data)
testUtil.writeUsFifo(req)
testUtil.writeEot()
testUtil.runCycles(RUN_CYCLES)
if (flags & 0x0008):
lenInBytes += int(len(data) / 8)
if (flags & 0x0010):
lenInBytes += int(len(data) / 8)
expData = (
getsingleword(lenInBytes) +
[0xc0, 0xde, 0xa4, 0x02, 0x0, 0x0, 0x0, 0x0, 0x00, 0x0, 0x0, 0x03])
testUtil.readDsFifo(expData)
testUtil.readEot()
def main():
testUtil.runCycles(10000000)
print("\nStarting putscom test")
testUtil.writeUsFifo(PUTSCOM_TESTDATA)
testUtil.writeEot()
testUtil.readDsFifo(PUTSCOM_EXPDATA)
testUtil.readEot()
print("\nStarting invalid putscom test")
testUtil.writeUsFifo(PUTSCOM_TESTDATA_INVALID)
testUtil.writeEot()
testUtil.readDsFifo(PUTSCOM_EXPDATA_INVALID)
testUtil.extractHWPFFDC()
#flush out distance
testUtil.readDsEntryReturnVal()
testUtil.readEot()
print("\nStarting getscom test")
testUtil.writeUsFifo(GETSCOM_TESTDATA)
testUtil.writeEot()
testUtil.readDsFifo(GETSCOM_EXPDATA)
testUtil.readEot()
print("\nStarting invalid getscom test")
testUtil.writeUsFifo(GETSCOM_TESTDATA_INVALID)
testUtil.writeEot()
testUtil.readDsFifo(GETSCOM_EXPDATA_INVALID)
testUtil.extractHWPFFDC()
#flush out distance
testUtil.readDsEntryReturnVal()
testUtil.readEot()
def main():
testUtil.runCycles(10000000)
#PutMemAdu with ECC
data = os.urandom(80)
data = [ord(c) for c in data]
testMemProcUtil.putmem(0x08000000, data, 0xAD, 0xEF)
data = testMemProcUtil.addItagEcc(data, False, True, 0xEF)
# GetMemAdu test with ECC
readData = testMemProcUtil.getmem(0x08000000, 80, 0xAD)
if (data == readData):
print("Success - Write-Read ADU with ECC")
else:
print data
print readData
raise Exception('data mistmach')
# Partial Write test
readData = testMemProcUtil.getmem(0x08000000, 40, 0xAD)
data = os.urandom(8)
data = [ord(c) for c in data]
testMemProcUtil.putmem(0x08000008, data, 0xAD, 0xEF)
data = testMemProcUtil.addItagEcc(data, False, True, 0xEF)
readBackData = testMemProcUtil.getmem(0x08000000, 40, 0xAD)
sandwichData = readData[:9] + data + readData[len(data) + 9:]
if (sandwichData == readBackData):
print("Success - Write_Part-Read ADU with ECC")
else:
print readData
print data
print readBackData
print sandwichData
raise Exception('data mistmach')
def main():
testUtil.runCycles(10000000)
# Test case 1: Valid lengths
bytes = [1, 2, 4]
offsets = {1: (0, 1, 2, 3, 4, 5, 6, 7), 2: (0, 2, 4, 6), 4: (0, 4)}
for byte in bytes:
for offset in offsets[byte]:
#PutMemAdu Test
data = os.urandom(byte)
data = [ord(c) for c in data]
testMemProcUtil.putmem(0x08000000 + offset, data, 0xA5)
# GetMemAdu test
readData = testMemProcUtil.getmem(0x08000000 + offset, byte, 0xA5)
if (data == readData):
print("Success - Write-Read ADU byte[" + str(byte) +
"] offset[" + str(offset) + "]")
else:
print[hex(a) for a in data]
print[hex(a) for a in readData]
raise Exception('data mistmach')
# Test case 2: Invalid length - 3
# GetMemAdu test
testMemProcUtil.getmem_failure(0x08000000, 3, 0xA5, 0x0002000A)
print("Success - invalid length test")
def getsram(addr, mode, length, primStatus, secStatus):
req = (getsingleword(0x05) + getsingleword(0xa403) + getsingleword(mode) +
getsingleword(addr) + getsingleword(length))
testUtil.runCycles(10000000)
testUtil.writeUsFifo(req)
testUtil.writeEot()
data = []
if ((primStatus != 0) or (secStatus != 0)):
length = 0
for i in range(0, int(-(-float(length) // 4))):
data += list(testUtil.readDsEntryReturnVal())
readLen = testUtil.readDsEntryReturnVal()
if (getsingleword(length) != list(readLen)):
print getsingleword(length)
print list(readLen)
raise Exception("Invalid Length")
expResp = (getsingleword(0xc0dea403) + gethalfword(primStatus) +
gethalfword(secStatus) + getsingleword(0x03))
testUtil.readDsFifo(expResp)
testUtil.readEot()
return data[:length]
def main():
testUtil.runCycles(10000000)
#stop all thread in core0
testUtil.writeUsFifo(INST_START0_ALL_TESTDATA_WITH_WARN_FLG)
testUtil.writeEot()
testUtil.readDsFifo(INST_EXPDATA)
testUtil.readEot()
def main( ):
testUtil.runCycles( 10000000 )
testUtil.writeUsFifo( TESTDATA )
testUtil.writeEot( )
testUtil.readDsFifo( EXPDATA )
testUtil.readEot( )
# fail get mem in quiesce state
testMemUtil.getmem_failure(0x08000000, 128*2, 0x02, 0x00010008, False)
def main():
testUtil.runCycles(10000000)
# GetRing test - Aligned Data
testUtil.writeUsFifo(GETRING_TESTDATA)
testUtil.writeEot()
testUtil.readDsEntry(678) ## 6242 entries
testUtil.readDsFifo(GETRING_EXPDATA)
testUtil.runCycles(10000000)
testUtil.readEot()
def getmem_failure(addr, len, flags, responseWord):
testUtil.runCycles(10000000)
req = (getsingleword(6) + [0, 0, 0xA4, 0x01] + getsingleword(flags) +
getdoubleword(addr) + getsingleword(len))
testUtil.writeUsFifo(req)
testUtil.writeEot()
expResp = ([0x0, 0x0, 0x0, 0x0] + [0xc0, 0xde, 0xa4, 0x01] +
getsingleword(responseWord) + [0x0, 0x0, 0x0, 0x03])
testUtil.readDsFifo(expResp)
testUtil.readEot()
def main():
testUtil.runCycles(10000000)
testUtil.writeUsFifo(PUTREG_TESTDATA)
testUtil.writeEot()
testUtil.readDsFifo(PUTREG_EXPDATA)
testUtil.readEot()
testUtil.writeUsFifo(GETREG_TESTDATA)
testUtil.writeEot()
testUtil.readDsFifo(GETREG_EXPDATA)
testUtil.readEot()
def main():
testUtil.runCycles(10000000)
testUtil.writeUsFifo(TESTDATA)
testUtil.writeEot()
# Ignore first two enteries ( major number, minor number
# and fw version) as they will keep on changing
testUtil.readDsEntry(2)
testUtil.readDsFifo(EXPDATA1)
testUtil.readDsFifo(EXPDATA2)
testUtil.readDsFifo(EXPDATA3)
testUtil.readEot()
def main( ):
# First Case without Fast Mode without LCO
testUtil.runCycles( 10000000 )
# Get mem PBA - WO FMODE, WO LCO
readData = testMemUtil.getmem(0x08200000, 128, 0x02)[44:][:-12]
if(data == readData):
print ("Success - Write-Read PBA - WO FMODE, WO LCO")
else:
print data
print readData
raise Exception('data mistmach')
def getmem_failure(addr, len, flags, responseWord, withLen=True):
testUtil.runCycles(RUN_CYCLES)
req = (getsingleword(6) + [0, 0, 0xA4, 0x01] + getsingleword(flags) +
getdoubleword(addr) + getsingleword(len))
testUtil.writeUsFifo(req)
testUtil.writeEot()
lenWord = []
if withLen:
lenWord = [0x0, 0x0, 0x0, 0x0]
expResp = (lenWord + [0xc0, 0xde, 0xa4, 0x01] +
getsingleword(responseWord) + [0x0, 0x0, 0x0, 0x03])
testUtil.readDsFifo(expResp)
testUtil.readEot()
def main():
testUtil.runCycles(10000000)
testUtil.writeUsFifo(PUTMEM_TEST_HDR)
loop = 1
while (loop <= LOOP_COUNT):
testUtil.writeUsFifo(PUTMEM_TEST_DATA)
loop += 1
testUtil.writeEot()
testUtil.readDsFifo(PUTMEM_EXPDATA)
testUtil.readEot()
def main():
testUtil.runCycles(10000000)
# GetMem test
testUtil.writeUsFifo(GETMEM_TESTDATA)
testUtil.writeEot()
# GetMem chipOp would send the read data first,
# thus, would attempt to read the expected length of data first
loop = 1
while (loop <= LOOP_COUNT):
testUtil.readDsEntry(32) ## 32 entries ~ 128B PBA granule
loop += 1
testUtil.readDsFifo(GETMEM_EXPDATA)
testUtil.readEot()
def main():
testUtil.runCycles(10000000)
# GetMem test
testUtil.writeUsFifo(GETMEM_TESTDATA)
testUtil.writeEot()
# GetMem chipOp would send the read data first,
# thus, would attempt to read the expected length of data first
loop = 1
while (loop <= LOOP_COUNT):
testUtil.readDsFifo(GETMEM_EXP_RESPDATA)
loop += 1
testUtil.readDsFifo(GETMEM_EXP_RESPHDR)
testUtil.readEot()
def main( ):
( rc, out ) = quiet_run_command( "sbe-ddlevel 0", output_modes.regular )
if(rc == "DD1"):
print "Not running Get Capabilities on DD1"
return
testUtil.runCycles( 10000000 )
testUtil.writeUsFifo( TESTDATA )
testUtil.writeEot( )
# Ignore first 7 enteries ( major number, minor number
# and fw version & tag) as they will keep on changing
testUtil.readDsEntry( 7 )
testUtil.readDsFifo( EXPDATA1 )
testUtil.readDsFifo( EXPDATA2 )
testUtil.readDsFifo( EXPDATA3 )
testUtil.readEot( )
def putsram(addr, mode, data, primStatus, secStatus):
req = (getsingleword(5 + (len(data) / 4)) + [0, 0, 0xA4, 0x04] +
getsingleword(mode) + getsingleword(addr) +
getsingleword(len(data)) + data)
testUtil.runCycles(10000000)
testUtil.writeUsFifo(req)
testUtil.writeEot()
if ((primStatus != 0) or (secStatus != 0)):
data = []
expData = (getsingleword(len(data)) + [0xc0, 0xde, 0xa4, 0x04] +
gethalfword(primStatus) + gethalfword(secStatus) +
getsingleword(0x03))
testUtil.readDsFifo(expData)
testUtil.readEot()
def main( ):
testUtil.runCycles( 10000000 )
# Test case 1: 1byte access
#PutMemAdu Test
data = os.urandom(1)
data = [ord(c) for c in data]
testMemProcUtil.putmem(0x08000000, data, 0xA5)
# GetMemAdu test
readData = testMemProcUtil.getmem(0x08000000, 1, 0xA5)
if(data == readData):
print ("Success - Write-Read ADU")
else:
print data
print readData
raise Exception('data mistmach')
# Test case 2: 2byte access
#PutMemAdu Test
data = os.urandom(2)
data = [ord(c) for c in data]
testMemProcUtil.putmem(0x08000000, data, 0xA5)
# GetMemAdu test
readData = testMemProcUtil.getmem(0x08000000, 2, 0xA5)
if(data == readData):
print ("Success - Write-Read ADU")
else:
print data
print readData
raise Exception('data mistmach')
# Test case 3: 4byte access
#PutMemAdu Test
data = os.urandom(4)
data = [ord(c) for c in data]
testMemProcUtil.putmem(0x08000000, data, 0xA5)
# GetMemAdu test
readData = testMemProcUtil.getmem(0x08000000, 4, 0xA5)
if(data == readData):
print ("Success - Write-Read ADU")
else:
print data
print readData
raise Exception('data mistmach')
def main():
testUtil.runCycles(10000000)
testUtil.writeUsFifo(PUTSCOM_TESTDATA)
testUtil.writeEot()
testUtil.readDsFifo(PUTSCOM_EXPDATA)
testUtil.readEot()
testUtil.writeUsFifo(PUTSCOMUMASK_TESTDATA)
testUtil.writeEot()
testUtil.readDsFifo(PUTSCOMUMASK_EXPDATA)
testUtil.readEot()
testUtil.writeUsFifo(GETSCOMUMASK_TESTDATA)
testUtil.writeEot()
testUtil.readDsFifo(GETSCOMUMASK_EXPDATA)
testUtil.readEot()
def main():
testUtil.runCycles(10000000)
#PutMemAdu Test
testUtil.writeUsFifo(PUTMEMADU_CNTLDATA)
testUtil.writeUsFifo(PUTMEMADU_TESTDATA)
testUtil.writeEot()
testUtil.readDsFifo(PUTMEMADU_EXPDATA)
testUtil.readEot()
# GetMemAdu test
testUtil.writeUsFifo(GETMEMADU_TESTDATA)
testUtil.writeEot()
testUtil.readDsFifo(GETMEMADU_EXPDATA)
testUtil.runCycles(10000000)
testUtil.readEot()
def pollingOn(self, simObj, test_data, retries=20):
for l_param in test_data:
while True:
print "\n***** Polling On result - retrials left [%d] " % retries
print "\n"
testUtil.runCycles(1000000)
test_d = (l_param, )
rc = self.ExecuteTestOp(simObj, test_d, False)
if rc == SUCCESS:
print('Polling Successful for - ' + l_param[5])
break
elif retries <= 0:
print " Retrials exhausted... Exiting polling"
raise Exception('Polling Failed for - ' + l_param[5])
break
else:
retries = retries - 1
return SUCCESS
def main():
testUtil.runCycles(10000000)
print("\nStarting control fastarray test")
print("\nTest case: Setup")
testUtil.writeUsFifo(CONTROL_FAST_ARRAY_SETUP_TESTDATA)
testUtil.writeEot()
testUtil.readDsFifo(CONTROL_FAST_ARRAY_VALID)
testUtil.readEot()
print("\nTest case: Catchup")
testUtil.writeUsFifo(CONTROL_FAST_ARRAY_CATCHUP_TESTDATA)
testUtil.writeEot()
testUtil.readDsFifo(CONTROL_FAST_ARRAY_VALID)
testUtil.readEot()
print("\nTest case: Cleanup")
testUtil.writeUsFifo(CONTROL_FAST_ARRAY_CLEANUP_TESTDATA)
testUtil.writeEot()
testUtil.readDsFifo(CONTROL_FAST_ARRAY_VALID)
testUtil.readEot()
def main():
# Run Simics initially
testUtil.runCycles(10000000)
print "\n Execute SBE Test - Read SBE Mem\n"
'''
Test Case 1
'''
readSeeprom(0, 128, 0x08000000, 0, 0)
print "SUCCESS: read seeprom valid"
# Read data from cache and verify its contents
# seeprom header
seepprmHdr = 'XIP SEPM'
#read from cache
readData = testMemUtil.getmem(0x08000000, 0x80, 0x02)
for byte in range(len(seepprmHdr)):
if (ord(seepprmHdr[byte]) != readData[byte]):
print "Data mismtach at: ", byte
print " expected: ", ord(seepprmHdr[byte])
print " Actual: ", readData[byte]
raise Exception('data mistmach')
'''
Test Case 2
'''
readSeeprom(0x38CA0, 0x180, 0x8973780, 0, 0)
print "SUCCESS: read seeprom HB testcase"
'''
Test Case 3
'''
readSeeprom(0x0, 0x40, 0x08000000, 0x03, 0x19)
print "SUCCESS: read seeprom size not aligned"
'''
Test Case 4
'''
readSeeprom(0x3fe80, 0x180, 0x08000000, 0x03, 0x19)
print "SUCCESS: read seeprom size exceeded"
'''
Test Case 5
'''
readSeeprom(0x7, 0x40, 0x08000000, 0x03, 0x19)
print "SUCCESS: read seeprom offset not aligned"