def fs_rk1(rel, SIMPLIFY, indt): rk = rel.power() #Rk if (rk[1] == 0): print "rk approximated..." rk = rk[0].coalesce() #print rk rk = isl.Map(iscc.RepairRk(str(rk), 0)) # przesun k do symb print "RK" print rk uds = rel.domain().subtract(rel.range()).coalesce() # ADD INDEPENDENT TILES TO UDS #uds = uds.union(indt).coalesce() print "UDS" print uds rel_plus = rel.transitive_closure()[0] sk = uds.apply(rk).subtract(uds.apply(rk).apply(rel_plus)).coalesce() sk = sk.insert_dims(isl.dim_type.set, 0, 1) sk = sk.set_dim_name(isl.dim_type.set, 0, "ink") c = isl.Constraint.eq_from_names(sk.get_space(), {"k": -1, "ink": 1}) sk = sk.add_constraint(c) sk = tiling_v3.Project(sk, ["k"]) uds = uds.insert_dims(isl.dim_type.set, 0, 1) uds = uds.set_dim_name(isl.dim_type.set, 0, "ink") c = isl.Constraint.eq_from_names(sk.get_space(), {1: 0, "ink": 1}) uds = uds.add_constraint(c) #x = isl.Set("{ [0, 0, 0, 6]}") #uds = uds.union(x).coalesce() print "TUDS" print uds sk = sk.union(uds).coalesce() if (SIMPLIFY): sk = imperf_tile.SimplifySlice(sk) return sk
def Create_RUCS(isl_rel, isl_relclosure, uds, udsi, dl=0, Rel_Y=""): n = uds.dim(isl.dim_type.set) symb_tuple = SymbolicTuple(n) _symb = symb_tuple[1] symb_tuple = symb_tuple[0] Sx = udsi.intersect(symb_tuple) Si = Sx.apply(isl_relclosure) if (dl == 1): Si = Si.apply(Rel_Y).coalesce() ris = isl_relclosure.fixed_power_val(-1) S2 = Si.apply(ris).intersect(uds).coalesce( ) # Intersection(Range(Restrict_Domain(copy(Ris), copy(S1))), copy(UDS)); // All_UDS? rucs = isl.Map.from_domain_and_range( Sx, S2).coalesce() # Relation RUCS = Cross_Product(copy(Sx), copy(S2)); inp = [] outp = [] inp2 = [] outp2 = [] if (dl == 0): zakres = n else: zakres = n / 2 for i in range(0, n): inp.append("i" + str(i)) outp.append("o" + str(i)) if (i < zakres): inp2.append("i" + str(i)) outp2.append("o" + str(i)) rlex = "{[" + ",".join(inp) + "] -> [" + ",".join( outp) + "] : " + tiling_v3.CreateLex(outp2, inp2) + "}" rlex = isl.Map(rlex) rucs = rucs.intersect(rlex) rucs = tiling_v3.Project(rucs, _symb).coalesce() return rucs
#str_TV = str(TILE_VLD) #str_TV = str_TV.replace('[N, ii, jj, kk] -> ', '') #str_TV = str_TV.replace('[', '[ii,jj,kk,') #str_TV = '[N] -> ' + str_TV #print str_TV #TILE_VLD_EXT = isl.Set(str_TV) if (1 == 0): Rapply = tiling_v3.GetRapply(['i', 'j', 'k'], ['ii', 'jj', 'kk'], 'ii,jj,kk,N,') TILE_VLD_EXT = tiling_v3.Project( TILE_VLD.apply(Rapply).coalesce(), ['ii', 'jj', 'kk']) Rmap = isl.Map( '{[ii,jj,kk,i,j,k,1] -> [0, ii,0, jj,0, kk,0, i,0, j,0,k,1]; [ii,jj,kk,i,j,k,2] -> [0, ii,0, jj,1, kk,0, i,0, j,1,k,2] } ' ) TILE_VLD_EXT = TILE_VLD_EXT.apply(Rmap).coalesce() RSched = '[N] -> {[i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12,i13]->[i1,i2,i3,i4,i5,i6,i7,-i8,i9,i10,i11,i12,i13] : ' in_ = [ 'i1', 'i2', 'i3', 'i4', 'i5', 'i6', 'i7', 'i8', 'i9', 'i10', 'i11', 'i12', 'i13' ] RSched = RSched + copyconstr.GetConstrSet(in_, TILE_VLD_EXT) + "}" Rsched = isl.Map(RSched)
def tile_par(isl_TILEprim, isl_TILEbis, sym_exvars, symb, isl_rel, isl_relplus, isl_relclosure): nloop = "" srepr = "" with open('sources_of_slices.txt') as f: content = f.readlines() srepr = content[0] srepr = isl.Set(srepr) srepr = srepr.insert_dims(isl.dim_type.set, 0, len(sym_exvars)) for i in range(0, len(sym_exvars)): srepr = srepr.set_dim_name(isl.dim_type.set, i, sym_exvars[i]) Rel_Z = "{[" for i in range(0, 2 * len(sym_exvars)): Rel_Z = Rel_Z + "i" + str(i) + "," Rel_Z = Rel_Z + "m] -> [" for i in range(0, len(sym_exvars)): Rel_Z = Rel_Z + "i" + str(i) + "," Rel_Z = Rel_Z[:-1] + "] };" Rel_Z = isl.Map(Rel_Z) Bis_Combo = isl_TILEbis[0] for j in range(1, len(isl_TILEbis)): Bis_Combo = Bis_Combo.union(isl_TILEbis[j]).coalesce() TILE_SOUR = Bis_Combo.intersect(srepr).coalesce() print TILE_SOUR fs = 0 if (TILE_SOUR.lexmax() == TILE_SOUR.lexmin()): print "FS" fs = 1 else: print "SLICING" rplus = tiling_v3.ExtendMap(isl_relplus, sym_exvars) rstar = tiling_v3.ExtendMap(isl_relclosure, sym_exvars) rt_red = tiling_v3.ExtendMap(isl_rel, sym_exvars) rs = isl.Map.from_domain_and_range(Bis_Combo, Bis_Combo) rs = rs.intersect(rplus) rt_red = rs.intersect(rs) if (fs != 1): z = TILE_SOUR.apply(Rel_Z) srepr_loop = iscc.iscc_communicate("L :=" + str(z) + "; codegen L;") rs = iscc.iscc_communicate(str(rs) + ";", 1).split('\n')[0] rs = iscc.RelationExists(rs, len(sym_exvars), symb) srepr_loop = srepr_loop.split('\n') for i in range(0, len(srepr_loop)): if "for" in srepr_loop[i]: srepr_loop.insert(i, "#pragma omp parallel for") break st_reg = re.compile('\s*\(.*\);') vecs = [] taby = [] for line in srepr_loop: if (st_reg.match(line)): vecs.append(iscc.s1_to_vec(line, len(vecs))) taby.append(iscc.correct.whites(line)) #R_T = iscc_communicate("RS := " + rs + ";RS;") cmd = "RT :=" + rs + ";" for i in range(0, len(vecs)): cmd = cmd + vecs[i] + "codegen RT(S" + str(i) + ');print "###";' cmd = iscc.iscc_communicate(cmd) cmd = cmd.split('"###"') new_loop = [] i = 0 for line in srepr_loop: if (st_reg.match(line)): petla = cmd[i].split('\n') for s in petla: new_loop.append(taby[i] + s) i = i + 1 else: new_loop.append(line) #print new_loop nloop = "" for line in new_loop: if line != '': nloop = nloop + line + "\n" nloop = nloop[:-1] isl_TILEprim_ = isl_TILEprim[0].union(isl_TILEprim[1]) bl_2half = iscc.iscc_communicate("L :=" + str(isl_TILEprim[0]) + "; codegen L;") slice_tiling(nloop, bl_2half, sym_exvars) else: I = isl.Map.identity( isl.Space.create_from_names(ctx, in_=sym_exvars, out=sym_exvars)).coalesce() sym_tmp = [] rlex = "{[" for s in sym_exvars: rlex = rlex + s + "," sym_tmp.append(s + "'") rlex = rlex[:-1] + '] -> [' for s in sym_exvars: rlex = rlex + s + "'," rlex = rlex[:-1] + '] : ' rlex = rlex + tiling_v3.CreateLex(sym_tmp, sym_exvars) + "};" rlex = isl.Map(rlex) UDS = isl_rel.domain().subtract(isl_rel.range()) UDS = UDS.insert_dims(isl.dim_type.set, 0, len(sym_exvars)) for i in range(0, len(sym_exvars)): UDS = UDS.set_dim_name(isl.dim_type.set, i, sym_exvars[i]) tuds = UDS.intersect(isl_TILEbis[0]).coalesce().apply(Rel_Z).coalesce() rt_red = iscc.iscc_communicate(str(rt_red) + ";", 1).split('\n')[0] rt_red = iscc.RelationExists(rt_red, len(sym_exvars), symb) #rk = iscc_communicate(rlex + 'RT_RED := ' + rt_red + "*RLEX;pow RT_RED;") rt_red = isl.Map(rt_red).intersect(rlex).coalesce() rk = rt_red.power() rk = rk[0] rk = isl.Map(iscc.RepairRk(str(rk), 0)) rp = rt_red.transitive_closure()[0] sk = tuds.apply(rk).subtract(tuds.apply(rk).apply(rp)).coalesce() sk = sk.insert_dims(isl.dim_type.set, 0, 1) sk = sk.set_dim_name(isl.dim_type.set, 0, "ink") c = isl.Constraint.eq_from_names(sk.get_space(), {"k": -1, "ink": 1}) sk = sk.add_constraint(c) sk = tiling_v3.Project(sk, ["k"]) tuds = tuds.insert_dims(isl.dim_type.set, 0, 1) tuds = tuds.set_dim_name(isl.dim_type.set, 0, "ink") c = isl.Constraint.eq_from_names(sk.get_space(), {1: 0, "ink": 1}) tuds = tuds.add_constraint(c) sk = sk.union(tuds) fsloop = iscc.iscc_communicate("L :=" + str(sk) + "; codegen L;") bl_2half = iscc.iscc_communicate("L :=" + str(isl_TILEprim[0]) + "; codegen L;") slice_tiling(fsloop, bl_2half, sym_exvars, 1)
def tile_par2(isl_TILEbis, sym_exvars, isl_rel, isl_relplus, isl_relclosure, Extend, _rap, Dodatek, SIMPLIFY): #with open('sources_of_slices.txt') as f: # content = f.readlines() # srepr = content[0] #srepr = isl.Set(srepr) #with open('rucs.txt') as f: # content = f.readlines() # rucs = content[0] #_rel = _rel.remove_dims(isl.dim_type.in_, 0,1) #_rel = _rel.remove_dims(isl.dim_type.out, 0,1) #print _rel ''' ir = isl_rel print ir ir = ir.insert_dims(isl.dim_type.in_, 0, len(sym_exvars)) ir = ir.insert_dims(isl.dim_type.out, 0, len(sym_exvars)) print ir ir2 = ir.from_domain_and_range(isl_TILEbis, isl_TILEbis).coalesce() ir = ir2.intersect(ir).coalesce() print ir ir = ir.remove_dims(isl.dim_type.in_, len(sym_exvars),len(sym_exvars)) ir = ir.remove_dims(isl.dim_type.out, len(sym_exvars),len(sym_exvars)) ir = ir.coalesce() print ir sys.exit(0); ''' srepr, rucs = slicing.Create_Srepr(isl_rel, isl_relclosure) print srepr ir = isl_rel.domain().union(isl_rel.range()).coalesce() ir = ir.insert_dims(isl.dim_type.set, 0, len(sym_exvars)) for i in range(0, len(sym_exvars)): ir = ir.set_dim_name(isl.dim_type.set, i, sym_exvars[i]) if (Extend): for i in range(0, 2 * len(sym_exvars)): ir = ir.insert_dims(isl.dim_type.set, 2 * i + 1, 1) srepr = srepr.insert_dims(isl.dim_type.set, 0, len(sym_exvars)) for i in range(0, len(sym_exvars)): srepr = srepr.set_dim_name(isl.dim_type.set, i, sym_exvars[i]) if (Extend): for i in range(0, 2 * len(sym_exvars)): srepr = srepr.insert_dims(isl.dim_type.set, 2 * i + 1, 1) x = 1 if (Extend): x = 2 #relacja do obliczenia poczatkow Rel_Z = "{[" for i in range(0, 2 * x * len(sym_exvars)): Rel_Z = Rel_Z + "i" + str(i) + "," Rel_Z = Rel_Z + "m] -> [" for i in range(0, x * len(sym_exvars)): Rel_Z = Rel_Z + "i" + str(i) + "," Rel_Z = Rel_Z[:-1] + "] };" Rel_Z = isl.Map(Rel_Z) #relacja do wylapania instrukcji z blokow Rel_Y = "{[" for i in range(0, x * len(sym_exvars)): Rel_Y = Rel_Y + "i" + str(i) + "," for i in range(0, x * len(sym_exvars) + 1): Rel_Y = Rel_Y + "j" + str(i) + "," Rel_Y = Rel_Y[:-1] + "] -> [" for i in range(0, x * len(sym_exvars)): Rel_Y = Rel_Y + "i" + str(i) + "," for i in range(0, x * len(sym_exvars) + 1): Rel_Y = Rel_Y + "k" + str(i) + "," Rel_Y = Rel_Y[:-1] + "] };" Rel_Y = isl.Map(Rel_Y) TILE_SOUR = isl_TILEbis.intersect(srepr).coalesce() TILE_IND = isl_TILEbis.subtract(isl_TILEbis.intersect(ir)).coalesce() indloop = iscc.iscc_communicate("L :=" + str(TILE_IND) + "; codegen L;") fs = 0 if (TILE_SOUR.lexmax() == TILE_SOUR.lexmin()): print "FS" fs = 1 else: print "SLICING" if (rucs.is_empty()): isl_rel = isl_rel.union(rucs) isl_relclosure = isl_relclosure.union(rucs) isl_relplus = isl_relplus.union(rucs) rplus = tiling_v3.ExtendMap(isl_relplus, sym_exvars, Extend) rstar = tiling_v3.ExtendMap(isl_relclosure, sym_exvars, Extend) rel_ = tiling_v3.ExtendMap(isl_rel, sym_exvars, Extend) #rucs = tiling_v3.ExtendMap(rucs, sym_exvars, Extend) rbis = isl.Map.from_domain_and_range(isl_TILEbis, isl_TILEbis) rs = rbis.intersect(rstar) rt_red = rbis.intersect(rplus) if (fs != 1): if (rucs.is_empty()): TILE_SOUR = TILE_SOUR.subtract(TILE_SOUR.apply( rplus)).coalesce() # remove dependent blocks with srepr TILE_RUCS = slicing.Create_RUCS(rel_, rs, TILE_SOUR, TILE_SOUR, 1, Rel_Y) TILE_SOUR = TILE_SOUR.subtract(TILE_RUCS.range()).coalesce() z = TILE_SOUR.apply(Rel_Z).coalesce() if (SIMPLIFY): z = imperf_tile.SimplifySlice(z) srepr_loop = iscc.iscc_communicate("L :=" + str(z) + "; codegen L;") # albo omega #srepr_loop = iscc.oc_communicate(z) print srepr_loop srepr_loop = srepr_loop.split('\n') for i in range(0, len(srepr_loop)): if "for" in srepr_loop[i]: srepr_loop.insert(i, "#pragma omp parallel for") break st_reg = re.compile('\s*\(.*\);') vecs = [] taby = [] for line in srepr_loop: if (st_reg.match(line)): vecs.append(isl.Set(iscc.s1_to_vec2(line, len(vecs)))) taby.append(iscc.correct.whites(line)) #print vecs permutate_maps = Dodatek[6] permutate_list = Dodatek[5] slices = [] for i in range(0, len(vecs)): vecs[i] = vecs[i].intersect(z).coalesce() for vec in vecs: vec = vec.insert_dims(isl.dim_type.set, x * len(sym_exvars), x * len(sym_exvars) + 1) slice = vec #.apply(rs) slice = slice.apply(Rel_Y) slice = slice.apply(rs).coalesce() # experimental permutate if (len(permutate_list) > 0): print "Tiling + slicing + permutation - experimental" RP = permutate_maps[0] RIDENT = RP.identity(RP.get_space()) if (not RP.is_equal(RIDENT) ): #permute map is not an identity map strRP = str(RP) strh = "" for i in range(0, x * len(sym_exvars)): strh = strh + "xx" + str(i) + "," if (Extend): strkoma = strRP.split(",") strRP = "" for i in range(0, 2 * len(sym_exvars)): strRP = strRP + strkoma[i] + ", yy" + str( i % len(sym_exvars)) + ", " strRP = strRP + strkoma[2 * len(sym_exvars)] strRP = strRP.replace("[", "[" + strh) RP = isl.Map(strRP) slice = slice.apply(RP).coalesce() # --------------------------------------------------------- if (SIMPLIFY): slice = imperf_tile.SimplifySlice(slice) slices.append(slice) print slice cmd = "" for i in range(0, len(vecs)): cmd = cmd + "codegen " + str(slices[i]) + ';print "###";' cmd = iscc.iscc_communicate(cmd) cmd = cmd.split('"###"') new_loop = [] i = 0 for line in srepr_loop: if (st_reg.match(line)): petla = cmd[i].split('\n') for s in petla: new_loop.append(taby[i] + s) i = i + 1 else: new_loop.append(line) nloop = "" for line in new_loop: if line != '': nloop = nloop + line + "\n" nloop = nloop[:-1] #nloop = nloop + indloop nloop = nloop.split('\n') # Dodatek = [LPetit, dane, maxl, step, nazwapar, permutate_list, permutate_maps] #permutate list nloop = tiling_v3.postprocess_loop(nloop) lines = nloop.split('\n') loop = imperf_tile.RestoreStatements(lines, Dodatek[0], Dodatek[1], Dodatek[2], Dodatek[3], Dodatek[5]) text_file = open(Dodatek[4], "w") text_file.write(loop) text_file.close() return "" else: print "fs (EXPERIMENTAL) ..." sym_tmp = [] rlex = "{[" for s in sym_exvars: rlex = rlex + s + "," sym_tmp.append(s + "'") rlex = rlex[:-1] + '] -> [' for s in sym_exvars: rlex = rlex + s + "'," rlex = rlex[:-1] + '] : ' rlex = rlex + tiling_v3.CreateLex(sym_tmp, sym_exvars) + "};" rlex = isl.Map(rlex) rlex = rlex.insert_dims(isl.dim_type.in_, len(sym_exvars), len(sym_exvars) + 1) rlex = rlex.insert_dims(isl.dim_type.out, len(sym_exvars), len(sym_exvars) + 1) UDS = isl_rel.domain().subtract(isl_rel.range()) UDS = UDS.insert_dims(isl.dim_type.set, 0, len(sym_exvars)) for i in range(0, len(sym_exvars)): UDS = UDS.set_dim_name(isl.dim_type.set, i, sym_exvars[i]) if (Extend): for i in range(0, 2 * len(sym_exvars)): UDS = UDS.insert_dims(isl.dim_type.set, 2 * i + 1, 1) rlex = rlex.insert_dims(isl.dim_type.in_, 2 * i + 1, 1) rlex = rlex.insert_dims(isl.dim_type.out, 2 * i + 1, 1) tuds = UDS.intersect(isl_TILEbis).coalesce() #tuds = tuds.insert_dims(isl.dim_type.set, len(sym_exvars), len(sym_exvars)+1) rt_red = rt_red.intersect(rlex).coalesce() rk = rt_red.power() rk = rk[0] rk = isl.Map(iscc.RepairRk(str(rk), 0)) rp = rt_red.transitive_closure()[0] sk = tuds.apply(rk).subtract(tuds.apply(rk).apply(rp)).coalesce() sk = sk.apply(Rel_Y).intersect(isl_TILEbis) sk = sk.insert_dims(isl.dim_type.set, 0, 1) sk = sk.set_dim_name(isl.dim_type.set, 0, "ink") c = isl.Constraint.eq_from_names(sk.get_space(), {"k": -1, "ink": 1}) sk = sk.add_constraint(c) sk = tiling_v3.Project(sk, ["k"]) tuds = tuds.apply(Rel_Y).intersect(isl_TILEbis) tuds = tuds.insert_dims(isl.dim_type.set, 0, 1) tuds = tuds.set_dim_name(isl.dim_type.set, 0, "ink") c = isl.Constraint.eq_from_names(sk.get_space(), {1: 0, "ink": 1}) tuds = tuds.add_constraint(c) sk = sk.union(tuds) print sk fsloop = iscc.iscc_communicate("L :=" + str(sk) + "; codegen L;") nloop = fsloop.split('\n') nloop = tiling_v3.postprocess_loop(nloop) lines = fs_pragma(nloop) #Dodatek[2]+1 shift + 1 for k #if extend first shift shoud be one smaller if (Extend): sh = 1 else: sh = 0 loop = imperf_tile.RestoreStatements(lines, Dodatek[0], Dodatek[1], Dodatek[2] + 1, Dodatek[3], Dodatek[5], sh) text_file = open(Dodatek[4], "w") text_file.write(loop) text_file.close() return ""
else: print colored('approx', 'red') Rpow = rpow[0] Rpow = isl.Map(iscc.RepairRk(str(Rpow), 0)) # przesun k do symb print Rpow uds = rel.domain().subtract(rel.range()).coalesce() print "UDS" print uds sk = uds.apply(Rpow).subtract(uds.apply(Rpow).apply(Rplus)).coalesce() sk = sk.insert_dims(isl.dim_type.set, 0, 1) sk = sk.set_dim_name(isl.dim_type.set, 0, "ink") c = isl.Constraint.eq_from_names(sk.get_space(), {"k": -1, "ink": 1}) sk = sk.add_constraint(c) sk = tiling_v3.Project(sk, ["k"]) uds = uds.insert_dims(isl.dim_type.set, 0, 1) uds = uds.set_dim_name(isl.dim_type.set, 0, "ink") c = isl.Constraint.eq_from_names(sk.get_space(), {1: 0, "ink": 1}) uds = uds.add_constraint(c) sk = sk.union(uds).coalesce() print 'Sk' print sk nloop = iscc.iscc_communicate("L :=" + str(sk) + "; codegen L;") print nloop print '--------------------------------------------------------' TILE_S1 = '[T,N,tt,ii,jj] -> ' TILE_S1 += '{[t,i,j,0] : ' tile_j_s1 = '0 + b1 * tt <= t <= b1*(tt+1) + 0 -1 ,T-1 && tt >=0 && '
def fs_rk(rel, rel_plus, uds, LPetit, dane, plik, SIMPLIFY, rap, acc, loop): aprox = 0 rk = rel.power() #Rk if (rk[1] == 0): print "rk approximated..." aprox = 1 rk = rk[0].coalesce() rk = isl.Map(iscc.RepairRk(str(rk), 0)) # przesun k do symb sk = uds.apply(rk).subtract(uds.apply(rk).apply(rel_plus)).coalesce() sq_sk = sk sk = sk.insert_dims(isl.dim_type.set, 0, 1) sk = sk.set_dim_name(isl.dim_type.set, 0, "ink") c = isl.Constraint.eq_from_names(sk.get_space(), {"k": -1, "ink": 1}) sk = sk.add_constraint(c) sk = tiling_v3.Project(sk, ["k"]) sq_sk2 = sk SQ = False if (SQ): sk = get_sq(sq_sk, sq_sk2, uds) else: uds = uds.insert_dims(isl.dim_type.set, 0, 1) uds = uds.set_dim_name(isl.dim_type.set, 0, "ink") c = isl.Constraint.eq_from_names(sk.get_space(), {1: 0, "ink": 1}) uds = uds.add_constraint(c) sk = sk.union(uds).coalesce() #if(SIMPLIFY): sk = imperf_tile.SimplifySlice(sk) rap = rap.insert_dims(isl.dim_type.in_, 0, 1) rap = rap.insert_dims(isl.dim_type.out, 0, 1) rap = rap.set_dim_name(isl.dim_type.in_, 0, 'ik1') rap = rap.set_dim_name(isl.dim_type.out, 0, 'ok1') c = isl.Constraint.eq_from_names(rap.get_space(), {'ik1': -1, 'ok1': 1}) rap = rap.add_constraint(c) rap = rap.coalesce() #print rap sk = sk.apply(rap) print sk if (aprox == 1): if (sk.is_bounded()): print "Approximation (no perfect FS) but Sk is bounded" else: print "Sk is not bounded. The result may not be valid!" else: print 'Rk exact' if (sk.is_bounded()): print 'Sk bounded.' else: print 'Sk NOT bounded' nloop = iscc.iscc_communicate("L :=" + str(sk) + "; codegen L;") # CODEGEN nloop = tiling_v3.postprocess_loop(nloop.split('\n')) lines = tiling_schedule.fs_pragma(nloop) if (acc): lines = openacc.CreateACCCode(lines, loop.var_st) loop = imperf_tile.RestoreStatements(lines, LPetit, dane, 1, 1, [], 1) for i in range(0, 5): if (loop[-1] == '\n'): loop = loop[:-1] loop = loop + "\n" base = os.path.basename(plik) nazwa = os.path.splitext(base)[0] + "_fs" + os.path.splitext(base)[1] text_file = open(nazwa, "w") text_file.write(loop) text_file.close() print nazwa + ' was created.'
def get_sq(sk, sk2, uds): # ---------- Obliczanie SQ d = 2 # tu bedzie wyliczona d i jeszcze q >= 0 sq = sk print sk2 print sk2.lexmin() print sk2.lexmax() z = [] l = sk.dim(isl.dim_type.set) for i in range(0, l): z.append("i" + str(i)) tmp = isl.Set("[k] -> {[" + ",".join(z) + "] : k = 0}") tmp = tmp.intersect(uds).coalesce() sq = sq.union(tmp).coalesce() sq = sq.insert_dims(isl.dim_type.set, 0, 1) sq = sq.set_dim_name(isl.dim_type.set, 0, "q") sq = sq.set_dim_name(isl.dim_type.set, 1, "ii") var_i = sq.get_var_names(isl.dim_type.set)[1] # sys.exit() c = isl.Constraint.eq_from_names(sq.get_space(), { "q": -1, "ii": d, "k": 1 }) sq = sq.add_constraint(c).coalesce() # ----------------------- # ---------- Obliczanie kmax i imax z = sk2.lexmax() z = z.remove_dims(isl.dim_type.set, 2, z.dim(isl.dim_type.set) - 2) z = z.set_dim_name(isl.dim_type.set, 0, "kmax") z = z.set_dim_name(isl.dim_type.set, 1, "imax") z = z.insert_dims(isl.dim_type.set, 0, 1) z = z.set_dim_name(isl.dim_type.set, 0, "q") # q <= d*imax + kmax c = isl.Constraint.ineq_from_names(z.get_space(), { "q": -1, "imax": d, "kmax": 1 }) z = z.add_constraint(c).coalesce() # q <= 0 c = isl.Constraint.ineq_from_names(z.get_space(), {"q": 1}) z = z.add_constraint(c).coalesce() z = z.remove_dims(isl.dim_type.set, 1, z.dim(isl.dim_type.set) - 1) z = z.insert_dims(isl.dim_type.set, 1, l) sq = sq.intersect(z).coalesce() sq = tiling_v3.Project(sq, ["k"]) #if(SIMPLIFY): # sq = imperf_tile.SimplifySlice(sq) return sq
def tile(plik, block, permute, output_file="", L="0", SIMPLIFY="False", perfect_mode=False, parallel_option=False, rplus_mode='', cpus=2): print '' print colored('/\__ _\ /\ == \ /\ __ \ /\ ___\ /\ __ \ ', 'green') print colored('\/_/\ \/ \ \ __< \ \ __ \ \ \ \____ \ \ \/\ \ ', 'green') print colored(' \ \_\ \ \_\ \_\ \ \_\ \_\ \ \_____\ \ \_____\ ', 'green') print colored(' \/_/ \/_/ /_/ \/_/\/_/ \/_____/ \/_____/ ', 'green') print '' print ' An Automatic Parallelizer and Optimizer' print 'based on the ' + colored('TRA', 'green') + 'nsitive ' + colored( 'C', 'green') + 'l' + colored('O', 'green') + 'sure of dependence graphs' print ' traco.sourceforge.net ' print '' DEBUG = True AGGRESSIVE_SIMPLIFY = False # TODO simpl_ub VALIDATION = 0 # levels FSSCHEDULE = 1 # RTILE expermiental INVERSE_TILING = 0 LPetit = "tmp/tmp_petit" + L + ".t" BLOCK = block.split(',') for i in range(len(BLOCK), 10): BLOCK.append(BLOCK[len(BLOCK) - 1]) BLOCK2 = [0, 6, 6] # BLOCK2 = BLOCK linestring = open(plik, 'r').read() lines = linestring.split('\n') if AGGRESSIVE_SIMPLIFY: petit_loop = convert_loop.convert_loop(lines, BLOCK2) BLOCK2 = map(str, BLOCK2) else: petit_loop = convert_loop.convert_loop(lines) file = open(LPetit, 'w') imperf = 0 endloop = 0 startloop = 0 for line in petit_loop: #sprawdz przy okazji jaka petla idealnie czy nie if 'for' in line and not 'endfor' in line: if startloop == 2: imperf = 1 startloop = 1 else: if startloop == 1: startloop = 2 if 'endfor' in line: endloop = 1 if endloop == 1 and 'endfor' not in line and not line.isspace( ) and line != '': imperf = 1 file.write(line + '\n') file.close() start = time.time() loop = Dependence.Kernel_Loop(LPetit) loop.Load_Deps() loop.Load_instrukcje() loop.Preprocess('0') loop.Get_Arrays() end = time.time() elapsed = end - start print "Dependence analysis: time taken: ", elapsed, "seconds." print colored('R', 'green') print loop.isl_rel print colored('domain R', 'green') print loop.isl_rel.domain() print colored('range R', 'green') print loop.isl_rel.range() IS = loop.isl_rel.domain().union(loop.isl_rel.range()) #s = IS.compute_schedule(loop.isl_rel, loop.isl_rel) #print s #sys.exit(0) print loop.dane cl = clanpy.ClanPy() cl.loop_path = plik cl.Load() ################################## # move to clanpy # combine clan with Dependence arr = map(int, loop.dane) arr = sorted(list(set(arr))) i = 0 for i in range(0, len(cl.statements)): cl.statements[i].petit_line = arr[i] cl.statements[i].bounds = GetBounds(petit_loop, cl.statements[i].petit_line, BLOCK2, AGGRESSIVE_SIMPLIFY) i = i + 1 ############################################################ ### R^+ isl_rel = loop.isl_rel #for i in range(0, len(cl.statements)): # print cl.statements[i].petit_line start = time.time() # ************************************************************************** RPLUSUNION = True #RPLUSUNION = False # NESTED strong experimental with Pugh only Valid why? exact_rplus = '-1' isl_relclosure = isl_rel if (RPLUSUNION): islrp = True if (rplus_mode == 'iterate'): islrp = False exact_rplus = True if not isl_rel.is_empty() and rplus_mode != 'remote': if islrp: isl_relclosure = isl_rel.transitive_closure() exact_rplus = isl_relclosure[1] isl_relclosure = isl_relclosure[0] else: isl_relclosure = relation_util.oc_IterateClosure(isl_rel) exact_rplus = True else: #R_UNDER still experimental, requires testing ############################################################################# print colored('R_UNDER', 'green') stline = [] subgraphs = [] isl_relclosure = isl.Map('{[i]->[i] : 1=0}').coalesce() for st in cl.statements: stline.append(st.petit_line) stline.sort() for i in range(0, len(stline)): w = 0 for sg in subgraphs: if stline[i] in sg: # it was used w = 1 if (w == 1): continue mylist = [] mylist.append(stline[i]) for j in range(i + 1, len(stline)): cutrel = '{[' + ','.join([ "a%d" % l for l in range(0, loop.maxl) ]) + ',' + str(stline[i]) + ']->[' + ','.join([ "b%d" % l for l in range(0, loop.maxl) ]) + ',' + str(stline[j]) + '];' cutrel += '[' + ','.join([ "a%d" % l for l in range(0, loop.maxl) ]) + ',' + str(stline[j]) + ']->[' + ','.join([ "b%d" % l for l in range(0, loop.maxl) ]) + ',' + str(stline[i]) + ']}' cutrel = isl.Map(cutrel) cutrel = isl_rel.intersect(cutrel).coalesce() if not cutrel.is_empty(): mylist.append(stline[j]) #mylist.append(maxst) subgraphs.append(mylist) print subgraphs for item in stline: count = 0 for sg in subgraphs: if item in sg: count = count + 1 if count > 1 and item != max(stline): print 'R_UNDER untested, switch RPLUSUNION to true' #exit(1) ii = 0 for sg in subgraphs: # calculate R_UNDER and its R+ ii = ii + 1 print str(ii) + "/" + str(len(subgraphs)) grel = '{' for i in sg: for j in sg: grel += '[' + ','.join([ "a%d" % l for l in range(0, loop.maxl) ]) + ',' + str(i) + ']->[' + ','.join( ["b%d" % l for l in range(0, loop.maxl)]) + ',' + str(j) + '];' grel += '}' grel = isl.Map(grel) grel = isl_rel.intersect(grel).coalesce() gp = grel.transitive_closure() if not gp[1]: print "NOT EXEACT R+" # print "iterate required" # gp = relation_util.oc_IterateClosure(grel) # iterate #else: gp = gp[0] if isl_relclosure.is_empty(): isl_relclosure = gp else: isl_relclosure = isl_relclosure.union(gp).coalesce() ############################################################################# if rplus_mode == 'remote': isl_relclosure, exact_rplus = agent.remote_tc(isl_rel) # ************************************************************************** isl_relplus = isl_relclosure print 'Rplus before' print isl_relplus # lata Pugh - eksperymentalnie #isl_rel = isl_rel.subtract(isl_relplus.apply_range(isl_rel)) print isl_rel #isl_relclosure = isl_rel.transitive_closure()[0] #isl_relplus = isl_relclosure # --------- print 'Rplus after' print isl_relplus end = time.time() elapsed = end - start print "Transitive closure: time taken: ", elapsed, "seconds." isl_ident = isl_rel if not isl_rel.is_empty: isl_ident = isl_rel.identity(isl_rel.get_space()) if (DEBUG and 1 == 0): print 'R+' print isl_relclosure #isl_relclosure = rpp if (DEBUG): color = 'red' if (exact_rplus): color = 'yellow' print colored("!! exact_rplus " + str(exact_rplus), color) isl_relclosure = isl_relclosure.union(isl_ident).coalesce() # R* = R+ u I if (INVERSE_TILING): isl_relclosure = isl_relclosure.fixed_power_val(-1).coalesce() if (DEBUG): print colored("R*", 'green') print isl_relclosure # ************************************************************************** start = time.time() B = (["b%d" % i for i in range(0, loop.maxl)]) vars = [] for st in cl.statements: if (len(st.original_iterators) == loop.maxl): vars = st.original_iterators break if (len(vars) == 0): print 'error 12, propably clan does not work' exit(12) # TODO to make abstract variubles bounds with variables must be also corrected sym_exvars = [] sym_exvars_p = [] print vars for v in vars: sym_exvars.append(v * 2) sym_exvars_p.append(v * 2 + 'p') if (DEBUG and 1 == 0): print sym_exvars print vars isl_symb = isl_rel.get_var_names(isl.dim_type.param) BLOCK = block.split(',') for i in range(len(BLOCK), 10): BLOCK.append(BLOCK[len(BLOCK) - 1]) # ************************************************************************** TILE = [] #isl TILE_STR = [] #string for st in cl.statements: if len(isl_symb) == 0: isl_symb = isl.Map(st.domain_map).get_var_names(isl.dim_type.param) tile = MakeTile(st, vars, sym_exvars, isl_symb, B) tile = ReplaceB(tile, BLOCK) TILE_STR.append(tile) tile = isl.Set(tile) # if statements before st domainv = isl.Set(st.domain_map) print domainv #if len(TILE) == 0: # domainv = isl.Set('[N] -> {[i, j, k, m]: N > 0 and 0 <= i <= -2 + N and 2 + i <= j < N and i < k <= -2 + j and k < m <= -3 - i + j + k and m < j and k < m and j-m < 30}') dimdom = domainv.dim(isl.dim_type.set) domainv = domainv.insert_dims(isl.dim_type.set, dimdom, loop.maxl + 1 - dimdom) tile = tile.intersect(domainv).coalesce() TILE.append(tile) if (DEBUG): DebugPrint('TILE', TILE, cl.statements) # ************************************************************************** TILE_LT = [] TILE_GT = [] for i in range(0, len(cl.statements)): TILE_LT_I = '' TILE_GT_I = '' for j in range(0, len(cl.statements)): l = CompareScat(cl.statements[i].scatering, cl.statements[j].scatering, len(vars)) tile_j = TILE_STR[j] PARTS = tile_j.split(':') for k in range(0, len(sym_exvars)): PARTS[1] = PARTS[1].replace(sym_exvars[k], sym_exvars_p[k]) PARTS[1] = PARTS[1].replace('}', ')}') lex_s_lt = MakeCustomLex( sym_exvars, sym_exvars_p, 'LT', l, cl.statements[i].petit_line > cl.statements[j].petit_line) lex_s_gt = MakeCustomLex( sym_exvars, sym_exvars_p, 'GT', l, cl.statements[i].petit_line < cl.statements[j].petit_line) join_LT = ': exists ' + ','.join( sym_exvars_p) + ' : ( ' + lex_s_lt join_GT = ': exists ' + ','.join( sym_exvars_p) + ' : ( ' + lex_s_gt TILE_LT_IJ = PARTS[0] + join_LT + PARTS[1] TILE_GT_IJ = PARTS[0] + join_GT + PARTS[1] #print TILE_LT_IJ TILE_LT_IJ = isl.Set(TILE_LT_IJ) TILE_GT_IJ = isl.Set(TILE_GT_IJ) if (j == 0): TILE_LT_I = TILE_LT_IJ TILE_GT_I = TILE_GT_IJ else: TILE_LT_I = TILE_LT_I.union(TILE_LT_IJ).coalesce() TILE_GT_I = TILE_GT_I.union(TILE_GT_IJ).coalesce() TILE_LT.append(TILE_LT_I) TILE_GT.append(TILE_GT_I) if (DEBUG): DebugPrint('TILE_LT', TILE_LT, cl.statements) DebugPrint('TILE_GT', TILE_GT, cl.statements) if (INVERSE_TILING): tmpx = TILE_LT[:] TILE_LT = TILE_GT TILE_GT = tmpx # ************************************************************************** TILE_ITR = [] for i in range(0, len(cl.statements)): if not isl_relclosure.is_empty(): TILE_ITRI = TILE[i].subtract( TILE_GT[i].apply(isl_relclosure)).coalesce() else: TILE_ITRI = TILE[i] if (SIMPLIFY): TILE_ITRI = imperf_tile.SimplifySlice(TILE_ITRI) TILE_ITR.append(TILE_ITRI) #print 'R+(TILE_GT)*TILE[i]' #print i # print TILE_GT[i].apply(isl_relclosure).intersect(TILE[i]) if (DEBUG): DebugPrint('TILE_ITR', TILE_ITR, cl.statements) # ************************************************************************** TVLD_LT = [] if not isl_relclosure.is_empty(): for i in range(0, len(cl.statements)): TVLD_LTI = (TILE_LT[i].intersect( TILE_ITR[i].apply(isl_relclosure))).subtract( TILE_GT[i].apply(isl_relclosure)).coalesce() TVLD_LT.append(TVLD_LTI) if (DEBUG): DebugPrint('TVLD_LT', TVLD_LT, cl.statements) # ************************************************************************** TILE_VLD = [] for i in range(0, len(cl.statements)): if not isl_relclosure.is_empty(): TILE_VLDI = TVLD_LT[i].union(TILE_ITR[i]).coalesce() else: TILE_VLDI = TILE_ITR[i] if (SIMPLIFY): TILE_VLDI = imperf_tile.SimplifySlice(TILE_VLDI) TILE_VLD.append(TILE_VLDI) if (DEBUG): DebugPrint('TILE_VLD', TILE_VLD, cl.statements) # ************************************************************************** TILE_VLD_EXT = [] Rapply = tiling_v3.GetRapply(vars, sym_exvars, ','.join(isl_symb + sym_exvars) + ',') for i in range(0, len(cl.statements)): TILE_VLD_EXTI = tiling_v3.Project(TILE_VLD[i].apply(Rapply).coalesce(), sym_exvars) ##################################################################################################################### if AGGRESSIVE_SIMPLIFY: cor_set = '' if (len(isl_symb) > 0): cor_set = '[' + ','.join(isl_symb) + '] -> ' else: cor_set = '' cor_set = cor_set + '{[' + ','.join(sym_exvars) + ',' + ','.join( vars) + ',' + 'v] : ' for k in range(0, i + 1): for j in range(0, len(cl.statements[k].bounds)): compar = ' <= ' add1 = ' - ' add2 = ' + ' if cl.statements[k].bounds[j]['step'] == '-1': add1 = ' + ' add2 = ' - ' compar = ' >= ' cor_set = cor_set + vars[j] + compar + cl.statements[ k].bounds[j]['ub'] + add1 + BLOCK2[j] + " && " cor_set = cor_set + cl.statements[k].bounds[j][ 'lb'] + add2 + BLOCK2[j] + compar + vars[j] + " && " cor_set = cor_set + "(" cor_set = cor_set + " v = " + str( cl.statements[i].petit_line) + " " cor_set = cor_set + ")}" print cor_set cor_set = isl.Set(cor_set) print '**************************' TILE_VLD_EXTI = TILE_VLD_EXTI.intersect(cor_set) ##################################################################################################################### TILE_VLD_EXT.append(TILE_VLD_EXTI) if (DEBUG): DebugPrint('TILE_VLD_EXT', TILE_VLD_EXT, cl.statements) # ************************************************************************** # TIME TO SCATTER - TO HONOUR ORDER OF STATEMENTS IN IMPERFECTLY NESTED LOOPS RMaps = [] for i in range(0, len(cl.statements)): RMap = '{' lbx = 0 ubx = i + 1 if (INVERSE_TILING): lbx = i ubx = len(cl.statements) for j in range(lbx, ubx): # to przy odwrotnym tilngu moze trzeba poprawic RMap = RMap + '[' + ','.join(sym_exvars + vars) + ',' + str( cl.statements[j].petit_line) + '] -> [' scati = fix_scat(cl.statements[i].scatering, loop.maxl) scatj = fix_scat(cl.statements[j].scatering, loop.maxl) combo = [ x for t in zip(scati + scatj, sym_exvars + vars) for x in t ] # obled RMap = RMap + ','.join(combo) + ',' + str( cl.statements[j].petit_line) + ']; ' # normalize j RMap = RMap[:-2] + '}' Rmap = isl.Map(RMap) RMaps.append(Rmap) if (DEBUG): DebugPrint('RMaps', RMaps, cl.statements) # ************************************************************************** for i in range(0, len(cl.statements)): TILE_VLD_EXT[i] = TILE_VLD_EXT[i].apply(RMaps[i]).coalesce() if (DEBUG): DebugPrint('TILE_VLD_EXT after Map', TILE_VLD_EXT, cl.statements) TILE_VLD_EXT_union = TILE_VLD_EXT[0] for i in range(1, len(cl.statements)): TILE_VLD_EXT_union = TILE_VLD_EXT_union.union( TILE_VLD_EXT[i]).coalesce() if (DEBUG): print colored('TILE_VLD_EXT to CodeGen', 'green') print TILE_VLD_EXT_union #if(SIMPLIFY): #TILE_VLD_EXT_union= imperf_tile.SimplifySlice(TILE_VLD_EXT_union) # ************************************************************************** # Optional Schedule s = ','.join(["i%d" % i for i in range(1, loop.maxl * 4 + 2)]) # RFS ss = s in_ = s.split(',') symb = '' if (len(isl_symb) > 0): symb += '[' + ','.join(isl_symb) + ']' + '->' RSched = symb + '{[' + s + '] -> [' RValid = RSched # RFS RFS = RSched # ***************************************************** LOOP SKEWING print colored('Loop skewing testing...', 'green') sdel = isl_rel.deltas() inp = [] for i in range(0, sdel.dim(isl.dim_type.set)): inp.append("i" + str(i)) stest = "{[" + ",".join(inp) + "] : " + inp[1] + " < 0 }" stest = isl.Set(stest) sdel = stest.intersect(sdel).coalesce() if (sdel.is_empty()): print colored('Found: i2 -> i2 + i4', 'yellow') s = s.replace('i2', 'i2 + i4') else: print colored('Failed.', 'yellow') #s = s.replace('i4', 'i6') #s = s.replace('i2', 'i2 + 2*i4') #s = s.replace('i', 'i8') #s = s.replace('i10', 'i10 + i8') #s = s.replace('i6', '2*i2 + i4 + i6') # ***************************************************** LOOP SKEWING # ***************************************************** DECREMENTATION index_arr = numpy.zeros(shape=(len(cl.statements), loop.maxl)) for k in range(0, loop.maxl): for i in range(0, len(cl.statements)): if (k < len(cl.statements[i].bounds)): index_arr[i][k] = cl.statements[i].bounds[k]['step'] print colored('step array (st,loop)', 'green') print numpy.matrix(index_arr) for k in range(0, loop.maxl): vec = index_arr[:, k] dec = 1 for i in range(0, len(cl.statements)): if (vec[i] != -1): dec = 0 break if (dec == 0): continue ind = str(2 * loop.maxl + 2 * (k + 1)) print colored('decrementation on ' + str(k + 1) + ' loop', 'yellow') s = s.replace('i' + ind, '-i' + ind) # TODO rozdzielic na gniazda i v w przyszlosci # ***************************************************** RSched += s + '] : ' RFS += ss + '] : 1=1 }' RSched = RSched + copyconstr.GetConstrSet(in_, TILE_VLD_EXT_union) + " }" print 'RSCHEDULE' print RSched Rsched = isl.Map(RSched) print 'VALIDATION CHECKING ' if (not isl_rel.is_empty() and 1 == 1): s_in = ','.join(["i%d" % i for i in range(1, loop.maxl * 4 + 2)]) sout = ','.join(["i%d'" % i for i in range(1, loop.maxl * 4 + 2)]) out_ = sout.split(',') i1 = in_[2 * loop.maxl + 1:4 * loop.maxl + 1:2] + [in_[loop.maxl * 4]] i2 = out_[2 * loop.maxl + 1:4 * loop.maxl + 1:2] + [in_[loop.maxl * 4]] RValid += sout + '] : ' DomR = isl_rel.domain() RValid += copyconstr.GetConstrSet( i1, DomR) + ' && ' + copyconstr.GetConstr(i1, i2, isl_rel) s_in_ex = ','.join(["ex%d" % i for i in range(1, loop.maxl * 4 + 2)]) s_out_ex = ','.join(["ex%d'" % i for i in range(1, loop.maxl * 4 + 2)]) ex_sin = s_in_ex.split(',') ex_sout = s_out_ex.split(',') RValid += ' && exists ' + s_in_ex + ',' + s_out_ex + ' : (' RValid += ' ( ' + tiling_v3.CreateLex(ex_sin, ex_sout) + ' ) && ' RValid += ' ( ' + copyconstr.GetConstr(in_, ex_sin, Rsched) + ' ) && ' RValid += ' ( ' + copyconstr.GetConstr(out_, ex_sout, Rsched) + ' ) ' RValid += ' ) }' RValid = isl.Map(RValid).coalesce() if (RValid.is_empty()): print colored('*** VALIDATION OK ***', 'green') else: print colored('*** VALIDADION FAILED ***', 'red') print colored(RValid, 'green') if (FSSCHEDULE == 0): print RValid sys.exit(0) for st in cl.statements: z = st.domain_map z = isl.Set(z) # czy wszystkie z domain sa w TVLD_EXT VLDUNION RELATION == v # I nalezy do TVLD_EXT and exists i,j,v i nalezy do domain_map i i,j,v != I ma byc pusty VLD_VAL = Rsched.range() if (VALIDATION > 0): tiling5_valid.Valid1(Rsched, symb, in_, out_, s_in, sout, loop) else: print "OK" # ************************************************************************** #### DISCOVER PARALLELISM -- empty # ii, jj -> ii, jj' : not jj = jj' print colored('Parallelism searching', 'green') s = ','.join(["i%d" % i for i in range(1, loop.maxl * 4 + 2)]) in_ = s.split(',') sprim = ','.join(["i%d'" % i for i in range(1, loop.maxl * 4 + 2)]) out_ = sprim.split(',') Rel_base = symb + '{[' + s + '] -> [' + sprim + '] : ' #i1 = domain R 12 = R(i1) ii,i1 nalezy do VLD_EXT i'i',i2 nalezy do VLDEXT i ogr. ponizej np ii2 <> ii2' ii1 = ii1' relacja par_loop = [] if (not isl_rel.is_empty() and 1 == 1): delta = isl_rel.deltas() chkc = isl.Set("{[0," + ",".join(vars) + "]}") delta = delta.subtract(chkc) for i in range(0, loop.maxl * 4, 2): j = -1 print 'c' + str(i + 1), Rel = Rel_base tmp = '' for j in range(0, i): tmp += in_[j] + ' = ' + out_[j] + ' && ' tmp += ' not ( ' + in_[j + 1] + ' = ' + out_[ j + 1] + ' && ' + in_[j + 2] + ' = ' + out_[j + 2] + ' ) && ' Rel += tmp Rel += copyconstr.GetConstrSet( i1, DomR) + ' && ' + copyconstr.GetConstr(i1, i2, isl_rel) Rel += ' && ( ' + copyconstr.GetConstrSet(in_, VLD_VAL) + ' ) && ' Rel += ' ( ' + copyconstr.GetConstrSet(out_, VLD_VAL) + ' ) ' Rel += ' }' #print Rel Rel = isl.Map(Rel) if (i == 0): Rel = delta if (Rel.is_empty()): print colored('found!', 'green') par_loop.append('c' + str(i + 1)) # break else: print 'no!' end = time.time() elapsed = end - start print "Algorithm: time taken: ", elapsed, "seconds." # ************************************************************************** vars = map(str, vars) start = time.time() ast = 0 if (ast == 1): loop_x = iscc.isl_ast_codegen_map(Rsched) else: loop_x = iscc.iscc_communicate("L :=" + str(Rsched) + "; codegen L;") print loop_x # ************************************************************************** lines = loop_x.split('\n') loop_str = [] for line in lines: if line.endswith(');'): tab = imperf_tile.get_tab(line) line = line.replace(' ', '') line = line[:-2] line = line[1:] arr = line.split(',') petit_st = arr[4 * loop.maxl] s = '' for i in range(0, len(cl.statements)): # TODO if petit_st has 'c' get all statements make if from petit_line and insert to s, solution for loop over st if 'c' in petit_st: combo_st = '{' for j in range(0, len(cl.statements)): combo_st += '\n' + tab combo_st += 'if( ' + petit_st + ' == ' + str( cl.statements[j].petit_line ) + ' ) ' + cl.statements[j].body s = combo_st + '\n' + tab + '}' elif cl.statements[i].petit_line == int( petit_st): # st.petit_line s = cl.statements[i].body for i in range( 0, len(vars) ): # todo oryginal iterators for loops with mixed indexes subt = arr[2 * loop.maxl + 2 * i + 1] if (('+' in subt) or ('-' in subt)): subt = '(' + subt + ')' s = re.sub(r'\b' + vars[i] + r'\b', subt, s) loop_str.append(tab + s) else: line = line.replace('for (int', 'for(') loop_str.append(line) end = time.time() elapsed = end - start print "Code Generation: time taken: ", elapsed, "seconds.\n\n" #loop_str = '\n'.join(loop_str) filePaths = glob.glob(plik) if (output_file != ""): nazwa = output_file else: for filePath in filePaths: base = os.path.basename(filePath) nazwa = os.path.splitext(base)[0] + "_tiling" + os.path.splitext( base)[1] text_file = open(nazwa, "w") for line in loop_str: if (len(par_loop) > 0): if ('for( ' + par_loop[0] + ' ' in line): print imperf_tile.get_tab(line) + colored( '#pragma omp parallel for', 'green') text_file.write( imperf_tile.get_tab(line) + '#pragma omp parallel for' + '\n') print line text_file.write(line + '\n') text_file.close() print 'Output written to: ' + nazwa for d in loop.Deps: del d.Relation sys.exit(0) ################################################################################################### if (FSSCHEDULE): rtile = tiling_schedule.get_RTILE(TILE_VLD_EXT_union, sym_exvars, isl_rel, True) #Rsched.Range() rtile_ii = rtile #print rtile_ii for i in range(0, loop.maxl): rtile_ii = rtile_ii.remove_dims(isl.dim_type.in_, 2 * loop.maxl - i * 2 - 2, 1) rtile_ii = rtile_ii.remove_dims(isl.dim_type.out, 2 * loop.maxl - i * 2 - 2, 1) print colored('RTILE', 'green') print rtile sys.exit(0) if islrp: rtileplus, exact = rtile.transitive_closure() else: rtileplus = relation_util.oc_IterateClosure(rtile) exact = 1 print colored('RTILE+', 'green') print rtileplus if (exact != 1): print colored('RTILE+ approx', 'yellow') else: print colored('RTILE+ exact', 'green') # tiling_v2.DynamicRTILE(rtile, Rsched.range(), loop.maxl, cl, vars, RFS) try: p = int(cpus) # or int except ValueError: print 'Bad cpus parameter. ' sys.exit(0) FI = symb + ' {[' + ','.join( sym_exvars) + ',v] -> [p] : (exists k : (' item = '' for i in range(0, p): item = item + ' (p=' + str(i) + ' ' + ' && ' + sym_exvars[ 0] + ' - (2k + ' + str(i) + ') = 0 ) || ' FI += item[:-3] + ' )) &&' vv = ["i%d" % i for i in range(1, loop.maxl * 4 + 2)] s_in = ','.join(vv) s_out = ','.join(["i%d" % i for i in range(2, loop.maxl * 2 + 1, 2) ]) + ',' + vv[len(vv) - 1] rmap_fi = '{[' + s_in + '] -> [' + s_out + ']}' rmap_fi = isl.Map(rmap_fi) II_SET = TILE_VLD_EXT_union.apply(rmap_fi).coalesce() print colored('II_SET', 'green') print II_SET FI += copyconstr.GetConstrSet(sym_exvars + ['v'], II_SET) + '}' FI = isl.Map(FI).coalesce() print colored('FI', 'green') print FI RPROC = symb + '{[' + ','.join(sym_exvars) + ',v] -> [' + ','.join( sym_exvars_p) + ',vp] : ' domRTILE = rtile_ii.domain().coalesce() RPROC += copyconstr.GetConstrSet( sym_exvars + ['v'], domRTILE) + ' && ' + copyconstr.GetConstr( sym_exvars + ['v'], sym_exvars_p + ['vp'], rtile_ii) RPROC += ' && exists p,pp : ( not(p=pp) && ' + copyconstr.GetConstr( sym_exvars + ['v'], ['p'], FI) + ' && ' + copyconstr.GetConstr( sym_exvars_p + ['vp'], ['pp'], FI) + ' ) }' #print RPROC RPROC = isl.Map(RPROC).coalesce() print colored('RPROC', 'green') print RPROC s = ','.join(["i%d" % i for i in range(0, loop.maxl + 1)]) sv = s.split(',') s1 = ','.join(["o%d" % i for i in range(0, loop.maxl + 1)]) sv1 = s1.split(',') s2 = ','.join(["ex%d" % i for i in range(0, loop.maxl + 1)]) sve = s2.split(',') R_RESIDUAL = symb + '{[' + s + '] -> [' + s1 + '] : ' R_RESIDUAL += copyconstr.GetConstrSet( sv, RPROC.domain().coalesce()) + '&& ' R_RESIDUAL += copyconstr.GetConstr( sv, sv1, RPROC) + '&& not exists ' + s2 + ' : (' R_RESIDUAL += tiling_v3.CreateLex( sve, sv) + ' && ' + copyconstr.GetConstr(sve, sv1, RPROC) + ')}' R_RESIDUAL = isl.Map(R_RESIDUAL).coalesce() print colored('R_RESIDUAL', 'green') print R_RESIDUAL irp = R_RESIDUAL.fixed_power_val(-1) R_P_RESIDUAL = symb + '{[' + ','.join( sym_exvars) + ',v] -> [p,' + ','.join(sym_exvars_p) + ',vp] : ' R_P_RESIDUAL += copyconstr.GetConstr( sym_exvars_p + ['vp'], ['p'], FI) + ' && ' + copyconstr.GetConstr( sym_exvars + ['v'], sym_exvars_p + ['vp'], irp) + ' }' R_P_RESIDUAL = isl.Map(R_P_RESIDUAL) print colored('R_P_RESIDUAL', 'green') print R_P_RESIDUAL