Exemple #1
0
def EOR(num): # bitwise Exclusive OR
	# Write to register A
	RegA.write_register(num)
	
	# Activate EOR output
	ALU.unset_all()
	ALU.set_XOR(1)
	
	# Read result
	RegADD.clock_data()
	EOR = RegADD.read_register()
	
	# Store result in Accumulator
	LDA(EOR)
Exemple #2
0
def ORA(num): # bitwise OR with Accumulator
	# Write to register A
	RegA.write_register(num)
	
	# Activate OR output
	ALU.unset_all()
	ALU.set_OR(1)
	
	# Read result
	RegADD.clock_data()
	OR = RegADD.read_register()
	
	# Store result in Accumulator
	LDA(OR)
Exemple #3
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def ROR(): # ROtate Right
	# Move accumulator val to Reg A
	RegA.write_register(STA())
	
	# Activate AND output
	ALU.unset_all()
	ALU.set_SR(1)
	
	# Read result
	RegADD.clock_data()
	ROR = RegADD.read_register()
	
	# Store result in Accumulator
	LDA(ROR)
Exemple #4
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def counter_test():
	numA = 1
	numB = 1
	
	while numB < 256:
		write_register(numA, numB)
		RegADD.clock_data()
		result = RegADD.read_register() + (ALU.read_C_OUT() << 8)
		print(numA, " +", numB, " = ", result)
		if result != (numA + numB):
			print("NumA: ", numA)
			print("Numb: ", numB)
			print("NumA: ", result)
			break
		numB += 1
		time.sleep(delayTime)
Exemple #5
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def LSR(): # Logical Shift Right
	# Move accumulator val to Reg A
	RegA.write_register(STA())
	
	# Clear the carry, so we shift in zeros
	CLC()
	
	# Activate AND output
	ALU.unset_all()
	ALU.set_SR(1)
	
	# Read result
	RegADD.clock_data()
	SR = RegADD.read_register()
	
	# Store result in Accumulator
	LDA(SR)
Exemple #6
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def ADC(addend): # ADd with Carry
	# Write to register A
	RegA.write_register(addend)
	
	# Activate Adder Output
	ALU.unset_all()
	ALU.set_ADD(1)
	
	# Read result
	C_OUT = ALU.read_C_OUT()
	RegADD.clock_data()
	SUM = RegADD.read_register()
	
	# Store result in Accumulator
	LDA(SUM)
	
	return(C_OUT)
Exemple #7
0
def AND(num): # bitwise AND with accumulator
	# Write to register A
	RegA.write_register(num)
	
	# Activate AND output
	ALU.unset_all()
	ALU.set_AND(1)
	
	# Read result
	C_OUT = ALU.read_C_OUT()
	RegADD.clock_data()
	AND = RegADD.read_register()
	
	# Store result in Accumulator
	LDA(AND)

	return(C_OUT)