def Sub(num1, num2):
result = 0
if (num1 - num2) < 0: result -= 65536
# Split the 16 bit input subtrahend into two 8 bit integers
num2lo = extract_byte(num2, 'low')
num2hi = extract_byte(num2, 'high')
# Invert the subtrahend
OP.CLC()
RegB.write_inverted_register(num2lo)
temp = OP.ADC(0)
num2lo = OP.STA()
RegB.write_inverted_register(num2hi)
temp = OP.ADC(0)
num2hi = OP.STA()
# Reconstruct the subtrahend
num2 = (num2hi << 8) + num2lo
if globals.debug == True: print("Inverted: ", bin(num2))
# Add 1 to the subtrahend to find the two's complement
num2 = Add(num2, 1)
if globals.debug == True: print("Incremented: ", bin(num2))
# Correct for large numbers
if globals.debug == True: print("Num1: ", num1, "Num2: ", num2)
result += (Add(num1, num2)) & 0xFFFF
return(result)
def Sub(num1, num2): result = 0 if (num1 - num2) < 0: result -= 256 # Invert the subtrahend OP.CLC() RegB.write_inverted_register(num2) temp = OP.ADC(0) num2 = OP.STA() # Add 1 to the subtrahend to find the two's complement num2 = Add(num2, 1) result += (Add(num1, num2)) & 0xFFFF return(result)
def SBC(subtrahend): # SuBtract with Carry # Locally store Accumulator minuend = STA() # Invert the subtrahend # RegB.write_inverted_register(subtrahend) RegB.write_inverted_register(subtrahend) # Add 1 to the inverted subtrahend. Result is 2's complement ADC(1) twos_comp = STA() # Add the result of step 2 to the minuend LDA(minuend) ADC(twos_comp) C_OUT = ALU.read_C_OUT() return(C_OUT)
