def execAnd_sr64(binary):
inst = 'AND '
rdKey = utilFunc.getRegKeyByStringKey(binary[27:32])
rnKey = utilFunc.getRegKeyByStringKey(binary[22:27])
rmKey = utilFunc.getRegKeyByStringKey(binary[11:16])
inst += 'x' + str(rdKey) + ', x' + str(rnKey) + ', x' + str(rmKey) + ', '
rnValue = utilFunc.getRegValueByStringkey(binary[22:27], '0')
immKey = binary[16:22]
immvalue = int(immKey, 2) # amount
rmValue = utilFunc.getRegValueByStringkey(binary[11:16], '0')
shifttype = binary[8:10]
temp = ''
if shifttype == "00":
temp = utilFunc.lsl(rmValue[0:64], immvalue)
inst += 'LSL'
elif shifttype == "01":
temp = utilFunc.lsr(rmValue[0:64], immvalue)
inst += 'LSR'
elif shifttype == "10":
temp = utilFunc.asr(rmValue[0:64], immvalue)
inst += 'ASR'
else:
temp = utilFunc.ror(rmValue[0:64], immvalue)
inst += 'ROR'
inst += ' #' + str(immvalue)
to_store = utilFunc.logical_and(temp, rnValue[0:64]).zfill(const.REG_SIZE)
utilFunc.finalize(rdKey, to_store, inst, '0')
def execAnd_sr64(binary):
inst = 'AND '
rdKey = utilFunc.getRegKeyByStringKey(binary[27:32])
rnKey = utilFunc.getRegKeyByStringKey(binary[22:27])
rmKey = utilFunc.getRegKeyByStringKey(binary[11:16])
inst += 'x' + str(rdKey) + ', x' + str(rnKey) + ', x' + str(rmKey) + ', '
rnValue = utilFunc.getRegValueByStringkey(binary[22:27], '0')
immKey = binary[16:22]
immvalue = int(immKey, 2) # amount
rmValue = utilFunc.getRegValueByStringkey(binary[11:16], '0')
shifttype = binary[8:10]
temp = ''
if shifttype == "00":
temp = utilFunc.lsl(rmValue[0:64], immvalue)
inst += 'LSL'
elif shifttype == "01":
temp = utilFunc.lsr(rmValue[0:64], immvalue)
inst += 'LSR'
elif shifttype == "10":
temp = utilFunc.asr(rmValue[0:64], immvalue)
inst += 'ASR'
else:
temp = utilFunc.ror(rmValue[0:64], immvalue)
inst += 'ROR'
inst += ' #' + str(immvalue)
to_store = utilFunc.logical_and(temp, rnValue[0:64]).zfill(const.REG_SIZE)
utilFunc.finalize(rdKey, to_store, inst, '0')
def fetchOp2_sr(rmVal, shiftType, amt, instr):
if shiftType == "00":
op2 = utilFunc.lsl(rmVal, amt)
instr += 'LSL'
elif shiftType == "01":
op2 = utilFunc.lsr(rmVal, amt)
instr += 'LSR'
elif shiftType == "10":
op2 = utilFunc.asr(rmVal, amt)
instr += 'ASR'
return op2, instr
def fetchOp2_sr(rmVal, shiftType, amt, instr):
if shiftType == "00":
op2 = utilFunc.lsl(rmVal, amt)
instr += 'LSL'
elif shiftType == "01":
op2 = utilFunc.lsr(rmVal, amt)
instr += 'LSR'
elif shiftType == "10":
op2 = utilFunc.asr(rmVal, amt)
instr += 'ASR'
return op2, instr
def execLslLsr_i64(binary):
rdKey, rnKey, rnVal, immr, imms = getFields_i(binary)
immrVal = int(immr,2)
immsVal = int(imms,2)
if(imms == '111111'):
#LSR
shiftVal = immrVal
instr = 'LSR x' + str(rdKey) + ", x" + str(rnKey) + ", #" + str(shiftVal)
rd = utilFunc.lsr(rnVal, shiftVal)
elif(immrVal == immsVal+1):
#LSL
shiftVal = 63-immsVal
instr = 'LSL x' + str(rdKey) + ", x" + str(rnKey) + ", #" + str(shiftVal)
rd = utilFunc.lsl(rnVal, shiftVal)
utilFunc.finalize(rdKey, rd, instr, '0')
def execLslLsr_i32(binary):
rdKey, rnKey, rnVal, immr, imms = getFields_i(binary)
immrVal = int(immr,2)
immsVal = int(imms,2)
if(imms == '011111'):
#LSR
shiftVal = immrVal
instr = 'LSR w' + str(rdKey) + ", w" + str(rnKey) + ", #" + str(shiftVal)
rd = '0' * 32 + utilFunc.lsr(rnVal[32:64], shiftVal)
elif(immrVal == immsVal+1):
#LSL
shiftVal = 63-immsVal
instr = 'LSL w' + str(rdKey) + ", w" + str(rnKey) + ", #" + str(shiftVal)
rd = '0' * 32 + utilFunc.lsl(rnVal[32:64], shiftVal)
utilFunc.finalize(rdKey, rd, instr, '0')
def execLslLsr_i32(binary):
rdKey, rnKey, rnVal, immr, imms = getFields_i(binary)
immrVal = int(immr, 2)
immsVal = int(imms, 2)
if (imms == '011111'):
#LSR
shiftVal = immrVal
instr = 'LSR w' + str(rdKey) + ", w" + str(rnKey) + ", #" + str(
shiftVal)
rd = '0' * 32 + utilFunc.lsr(rnVal[32:64], shiftVal)
elif (immrVal == immsVal + 1):
#LSL
shiftVal = 63 - immsVal
instr = 'LSL w' + str(rdKey) + ", w" + str(rnKey) + ", #" + str(
shiftVal)
rd = '0' * 32 + utilFunc.lsl(rnVal[32:64], shiftVal)
utilFunc.finalize(rdKey, rd, instr, '0')
def execLslLsr_i64(binary):
rdKey, rnKey, rnVal, immr, imms = getFields_i(binary)
immrVal = int(immr, 2)
immsVal = int(imms, 2)
if (imms == '111111'):
#LSR
shiftVal = immrVal
instr = 'LSR x' + str(rdKey) + ", x" + str(rnKey) + ", #" + str(
shiftVal)
rd = utilFunc.lsr(rnVal, shiftVal)
elif (immrVal == immsVal + 1):
#LSL
shiftVal = 63 - immsVal
instr = 'LSL x' + str(rdKey) + ", x" + str(rnKey) + ", #" + str(
shiftVal)
rd = utilFunc.lsl(rnVal, shiftVal)
utilFunc.finalize(rdKey, rd, instr, '0')
def execLsr_r64(binary):
rdKey, rnKey, rmKey, rnVal, rmVal = getFields_r(binary)
instr = 'LSR x' + str(rdKey) + ", x" + str(rnKey) + ", x" + str(rmKey)
rd = utilFunc.lsr(rnVal, int(rmVal[58:64], 2))
utilFunc.finalize(rdKey, rd, instr, '0')
def execLsr_r32(binary):
rdKey, rnKey, rmKey, rnVal, rmVal = getFields_r(binary)
instr = 'LSR w' + str(rdKey) + ", w" + str(rnKey) + ", w" + str(rmKey)
rd = '0' * 32 + utilFunc.lsr(rnVal[32:64], int(rmVal[59:64], 2))
utilFunc.finalize(rdKey, rd, instr, '0')
def execLsr_r64(binary):
rdKey, rnKey, rmKey, rnVal, rmVal = getFields_r(binary)
instr = 'LSR x' + str(rdKey) + ", x" + str(rnKey) + ", x" + str(rmKey)
rd = utilFunc.lsr(rnVal, int(rmVal[58:64], 2))
utilFunc.finalize(rdKey, rd, instr, '0')
def execLsr_r32(binary):
rdKey, rnKey, rmKey, rnVal, rmVal = getFields_r(binary)
instr = 'LSR w' + str(rdKey) + ", w" + str(rnKey) + ", w" + str(rmKey)
rd = '0' * 32 + utilFunc.lsr(rnVal[32:64], int(rmVal[59:64], 2))
utilFunc.finalize(rdKey, rd, instr, '0')
