def add_Hl_rr_c(cpu, opcode, logger):
regInd = (opcode >> 4) & 3
val = cpu.Reg16(regInd)
old = cpu.HL
cpu.HL = cpu.HL + val + (1 if cpu.CFlag else 0)
cpu.SFlag = Bits.signFlag(cpu.HL, bits=16)
cpu.ZFlag = Bits.isZero(cpu.HL)
cpu.HFlag = Bits.halfCarrySub16(old, cpu.HL)
cpu.PVFlag = Bits.overflow(old, cpu.HL, bits=16)
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.set() if (Bits.getNthBit(old, 15) == 1 and
Bits.getNthBit(cpu.HL, 15) == 0) else Bits.reset()
cpu.m_cycles, cpu.t_states = 4, 15
logger.info("ADC HL, {}".format(IndexToReg.translate16Bit(regInd)))
def rlca(cpu, opcode, logger):
cflag = Bits.getNthBit(cpu.A, 7)
cpu.A = Bits.setNthBit(cpu.A << 1, 0, cflag)
cpu.CFlag = Bits.set() if cflag != 0 else Bits.reset()
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("RLCA")
def rra(cpu, opcode, logger):
cflag = Bits.getNthBit(cpu.A, 0)
cpu.A = Bits.setNthBit((cpu.A >> 1), 7, cpu.CFlag)
cpu.CFlag = Bits.set() if cflag == 1 else Bits.reset()
cpu.HFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("RRA")
def srl_r(cpu, opcode, logger):
reg_idx = (opcode & 7)
old_val = cpu.regs[reg_idx]
cpu.regs[reg_idx] = (old_val >> 1)
last_bit = Bits.getNthBit(old_val, 0)
cpu.CFlag = Bits.set() if last_bit == 1 else Bits.reset()
cpu.NFlag = Bits.reset()
cpu.HFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.regs[reg_idx])
cpu.PVFlag = Bits.isEvenParity(cpu.regs[reg_idx])
cpu.SFlag = Bits.reset()
cpu.m_cycles, cpu.t_states = 2, 8
logger.info("SRL {}".format(IndexToReg.translate8Bit(reg_idx)))
def ZFlag(self):
return Bits.getNthBit(self.F, ZF) == 1
def CFlag(self):
return Bits.getNthBit(self.F, CF) == 1
def ZFlag(self):
return Bits.getNthBit(self.F, ZF) == 1
def PVFlag(self):
return Bits.getNthBit(self.F, PVF) == 1
def SFlag(self):
return Bits.getNthBit(self.F, SF) == 1
def HFlag(self):
return Bits.getNthBit(self.F, HF) == 1
def NFlag(self):
return Bits.getNthBit(self.F, NF) == 1
def test_bits_getNthBit_returns_1_for_N_equals_2_and_value_14(self):
self.assertEqual(1, Bits.getNthBit(14, 2))
def lra(cpu, opcode, logger):
cflag = Bits.getNthBit(cpu.A, 7)
cpu.A = Bits.setNthBit((cpu.A << 1), 0, cpu.CFlag)
cpu.CFlag = Bits.set() if cflag == 1 else Bits.reset()
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("LRA")
def XFlag(self):
return Bits.getNthBit(self.F, XF) == 1
def YFlag(self):
return Bits.getNthBit(self.F, YF) == 1
def PVFlag(self):
return Bits.getNthBit(self.F, PVF) == 1
def SFlag(self):
return Bits.getNthBit(self.F, SF) == 1
def HFlag(self):
return Bits.getNthBit(self.F, HF) == 1
def NFlag(self):
return Bits.getNthBit(self.F, NF) == 1
def state(self, flag, flag_bit, flag_name):
state = Bits.getNthBit(flag, flag_bit)
return flag_name if state != 0 else flag_name.lower()
def CFlag(self):
return Bits.getNthBit(self.F, CF) == 1
def test_bits_getNthBit_returns_1_for_N_equals_2_and_value_14(self):
self.assertEquals(1, Bits.getNthBit(14, 2))
def state(self, flag, flag_bit, flag_name):
state = Bits.getNthBit(flag, flag_bit)
return flag_name if state != 0 else flag_name.lower()
