def compile_all_cores(cfg_dir, rtl_root, run_root, target='generic',
flow='vsim', stdout=None, stderr=None):
sim_cc, sim_exe = sim_utils.get_rtl_tools(flow)
for root, d, files in os.walk(cfg_dir):
for f in files:
if not f.endswith('.json'): continue
arch_cfg = os.path.join(root, f)
cfg = read_arch_config(arch_cfg)
tgt_root = os.path.join(rtl_root,'core',cfg.name,cfg.get_tgt_attr())
if not os.path.isdir(tgt_root): continue
arch_md5 = sys_utils.md5_file(arch_cfg)
rtl_path = (os.path.join(rtl_root, 'common'),
os.path.join(rtl_root, 'memory'),
os.path.join(rtl_root, 'top'), tgt_root)
t_wd = get_target_out_dir(cfg.get_tgt_sig(), arch_md5, run_root)
lib_path = os.path.join(t_wd, 'hw-libs')
solver_rtl_gen.generate_rtl_package(
cfg, lib_path, rtl_path=rtl_path,
tb_path = (os.path.join(rtl_root, 'testbench'),),
def_path = (os.path.join(rtl_root, 'define'),),
target=target, tb_module='simd_top_testbench', lib='work')
sim_wd = os.path.join(lib_path, '%s_wd'%flow)
# Check if it is necessary to compile the simulation libraries
check_and_compile_solver_rtl(lib_path, sim_wd, flow, sim_cc,
stdout=stdout, stderr=stderr)
def run_solver_bin_ar(bin_ar,
arch_config,
rtl_root,
run_root,
sim_out=None,
target='generic',
flow='vsim',
stdout=None,
stderr=None):
global VERBOSE
if not os.access(arch_config, os.R_OK):
raise RuntimeError('Invalid architecture config "%s"' % arch_config)
arch_md5 = sys_utils.md5_file(arch_config)
cfg = read_arch_config(arch_config)
tgt_sig = cfg.get_tgt_sig()
sim_cc, sim_exe = sim_utils.get_rtl_tools(flow)
sys_utils.mkdir_p(os.path.abspath(run_root))
t_wd = get_target_out_dir(cfg.get_tgt_sig(), arch_md5, run_root)
lib_path = os.path.join(t_wd, 'hw-libs')
# If RTL folder does not exist, generate it from config file
if not os.path.isdir(lib_path):
tgt_rtl_root = os.path.join(rtl_root, 'core', cfg.name,
cfg.get_tgt_attr())
rtl_path = (os.path.join(rtl_root,
'common'), os.path.join(rtl_root, 'memory'),
os.path.join(rtl_root, 'top'), tgt_rtl_root)
solver_rtl_gen.generate_rtl_package(
cfg,
lib_path,
rtl_path=rtl_path,
tb_path=(os.path.join(rtl_root, 'testbench'), ),
def_path=(os.path.join(rtl_root, 'define'), ),
target=target,
tb_module='simd_top_testbench',
lib='work')
sim_wd = os.path.join(lib_path, '%s_wd' % flow)
# Check if it is necessary to compile the simulation libraries
check_and_compile_solver_rtl(lib_path,
sim_wd,
flow,
sim_cc,
stdout=stdout,
stderr=stderr)
# Setup application files
clean_solver_rtl_simulation(sim_wd)
app_name = sys_utils.get_path_basename(bin_ar)
setup_solver_mem_files(bin_ar, sim_wd)
# Run the actual simulation
run_solver_rtl_simulation(sim_exe,
sim_wd,
flow,
lib_path,
cfg,
stdout=stdout,
stderr=stderr,
gui=False)
if not sim_out: sim_out = os.path.join(t_wd, 'sim-out', app_name)
move_dump_files(sim_wd, sim_out)
def check_and_synthesis(design, run_dir, tcsh_rc, force, VERBOSE):
syn_hash = {}
for f in design.hdls:
syn_hash[f] = sys_utils.md5_file(f)
for d in design.hdl_dirs:
for f in glob.glob(os.path.join(d, '*.v')):
syn_hash[f] = sys_utils.md5_file(f)
syn_hash_file = os.path.join(run_dir, 'synth_src.hash')
skip_synth = False
if os.path.exists(syn_hash_file):
if VERBOSE: print('Checking existing build in ' + run_dir)
with open(syn_hash_file) as f:
try:
h_cache = json.load(f)
skip_synth = True
ck = h_cache.keys()
if len(ck) != len(syn_hash): skip_synth = False
else:
for f in ck:
if f not in syn_hash or h_cache[f] != syn_hash[f]:
skip_synth = False
except:
skip_synth = False
with open(syn_hash_file, 'w') as f:
json.dump(syn_hash, f)
if not skip_synth or force:
start = time.time()
if VERBOSE: print('Running RTL synthesis with RC')
run_synthesis(tcsh_rc, run_dir, VERBOSE)
if VERBOSE: print('Compiling post-synthesis simulation libraries')
compile_post_sim(tcsh_rc, run_dir)
for f in glob.glob(os.path.join(run_dir, 'rc.log*')):
os.remove(f)
for f in glob.glob(os.path.join(run_dir, 'rc.cmd*')):
os.remove(f)
for f in glob.glob(os.path.join(run_dir, 'nc*.log')):
os.remove(f)
t = time.time() - start
if VERBOSE: print_green('Synthesis finished, elasped time %.2fs' % t)
elif VERBOSE: print('RTL hash matches, skip synthesis and compilation.')
def solver_rtl_implemented(arch_config, run_root, flow):
tgt_md5 = sys_utils.md5_file(arch_config)
cfg = read_arch_config(arch_config)
tgt_sig = cfg.get_tgt_sig()
t_wd = os.path.join(os.path.abspath(run_root), '%s-%s'%(tgt_sig, tgt_md5))
lib_path = os.path.join(t_wd, 'hw-libs')
sim_wd = os.path.join(lib_path, '%s_wd'%flow)
if not os.path.isdir(lib_path): return False
if flow == 'vsim' and not os.path.isdir(os.path.join(sim_wd, 'work')):
return False
elif flow == 'iverilog' and not os.path.isfile(os.path.join(sim_wd,'work')):
return False
return True
def solver_rtl_implemented(arch_config, run_root, flow):
tgt_md5 = sys_utils.md5_file(arch_config)
cfg = read_arch_config(arch_config)
tgt_sig = cfg.get_tgt_sig()
t_wd = os.path.join(os.path.abspath(run_root),
'%s-%s' % (tgt_sig, tgt_md5))
lib_path = os.path.join(t_wd, 'hw-libs')
sim_wd = os.path.join(lib_path, '%s_wd' % flow)
if not os.path.isdir(lib_path): return False
if flow == 'vsim' and not os.path.isdir(os.path.join(sim_wd, 'work')):
return False
elif flow == 'iverilog' and not os.path.isfile(os.path.join(
sim_wd, 'work')):
return False
return True
def compile_all_cores(cfg_dir,
rtl_root,
run_root,
target='generic',
flow='vsim',
stdout=None,
stderr=None):
sim_cc, sim_exe = sim_utils.get_rtl_tools(flow)
for root, d, files in os.walk(cfg_dir):
for f in files:
if not f.endswith('.json'): continue
arch_cfg = os.path.join(root, f)
cfg = read_arch_config(arch_cfg)
tgt_root = os.path.join(rtl_root, 'core', cfg.name,
cfg.get_tgt_attr())
if not os.path.isdir(tgt_root): continue
arch_md5 = sys_utils.md5_file(arch_cfg)
rtl_path = (os.path.join(rtl_root, 'common'),
os.path.join(rtl_root,
'memory'), os.path.join(rtl_root,
'top'), tgt_root)
t_wd = get_target_out_dir(cfg.get_tgt_sig(), arch_md5, run_root)
lib_path = os.path.join(t_wd, 'hw-libs')
solver_rtl_gen.generate_rtl_package(
cfg,
lib_path,
rtl_path=rtl_path,
tb_path=(os.path.join(rtl_root, 'testbench'), ),
def_path=(os.path.join(rtl_root, 'define'), ),
target=target,
tb_module='simd_top_testbench',
lib='work')
sim_wd = os.path.join(lib_path, '%s_wd' % flow)
# Check if it is necessary to compile the simulation libraries
check_and_compile_solver_rtl(lib_path,
sim_wd,
flow,
sim_cc,
stdout=stdout,
stderr=stderr)
def run_solver_bin_ar(bin_ar, arch_config, rtl_root, run_root, sim_out=None,
target='generic', flow='vsim', stdout=None, stderr=None):
global VERBOSE
if not os.access(arch_config, os.R_OK):
raise RuntimeError('Invalid architecture config "%s"'%arch_config)
arch_md5 = sys_utils.md5_file(arch_config)
cfg = read_arch_config(arch_config)
tgt_sig = cfg.get_tgt_sig()
sim_cc, sim_exe = sim_utils.get_rtl_tools(flow)
sys_utils.mkdir_p(os.path.abspath(run_root))
t_wd = get_target_out_dir(cfg.get_tgt_sig(), arch_md5, run_root)
lib_path = os.path.join(t_wd, 'hw-libs')
# If RTL folder does not exist, generate it from config file
if not os.path.isdir(lib_path):
tgt_rtl_root = os.path.join(rtl_root,'core',cfg.name,cfg.get_tgt_attr())
rtl_path = (os.path.join(rtl_root, 'common'),
os.path.join(rtl_root, 'memory'),
os.path.join(rtl_root, 'top'), tgt_rtl_root)
solver_rtl_gen.generate_rtl_package(
cfg, lib_path, rtl_path=rtl_path,
tb_path = (os.path.join(rtl_root, 'testbench'),),
def_path = (os.path.join(rtl_root, 'define'),),
target=target, tb_module='simd_top_testbench', lib='work')
sim_wd = os.path.join(lib_path, '%s_wd'%flow)
# Check if it is necessary to compile the simulation libraries
check_and_compile_solver_rtl(lib_path, sim_wd, flow, sim_cc,
stdout=stdout, stderr=stderr)
# Setup application files
clean_solver_rtl_simulation(sim_wd)
app_name = sys_utils.get_path_basename(bin_ar)
setup_solver_mem_files(bin_ar, sim_wd)
# Run the actual simulation
run_solver_rtl_simulation(sim_exe, sim_wd, flow, lib_path, cfg,
stdout=stdout, stderr=stderr, gui=False)
if not sim_out: sim_out = os.path.join(t_wd, 'sim-out', app_name)
move_dump_files(sim_wd, sim_out)