def print_top(seed, f=sys.stdout):
np.random.seed(seed)
DCLK_N = 10
DIN_N = (40 * 1 + 1)
DOUT_N = 1
top_harness_clk(DCLK_N, DIN_N, DOUT_N)
bufgces, slices = gen_sites()
orig_bufgces = list(bufgces)
np.random.shuffle(bufgces)
np.random.shuffle(slices)
bufg_prob = np.random.randint(15, 20)
N = 256
M = 16
for m in range(M):
print(
"module layer_1_%d(input [31:0] clk, input [71:0] cen, input d, output q);"
% m,
file=f)
print(" wire [%d:0] r;" % N, file=f)
print(" assign r[0] = d;", file=f)
print(" assign q = r[%d];" % N, file=f)
print("", file=f)
for i in range(N):
if N == 0 and len(slices) > 0:
loc = slices.pop()
print("(* LOC=\"%s\" *)" % loc, file=f)
print(
" FDCE ff_%d (.C(clk[%d]), .CLR(1'b0), .CE(cen[%d]), .D(r[%d]), .Q(r[%d]));"
% (i, (i * 32) // N, np.random.randint(72), i, i + 1),
file=f)
print("endmodule", file=f)
print("""
module roi(input [{DCLK_N}-1:0] clk, input [{DIN_N}-1:0] din, output [{DOUT_N}:0] dout);
wire [39:0] cen;
wire d;
wire q;
assign cen = din[0+:40];
assign d = din[40+:1];
assign dout = q;
""".format(DCLK_N=DCLK_N, DIN_N=DIN_N, DOUT_N=DOUT_N))
num_inputs = np.random.randint(8, 40)
print(" wire [511:0] clk_int;", file=f)
print(" wire [71:0] cen_int;", file=f)
for start_idx in range(0, num_inputs, DCLK_N):
end_idx = min(start_idx + DCLK_N, num_inputs) - 1
end_clk_idx = min(DCLK_N, num_inputs - start_idx) - 1
print(
" assign clk_int[{end_idx}:{start_idx}] = clk[{end_clk_idx}:0];"
.format(start_idx=start_idx,
end_idx=end_idx,
end_clk_idx=end_clk_idx),
file=f)
print(" assign cen_int[%d:0] = cen;" % (num_inputs - 1), file=f)
print(" assign cen_int[71:64] = 8'hFF;", file=f)
bufgces = list(orig_bufgces)
np.random.shuffle(bufgces)
for i in range(num_inputs, 512):
a = np.random.randint(num_inputs)
b = None
while b is None or b == a:
b = np.random.randint(num_inputs)
c = None
while c is None or c == a or c == b:
c = np.random.randint(num_inputs)
bg = None
if len(bufgces) > 0:
bg = bufgces.pop()
if bg is not None and np.random.randint(20) >= bufg_prob or (
bg is not None and "DIV" in bg
and np.random.randint(19) >= bufg_prob):
if "DIV" in bg:
print(
" BUFGCE_DIV #(.BUFGCE_DIVIDE(%d), .IS_I_INVERTED(%d), .IS_CE_INVERTED(%d), .IS_CLR_INVERTED(%d)) bufg_%d (.I(clk[%d] ^ clk[%d] ^ clk[%d]), .CLR(!cen[%d]), .CE(cen[%d]), .O(clk_int[%d]));"
% (np.random.randint(1, 9), np.random.randint(2),
np.random.randint(2), np.random.randint(2), i, a, b, c,
np.random.randint(40), np.random.randint(40), i),
file=f)
else:
ctype = np.random.choice(["", "_1"])
params = " #(.IS_I_INVERTED(%d), .IS_CE_INVERTED(%d), .CE_TYPE(\"%s\")) " % (
np.random.randint(2), np.random.randint(2),
np.random.choice(["SYNC", "ASYNC", "HARD_SYNC"
])) if ctype == "" else ""
print(
" BUFGCE%s %s bufg_%d (.I(clk[%d] ^ clk[%d] ^ clk[%d]), .CE(cen[%d]), .O(clk_int[%d]));"
% (ctype, params, i, a, b, c, np.random.randint(40), i),
file=f)
else:
print(" assign clk_int[%d] = clk[%d] ^ clk[%d] ^ clk[%d];" %
(i, a, b, c),
file=f)
if i < 64:
print(" assign cen_int[%d] = cen[%d] ^ cen[%d];" % (i, a, b),
file=f)
print("", file=f)
print(" wire [%d:0] r;" % M, file=f)
print(" assign r[0] = d;", file=f)
print(" assign q = r[%d];" % M, file=f)
for i in range(M):
print(
" layer_1_%d submod_%d(.clk(clk_int[%d +: 32]), .cen(cen_int), .d(r[%d]), .q(r[%d]));"
% (i, i, 32 * i, i, i + 1),
file=f)
print("endmodule", file=f)
def print_top(seed):
np.random.seed(seed)
DCLK_N = 10
DIN_N = (16 * 2 + 8)
DOUT_N = 32
top_harness_clk(DCLK_N, DIN_N, DOUT_N)
print("")
print("""
module roi(input [{DCLK_N}-1:0] clk, input [{DIN_N}-1:0] din, output [31:0] dout);
wire [15:0] sr;
wire [15:0] ce;
wire [7:0] d;
wire [31:0] q;
assign sr = din[0+:16];
assign ce = din[16+:16];
assign d = din[32+:8];
assign dout = q;
""".format(DCLK_N=DCLK_N, DIN_N=DIN_N, DOUT_N=DOUT_N))
N = 150
D = ["d[%d]" % i for i in range(8)]
slices = sorted(gen_sites())
np.random.shuffle(slices)
with open('top.tcl', 'w') as f:
for i in range(N):
sl = slices.pop()
clk = tuple(np.random.randint(DCLK_N, size=2))
wclk = None
while wclk is None or wclk in clk:
wclk = np.random.randint(DCLK_N)
sr = tuple([
"1'b1" if y >= 16 else "sr[%d]" % y
for y in np.random.randint(25, size=2)
])
ce = tuple([
"1'b1" if y >= 16 else "ce[%d]" % y
for y in np.random.randint(25, size=4)
])
we = np.random.randint(16)
def random_fftype(mode):
if mode == 0:
return np.random.choice(["NONE", "FDSE", "FDRE"])
elif mode == 1:
return np.random.choice(["NONE", "FDPE", "FDCE"])
elif mode == 2:
return np.random.choice(["NONE", "LDPE", "LDCE"])
def random_bit():
return np.random.choice(D)
def random_data(width):
return "{%s}" % (", ".join(
[random_bit() for k in range(width)]))
#fftypes = [random_fftype(ffmode[j // 8]) for j in range(16)]
fftypes = ["NONE" for j in range(16)]
dimux = []
mode = []
ram_legal = True
for lut in "HGFEDCBA":
choices = ["LOGIC"]
if len(dimux) >= 2 and dimux[1] == 'SIN':
mode.append("SRL32")
dimux.append("SIN")
continue
if lut == "H":
choices += ["RAMD64", "RAMS64", "RAMD32", "SRL16", "SRL32"]
else:
if mode[0][0:3] != "RAM":
choices += ["SRL16", "SRL32"]
if ram_legal:
choices.append(mode[0])
p = [0.1]
for j in range(1, len(choices)):
p.append(0.9 / (len(choices) - 1))
if len(choices) == 1:
p[0] = 1
next_mode = np.random.choice(choices, p=p)
if len(mode
) > 0 and mode[-1] == "SRL32" and next_mode == "SRL32":
dimux.append(np.random.choice(["DI", "SIN"], p=[0.2, 0.8]))
else:
dimux.append("DI")
if next_mode[0:3] != "RAM":
ram_legal = False
mode.append(next_mode)
dimux = list(reversed(dimux))
mode = list(reversed(mode))
emit_ultra_slice_memory(f, sl, 'roi/slice{}'.format(i), mode,
dimux)
print(' wire [31:0] d%d;' % i)
print(' ultra_slice_memory #(')
print(' .LOC("%s"),' % sl)
for j in range(8):
print(' .%s_MODE("%s"),' % ("ABCDEFGH" [j], mode[j]))
for lut in "ABCDEFGH":
print(" .%sLUT_INIT(64'b%s)," % (lut, "".join(
str(_) for _ in np.random.randint(2, size=64))))
for j in range(16):
print(' .%sFF%s_TYPE("%s"),' %
("ABCDEFGH" [j // 2], "2" if
(j % 2) == 1 else "", fftypes[j]))
print(" .FF_INIT(16'b%s)," % "".join(
str(_) for _ in np.random.randint(2, size=16)))
for j1 in "ABCDEFGH":
for j2 in ("1", "2"):
print(' .FFMUX%s%s("%s"),' %
(j1, j2, np.random.choice(["F7F8", "D6", "D5"])))
for j in "ABCDEFGH":
print(' .OUTMUX%s("%s"),' %
(j, np.random.choice(["F7F8", "D6", "D5"])))
for j in range(7):
print(' .DIMUX%s("%s"),' % ("ABCDEFG" [j], dimux[j]))
print(" .WCLKINV(1'd%d)," % np.random.randint(2))
waused = np.random.randint(4)
print(" .WA6USED(1'd%d)," % (1 if waused > 0 else 0))
print(" .WA7USED(1'd%d)," % (1 if waused > 1 else 0))
print(" .WA8USED(1'd%d)," % (1 if waused > 2 else 0))
print(" .CLKINV(2'd%d)," % np.random.randint(4))
print(" .SRINV(2'd%d)" % np.random.randint(4))
print(' ) slice%d (' % i)
for j in range(1, 7):
print(" .A%d(%s)," % (j, random_data(8)))
print(" .I(%s)," % random_data(8))
print(" .X(%s)," % random_data(8))
print(" .CLK({clk[%d], clk[%d]})," % clk[0:2])
print(" .WCLK(clk[%d])," % wclk)
print(" .SR({%s, %s})," % sr)
print(" .CE({%s, %s, %s, %s})," % ce[0:4])
print(" .WE(ce[%d])," % we)
print(" .O(d%d[7:0])," % i)
print(" .Q(d%d[15:8])," % i)
print(" .Q2(d%d[23:16])," % i)
print(" .MUX(d%d[31:24])" % i)
print(' );')
print()
D.clear()
for j in range(8):
D.append("d%d[%d]" % (i, j))
D.append("d%d[%d]" % (i, 24 + j))
if fftypes[2 * j] != "NONE":
D.append("d%d[%d]" % (i, 8 + j))
if fftypes[2 * j + 1] != "NONE":
D.append("d%d[%d]" % (i, 16 + j))
print(" assign q = d%d;" % (N - 1))
print("endmodule")
with open(os.path.join(os.getenv('URAY_DIR'), 'spec',
'slice_memory.v')) as f:
for l in f:
print(l.rstrip())
def print_top(seed):
np.random.seed(seed)
DCLK_N = 10
DIN_N = (16 + 9 + 8 + 8 + 12)
DOUT_N = 4
top_harness_clk(DCLK_N, DIN_N, DOUT_N)
print("""
module roi(input [{DCLK_N}-1:0] clk, input [{DIN_N}-1:0] din, output [{DOUT_N}:0] dout);
wire [15:0] cen;
wire [8:0] wa;
wire [7:0] ra;
wire [7:0] d;
wire [11:0] sel;
wire [3:0] q;
assign cen = din[0+:16];
assign wa = din[16+:9];
assign ra = din[25+:8];
assign d = din[33+:8];
assign sel = din[41+:12];
assign dout = q;
""".format(DCLK_N=DCLK_N, DIN_N=DIN_N, DOUT_N=DOUT_N))
N = 512
print(" wire [3:0] int_d[0:%d-1];" % N)
print(" assign q = int_d[sel];")
def connect(sig, dst, len):
if sig is None:
return []
bit = 0
conns = []
for x in sig:
if type(x) is tuple:
name, width = x
conns.append(".%s(%s[%d +: %d])" % (name, dst, bit, width))
bit += width
else:
conns.append(".%s(%s[%d])" % (x, dst, bit))
bit += 1
return conns
for i in range(N):
ctype = np.random.choice([
"SRL16E", "SRLC32E", "RAM32X1D", "RAM32X1S", "RAM64X1D",
"RAM64X1S", "RAM128X1S", "RAM128X1D", "RAM256X1D", "RAM256X1S",
"RAM512X1S"
])
clockport = None
ceport = None
wraddr = None
rdaddr = None
wdata = None
rdata = None
init_len = None
if ctype in ("SRL16E", "SRLC32E"):
clockport = "CLK"
ceport = "CE"
wdata = ["D"]
rdata = ["Q"]
if ctype == "SRLC32E":
rdata.append("Q31")
rdaddr = [("A", 5)]
init_len = 32
else:
rdaddr = ["A0", "A1", "A2", "A3"]
init_len = 16
elif ctype in ("RAM32X1D", "RAM32X1S"):
clockport = "WCLK"
ceport = "WE"
wdata = ["D"]
wraddr = ["A0", "A1", "A2", "A3", "A4"]
init_len = 32
if ctype == "RAM32X1D":
rdaddr = ["DPRA0", "DPRA1", "DPRA2", "DPRA3", "DPRA4"]
rdata = ["SPO", "DPO"]
else:
rdata = ["O"]
elif ctype in ("RAM64X1D", "RAM64X1S"):
clockport = "WCLK"
ceport = "WE"
wdata = ["D"]
wraddr = ["A0", "A1", "A2", "A3", "A4", "A5"]
init_len = 64
if ctype == "RAM64X1D":
rdaddr = ["DPRA0", "DPRA1", "DPRA2", "DPRA3", "DPRA4", "DPRA5"]
rdata = ["SPO", "DPO"]
else:
rdata = ["O"]
elif ctype in ("RAM128X1S", "RAM128X1D", "RAM256X1D", "RAM256X1S",
"RAM512X1S"):
init_len = int(ctype[3:6])
abits = math.log2(init_len)
clockport = "WCLK"
ceport = "WE"
wdata = ["D"]
if ctype == "RAM128X1S":
wraddr = ["A0", "A1", "A2", "A3", "A4", "A5", "A6"]
else:
wraddr = [("A", abits)]
if ctype[-1] == "D":
rdaddr = [("DPRA", abits)]
rdata = ["SPO", "DPO"]
else:
rdata = ["O"]
else:
assert False, ctype
conns = []
if clockport is not None:
conns.append(".%s(clk[%d])" %
(clockport, np.random.randint(0, 16)))
if ceport is not None:
conns.append(".%s(cen[%d])" % (ceport, np.random.randint(0, 16)))
conns += connect(wraddr, "wa", 9)
conns += connect(rdaddr, "ra", 8)
conns += connect(wdata, "d", 8)
conns += connect(rdata, "int_d[%d]" % i, 4)
print(" %s #(" % ctype)
if init_len is not None:
initdata = np.random.randint(2, size=init_len)
print(" .INIT(%d'b%s)" %
(init_len, "".join([str(_) for _ in initdata])))
print(" ) %s_%d (" % (ctype, i))
print(" %s" % ",\n ".join(conns))
print(" );")
print("endmodule")
def print_top(seed):
np.random.seed(seed)
DCLK_N = 10
DIN_N = (16 * 2 + 7)
DOUT_N = 1
top_harness_clk(DCLK_N, DIN_N, DOUT_N)
print("""
module roi(input [{DCLK_N}-1:0] clk, input [{DIN_N}-1:0] din, output [{DOUT_N}:0] dout);
wire [15:0] rst;
wire [15:0] cen;
wire [6:0] d;
wire q;
assign rst = din[0+:16];
assign cen = din[16+:16];
assign d = din[32+:7];
assign dout = q;
""".format(DCLK_N=DCLK_N, DIN_N=DIN_N, DOUT_N=DOUT_N))
N = 1000
print(" wire [%d:0] int_d;" % N)
print(" assign int_d[6:0] = d;")
print(" assign q = int_d[%d];" % N)
slices = sorted(gen_sites())
for i in range(6, N):
fftype, srsig = np.random.choice(
["FDPE,PRE", "FDCE,CLR", "FDSE,S", "FDRE,R"]).split(",")
sl = slices.pop()
if np.random.ranf() < 0.5:
data = "int_d[%d]" % i
else:
lutsize = np.random.randint(2, 10)
if lutsize > 6:
lutsize = 6
print(" wire lut_q_%d;" % i)
print(
" (* BEL=\"%s%dLUT\" *) (* LOC=\"%s\" *) LUT%d #(" %
(np.random.choice(list("ABCDEFGH")),
np.random.randint(6 if lutsize == 6 else 5, 7), sl, lutsize))
print(" .INIT(%d'h%016x)" %
(2**lutsize, np.random.randint(1,
(2**((2**lutsize) - 1) - 1))))
print(" ) lut_%d (" % i)
for j in range(lutsize):
print(" .I%d(int_d[%d])," % (j, i - j))
print(" .O(lut_q_%d)" % i)
print(" );")
data = "lut_q_%d" % i
print(" (* BEL=\"%sFF%s\" *) (* LOC=\"%s\" *) %s #(" %
(np.random.choice(list("ABCDEFGH")), np.random.choice(
["", "2"]), sl, fftype))
print(" .IS_C_INVERTED(%s)," % np.random.choice(["0", "1"]))
print(" .IS_%s_INVERTED(%s)," %
(srsig, np.random.choice(["0", "1"])))
print(" .INIT(%s)" % np.random.choice(["1'b0", "1'b1"]))
print(" ) ff_%d (" % i)
print(" .C(clk[%d])," % np.random.randint(0, DCLK_N))
print(" .CE(cen[%d])," % np.random.randint(0, 16))
print(" .%s(rst[%d])," % (srsig, np.random.randint(0, 16)))
print(" .D(%s)," % (data))
print(" .Q(int_d[%d])" % (i + 1))
print(" );")
print("endmodule")
def print_top(seed):
np.random.seed(seed)
DCLK_N = 2
DIN_N = 78
DOUT_N = 36
top_harness_clk(DCLK_N, DIN_N, DOUT_N)
print("")
print("""
module roi(input [{DCLK_N}-1:0] clk, input [{DIN_N}-1:0] din, output [35:0] dout);
wire clk1;
wire clk1b;
wire rst;
wire ena;
wire enb;
wire cea;
wire ceb;
wire [13:0] ra;
wire [13:0] wa;
wire [15:0] we;
wire [17:0] wdata;
wire [10:0] sel;
wire [35:0] rdata;
assign clk1 = clk[0];
assign clk1b = clk[1];
assign rst = din[0];
assign ena = din[1];
assign enb = din[2];
assign cea = din[3];
assign ceb = din[4];
assign ra = din[5+:14];
assign wa = din[19+:14];
assign we = din[33+:16];
assign wdata = din[49+:18];
assign sel = din[67+:11];
assign dout = rdata;
""".format(DCLK_N=DCLK_N, DIN_N=DIN_N))
N = 200
print(" wire [71:0] int_d[0:%d-1];" % N)
print(" assign rdata = int_d[sel[10:2]][18 * sel[1:0] +: 18];")
for i in range(N):
read_width_a = np.random.choice(
[0, 1, 2, 4, 9, 18, 36, 72],
p=[0.05, 0.1, 0.1, 0.1, 0.1, 0.1, 0.40, 0.05])
write_width_a = np.random.choice([0, 1, 2, 4, 9, 18, 36])
read_width_b = np.random.choice(
[0, 1, 2, 4, 9, 18, 36], p=[0.05, 0.1, 0.1, 0.1, 0.1, 0.1, 0.45])
write_width_b = np.random.choice([0, 1, 2, 4, 9, 18, 36, 72])
cd = np.random.choice(["INDEPENDENT", "COMMON"])
en_ecc_read = np.random.choice(["FALSE", "TRUE"], p=[0.9, 0.1])
en_ecc_write = np.random.choice(["FALSE", "TRUE"], p=[0.9, 0.1])
if en_ecc_read == "TRUE" or en_ecc_write == "TRUE":
read_width_a = 72
write_width_b = 72
write_mode_a = np.random.choice(
["NO_CHANGE", "READ_FIRST", "WRITE_FIRST"])
write_mode_b = np.random.choice(
["NO_CHANGE", "READ_FIRST", "WRITE_FIRST"])
cascade_order_a = np.random.choice(["NONE", "FIRST", "MIDDLE", "LAST"])
cascade_order_b = np.random.choice(["NONE", "FIRST", "MIDDLE", "LAST"])
# DRC AVAL-165
if read_width_a == 72 or write_width_b == 72:
cascade_order_b = cascade_order_a
write_mode_b = write_mode_a
print(" RAMB36E2 #(")
print(" .CLOCK_DOMAINS(\"%s\")," % cd)
print(" .READ_WIDTH_A(%d)," % read_width_a)
print(" .READ_WIDTH_B(%d)," % read_width_b)
print(" .WRITE_WIDTH_A(%d)," % write_width_a)
print(" .WRITE_WIDTH_B(%d)," % write_width_b)
print(" .WRITE_MODE_A(\"%s\")," % write_mode_a)
print(" .WRITE_MODE_B(\"%s\")," % write_mode_b)
print(" .CASCADE_ORDER_A(\"%s\")," % cascade_order_a)
print(" .CASCADE_ORDER_B(\"%s\")," % cascade_order_b)
print(" .DOA_REG(%d)," % np.random.randint(2))
print(" .DOB_REG(%d)," % np.random.randint(2))
print(" .ENADDRENA(\"%s\")," %
np.random.choice(["FALSE", "TRUE"]))
print(" .ENADDRENB(\"%s\")," %
np.random.choice(["FALSE", "TRUE"]))
print(" .EN_ECC_PIPE(\"%s\")," % en_ecc_read)
print(" .EN_ECC_READ(\"%s\")," % en_ecc_read)
print(" .EN_ECC_WRITE(\"%s\")," % en_ecc_write)
print(" .RDADDRCHANGEA(\"%s\")," %
np.random.choice(["FALSE", "TRUE"]))
print(" .RDADDRCHANGEB(\"%s\")," %
np.random.choice(["FALSE", "TRUE"]))
print(" .SLEEP_ASYNC(\"%s\")," %
np.random.choice(["FALSE", "TRUE"]))
print(" .RSTREG_PRIORITY_A(\"%s\")," %
np.random.choice(["RSTREG", "REGCE"]))
print(" .RSTREG_PRIORITY_B(\"%s\")," %
np.random.choice(["RSTREG", "REGCE"]))
for pin in ("CLKARDCLK", "CLKBWRCLK", "ENARDEN", "ENBWREN",
"RSTRAMARSTRAM", "RSTRAMB", "RSTREGARSTREG", "RSTREGB"):
print(" .IS_%s_INVERTED(%d)," % (pin, np.random.randint(2)))
print(" .INIT_A({18'd%d, 18'd%d})," %
(np.random.randint(2**18), np.random.randint(2**18)))
print(" .INIT_B({18'd%d, 18'd%d})," %
(np.random.randint(2**18), np.random.randint(2**18)))
print(" .SRVAL_A({18'd%d, 18'd%d})," %
(np.random.randint(2**18), np.random.randint(2**18)))
print(" .SRVAL_B({18'd%d, 18'd%d})" %
(np.random.randint(2**18), np.random.randint(2**18)))
print(" ) ram%d (" % i)
print(" .DINADIN({wdata[15:0], wdata[15:0]}),")
print(" .DINPADINP({wdata[17:16], wdata[17:16]}),")
print(" .DOUTADOUT({int_d[%d][31:0]})," % i)
print(" .DOUTPADOUTP({int_d[%d][35:32]})," % i)
print(" .ADDRARDADDR(ra),")
print(" .CLKARDCLK(clk),")
print(" .ADDRENA(ena),")
print(" .ENARDEN(ena),")
print(" .REGCEAREGCE(cea),")
print(" .RSTRAMARSTRAM(rst),")
print(" .RSTREGARSTREG(rst),")
print(" .WEA(%s)," % ("8'b00" if write_width_a == 0
or write_width_b == 72 else "we[7:0]"))
print(" .DINBDIN({wdata[15:0], wdata[15:0]}),")
print(" .DINPBDINP({wdata[17:16], wdata[17:16]}),")
print(" .DOUTBDOUT(int_d[%d][67:36])," % i)
print(" .DOUTPBDOUTP(int_d[%d][71:68])," % i)
print(" .ADDRBWRADDR(wa),")
print(" .CLKBWRCLK(%s)," %
("clkb" if cd == "INDEPENDENT" else "clk"))
print(" .ENBWREN(enb),")
print(" .ADDRENB(enb),")
print(" .REGCEB(ceb),")
print(" .RSTRAMB(rst),")
print(" .RSTREGB(rst),")
print(" .WEBWE(%s)" %
("8'b00" if write_width_b == 0 else
"8'hFF" if en_ecc_write == "TRUE" else "we[15:8]"))
print(" );")
print()
print("endmodule")
def print_top(seed, f=sys.stdout):
bufgces, slices = gen_sites()
orig_bufgces = list(bufgces)
np.random.shuffle(bufgces)
np.random.shuffle(slices)
DCLK_N = 10
DIN_N = (DCLK_N * 1 + 1)
DOUT_N = 1
top_harness_clk(DCLK_N, DIN_N, DOUT_N)
bufg_prob = np.random.randint(15, 20)
N = 256
M = np.random.randint(16)
for m in range(M):
print(
"module layer_1_%d(input [31:0] clk, input [71:0] cen, input d, output q);"
% m,
file=f)
print(" wire [%d:0] r;" % N, file=f)
print(" assign r[0] = d;", file=f)
print(" assign q = r[%d];" % N, file=f)
print("", file=f)
for i in range(N):
if N == 0 and len(slices) > 0:
loc = slices.pop()
print("(* LOC=\"%s\" *)" % loc, file=f)
if N != 0 and np.random.randint(16) == 0:
print(" wire srl_tmp_%d;" % i, file=f)
print(
" SRLC32E srl_%d (.CLK(clk[%d]), .CE(cen[%d]), .A(5'b11111), .D(r[%d]), .Q(srl_tmp_%d));"
% (i, (i * 32) // N, np.random.randint(72), i, i),
file=f)
print(
" FDCE ff_%d (.C(clk[%d]), .CLR(1'b0), .CE(cen[%d]), .D(srl_tmp_%d), .Q(r[%d]));"
% (i, (i * 32) // N, np.random.randint(72), i, i + 1),
file=f)
else:
print(
" FDCE ff_%d (.C(clk[%d]), .CLR(1'b0), .CE(cen[%d]), .D(r[%d]), .Q(r[%d]));"
% (i, (i * 32) // N, np.random.randint(72), i, i + 1),
file=f)
print("endmodule", file=f)
print("""
module roi(input [{DCLK_N}-1:0] clk, input [{DIN_N}-1:0] din, output [{DOUT_N}:0] dout);
wire [39:0] cen;
wire d;
wire q;
assign cen = din[0+:{DCLK_N}];
assign d = din[{DCLK_N}+:1];
assign dout = q;
""".format(DCLK_N=DCLK_N, DIN_N=DIN_N, DOUT_N=DOUT_N))
num_inputs = np.random.randint(8, DCLK_N)
print(" wire [511:0] clk_int;", file=f)
print(" wire [71:0] cen_int;", file=f)
print(" assign clk_int[%d:0] = clk;" % (num_inputs - 1), file=f)
print(" assign cen_int[%d:0] = cen;" % (num_inputs - 1), file=f)
print(" assign cen_int[71:64] = 8'hFF;", file=f)
bufgces = list(orig_bufgces)
np.random.shuffle(bufgces)
for i in range(num_inputs, 256):
a = np.random.randint(num_inputs)
b = None
while b is None or b == a:
b = np.random.randint(num_inputs)
c = None
while c is None or c == a or c == b:
c = np.random.randint(num_inputs)
bg = None
if len(bufgces) > 0:
bg = bufgces.pop()
if bg is not None and np.random.randint(20) >= bufg_prob or (
bg is not None and "DIV" in bg
and np.random.randint(19) >= bufg_prob):
if "DIV" in bg:
print(
" BUFGCE_DIV #(.BUFGCE_DIVIDE(%d), .IS_I_INVERTED(%d), .IS_CE_INVERTED(%d), .IS_CLR_INVERTED(%d)) bufg_%d (.I(clk[%d] ^ clk[%d] ^ clk[%d]), .CLR(!cen[%d]), .CE(cen[%d]), .O(clk_int[%d]));"
% (np.random.randint(1, 9), np.random.randint(2),
np.random.randint(2), np.random.randint(2), i, a, b, c,
np.random.randint(40), np.random.randint(40), i),
file=f)
else:
ctype = np.random.choice(["", "_1"])
params = " #(.IS_I_INVERTED(%d), .IS_CE_INVERTED(%d), .CE_TYPE(\"%s\")) " % (
np.random.randint(2), np.random.randint(2),
np.random.choice(["SYNC", "ASYNC"])) if ctype == "" else ""
print(
" BUFGCE%s %s bufg_%d (.I(clk[%d] ^ clk[%d] ^ clk[%d]), .CE(cen[%d]), .O(clk_int[%d]));"
% (ctype, params, i, a, b, c, np.random.randint(40), i),
file=f)
else:
print(" assign clk_int[%d] = clk[%d] ^ clk[%d] ^ clk[%d];" %
(i, a, b, c),
file=f)
if i < 64:
print(" assign cen_int[%d] = cen[%d] ^ cen[%d];" % (i, a, b),
file=f)
print("", file=f)
print(" wire [%d:0] r;" % M, file=f)
print(" assign r[0] = d;", file=f)
print(" assign q = r[%d];" % M, file=f)
for i in range(M):
print(
" layer_1_%d submod_%d(.clk(clk_int[%d +: 32]), .cen(cen_int), .d(r[%d]), .q(r[%d]));"
% (i, i, 32 * i, i, i + 1),
file=f)
print("endmodule", file=f)
ccio = []
with open('../ccio_pins.csv') as f:
for l in f:
l = l.strip()
if l:
ccio.append(l.split(',')[0])
np.random.shuffle(ccio)
with open("top.tcl", "w") as f:
for i in range(num_inputs):
if i >= len(ccio):
break
print("set_property PACKAGE_PIN %s [get_ports {clk[%d]}]" %
(ccio[i], i),
file=f)
print("set_property IOSTANDARD LVCMOS18 [get_ports {clk[%d]}]" %
(i),
file=f)
print('opt_design', file=f)
def print_top(seed):
np.random.seed(seed)
DCLK_N = 10
DIN_N = (16 * 2 + 8)
DOUT_N = 32
top_harness_clk(DCLK_N, DIN_N, DOUT_N)
print("")
print("""
module roi(input [{DCLK_N}-1:0] clk, input [{DIN_N}-1:0] din, output [31:0] dout);
wire [15:0] sr;
wire [15:0] ce;
wire [7:0] d;
wire [31:0] q;
assign sr = din[0+:16];
assign ce = din[16+:16];
assign d = din[32+:8];
assign dout = q;
""".format(DCLK_N=DCLK_N, DIN_N=DIN_N, DOUT_N=DOUT_N))
N = 200
D = ["d[%d]" % i for i in range(16)]
slices = gen_sites()
for i in range(N):
tile_type = np.random.choice(sorted(slices.keys()))
sl = np.random.choice(sorted(slices[tile_type]))
slices[tile_type].remove(sl)
m = SLICE_XY.match(sl)
assert m is not None
x = int(m.group(1))
y = int(m.group(2))
sl_up = 'SLICE_X{}Y{}'.format(x, y + 1)
if sl_up not in slices[tile_type]:
sl_up = ''
ffmode = np.random.randint(3, size=2)
clk = tuple(np.random.randint(DCLK_N, size=2))
sr = tuple([
"1'b1" if y >= 16 else "sr[%d]" % y
for y in np.random.randint(25, size=2)
])
ce = tuple([
"1'b1" if y >= 16 else "ce[%d]" % y
for y in np.random.randint(25, size=4)
])
def random_fftype(mode):
if mode == 0:
return np.random.choice(["FDSE", "FDRE"])
elif mode == 1:
return np.random.choice(["FDPE", "FDCE"])
elif mode == 2:
return np.random.choice(["LDPE", "LDCE"])
def random_bit():
return np.random.choice(D)
def random_data(width):
return "{%s}" % (", ".join([random_bit() for k in range(width)]))
fftypes = [random_fftype(ffmode[j // 8]) for j in range(16)]
used_outroute = [
np.random.choice(["FF", "FF2", "MUX"]) for k in range(8)
]
for j in range(8):
if used_outroute[j] == "FF":
fftypes[2 * j + 1] = "NONE"
elif used_outroute[j] == "FF2":
fftypes[2 * j] = "NONE"
else:
fftypes[2 * j] = "NONE"
fftypes[2 * j + 1] = "NONE"
cmode = np.random.choice(["NONE", "SINGLE_CY8", "DUAL_CY4"],
p=[0.1, 0.7, 0.2])
carry_used = False
if cmode == "SINGLE_CY8" and sl_up:
if np.random.randint(2):
carry_used = True
slices[tile_type].remove(sl_up)
else:
sl_up = ''
print(' wire [31:0] d%d;' % i)
print(' ultra_slice_carry #(')
print(' .LOC("%s"),' % sl)
print(' .LOC2("%s"),' % sl_up)
print(' .CARRY_USED(%d),' % carry_used)
for lut in "ABCDEFGH":
print(" .%sLUT_INIT(64'b%s)," % (lut, "".join(
str(_) for _ in np.random.randint(2, size=64))))
for j in range(16):
print(' .%sFF%s_TYPE("%s"),' %
("ABCDEFGH" [j // 2], "2" if
(j % 2) == 1 else "", fftypes[j]))
print(" .FF_INIT(16'b%s)," % "".join(
str(_) for _ in np.random.randint(2, size=16)))
for j1 in "ABCDEFGH":
for j2 in ("1", "2"):
print(' .FFMUX%s%s("%s"),' %
(j1, j2,
np.random.choice(
["XORIN", "CY"] if cmode != "NONE" else ["D6"])))
for j in range(8):
print(' .OUTMUX%s("%s"),' %
("ABCDEFGH" [j],
("D6" if used_outroute[j] != "MUX" else np.random.choice(
["D6", "XORIN", "CY"] if cmode != "NONE" else ["D6"]))))
print(" .CLKINV(2'd%d)," % np.random.randint(4))
print(" .SRINV(2'd%d)," % np.random.randint(4))
print(' .CARRY_TYPE("%s"),' % cmode)
for j in range(8):
print(' .DI%dMUX("%s"),' % (j, np.random.choice(["DI", "X"])))
print(' .CIMUX("%s"),' % np.random.choice(["1", "0", "X"]))
print(' .CITOPMUX("%s")' % (np.random.choice(["1", "0", "X"])
if cmode == "DUAL_CY4" else "CI"))
print(' ) slice%d (' % i)
for j in range(1, 7):
print(" .A%d(%s)," % (j, random_data(8)))
print(" .I(%s)," % random_data(8))
print(" .X(%s)," % random_data(8))
print(" .CLK({clk[%d], clk[%d]})," % clk)
print(" .SR({%s, %s})," % sr)
print(" .CE({%s, %s, %s, %s})," % ce)
print(" .O(d%d[7:0])," % i)
print(" .Q(d%d[15:8])," % i)
print(" .Q2(d%d[23:16])," % i)
print(" .MUX(d%d[31:24])" % i)
print(' );')
print()
D.clear()
for j in range(8):
D.append("d%d[%d]" % (i, j))
D.append("d%d[%d]" % (i, 24 + j))
if fftypes[2 * j] != "NONE":
D.append("d%d[%d]" % (i, 8 + j))
if fftypes[2 * j + 1] != "NONE":
D.append("d%d[%d]" % (i, 16 + j))
print(" assign q = d%d;" % (N - 1))
print("endmodule")
print("")
with open(os.path.join(os.getenv('URAY_DIR'), 'spec',
'slice_carry.v')) as f:
for l in f:
print(l.rstrip())
with open('top.tcl', 'w') as f:
f.write('opt_design')
def print_top(seed):
np.random.seed(seed)
DCLK_N = 10
DIN_N = (16 * 2 + 8)
DOUT_N = 32
top_harness_clk(DCLK_N, DIN_N, DOUT_N)
print("")
print("""
module roi(input [{DCLK_N}-1:0] clk, input [{DIN_N}-1:0] din, output [31:0] dout);
wire [15:0] sr;
wire [15:0] ce;
wire [7:0] d;
wire [31:0] q;
assign sr = din[0+:16];
assign ce = din[16+:16];
assign d = din[32+:8];
assign dout = q;
""".format(DCLK_N=DCLK_N, DIN_N=DIN_N, DOUT_N=DOUT_N))
N = 100
D = ["d[%d]" % i for i in range(8)]
slices = gen_sites()
for i in range(N):
tile_type = np.random.choice(sorted(slices.keys()))
sl = np.random.choice(sorted(slices[tile_type]))
slices[tile_type].remove(sl)
ffmode = np.random.randint(3, size=2)
clk = tuple(np.random.randint(DCLK_N, size=2))
sr = tuple([
"1'b1" if y >= 16 else "sr[%d]" % y
for y in np.random.randint(25, size=2)
])
ce = tuple([
"1'b1" if y >= 16 else "ce[%d]" % y
for y in np.random.randint(25, size=4)
])
def random_fftype(mode):
if mode == 0:
return np.random.choice(["NONE", "FDSE", "FDRE"])
elif mode == 1:
return np.random.choice(["NONE", "FDPE", "FDCE"])
elif mode == 2:
return np.random.choice(["NONE", "LDPE", "LDCE"])
def random_bit():
return np.random.choice(D)
def random_data(width):
return "{%s}" % (", ".join([random_bit() for k in range(width)]))
fftypes = [random_fftype(ffmode[j // 8]) for j in range(16)]
print(' wire [31:0] d%d;' % i)
print(' ultra_slice_logic #(')
print(' .LOC("%s"),' % sl)
for lut in "ABCDEFGH":
print(" .%sLUT_INIT(64'b%s)," %
(lut, "".join(str(_)
for _ in np.random.randint(2, size=64))))
for j in range(16):
print(' .%sFF%s_TYPE("%s"),' %
("ABCDEFGH"[j // 2], "2" if
(j % 2) == 1 else "", fftypes[j]))
print(" .FF_INIT(16'b%s)," %
"".join(str(_) for _ in np.random.randint(2, size=16)))
for j1 in "ABCDEFGH":
for j2 in ("1", "2"):
print(' .FFMUX%s%s("%s"),' %
(j1, j2, np.random.choice(["F7F8", "D6", "D5", "BYP"])))
for j in "ABCDEFGH":
print(' .OUTMUX%s("%s"),' %
(j, np.random.choice(["F7F8", "D6", "D5"])))
print(" .CLKINV(2'd%d)," % np.random.randint(4))
print(" .SRINV(2'd%d)" % np.random.randint(4))
print(' ) slice%d (' % i)
for j in range(1, 7):
print(" .A%d(%s)," % (j, random_data(8)))
print(" .I(%s)," % random_data(8))
print(" .X(%s)," % random_data(8))
print(" .CLK({clk[%d], clk[%d]})," % clk)
print(" .SR({%s, %s})," % sr)
print(" .CE({%s, %s, %s, %s})," % ce)
print(" .O(d%d[7:0])," % i)
print(" .Q(d%d[15:8])," % i)
print(" .Q2(d%d[23:16])," % i)
print(" .MUX(d%d[31:24])" % i)
print(' );')
print()
D.clear()
for j in range(8):
D.append("d%d[%d]" % (i, j))
D.append("d%d[%d]" % (i, 24 + j))
if fftypes[2 * j] != "NONE":
D.append("d%d[%d]" % (i, 8 + j))
if fftypes[2 * j + 1] != "NONE":
D.append("d%d[%d]" % (i, 16 + j))
print(" assign q = d%d;" % (N - 1))
print("endmodule")
print("")
with open(os.path.join(os.getenv('URAY_DIR'), 'spec', 'slice.v')) as f:
for l in f:
print(l.rstrip())
def print_top(seed):
np.random.seed(seed)
DCLK_N = 2
DIN_N = 66
DOUT_N = 36
top_harness_clk(DCLK_N, DIN_N, DOUT_N)
print("")
print("""
module roi(input [{DCLK_N}-1:0] clk, input [{DIN_N}-1:0] din, output [35:0] dout);
wire clk1;
wire clk1b;
wire rst;
wire ena;
wire enb;
wire cea;
wire ceb;
wire [13:0] ra;
wire [13:0] wa;
wire [3:0] we;
wire [17:0] wdata;
wire [10:0] sel;
wire [35:0] rdata;
assign clk1 = clk[0];
assign clk1b = clk[1];
assign rst = din[0];
assign ena = din[1];
assign enb = din[2];
assign cea = din[3];
assign ceb = din[4];
assign ra = din[5+:14];
assign wa = din[19+:14];
assign we = din[33+:4];
assign wdata = din[37+:18];
assign sel = din[55+:11];
assign dout = rdata;
""".format(DCLK_N=DCLK_N, DIN_N=DIN_N))
N = 200
print(" wire [35:0] int_d[0:%d-1];" % N)
print(
" assign rdata = sel[0] ? int_d[sel[10:1]][35:18] : int_d[sel[10:1]][17:0];"
)
for i in range(N):
write_width_b = np.random.choice([0, 1, 2, 4, 9, 18, 36])
read_width_a = np.random.choice(
[0, 1, 2, 4, 9, 18, 36], p=[0.05, 0.1, 0.1, 0.1, 0.1, 0.45, 0.1])
write_width_a = 0 if (write_width_b == 36
or read_width_a == 36) else np.random.choice(
[0, 1, 2, 4, 9, 18])
read_width_b = 0 if (
read_width_a == 36 or write_width_b == 36) else np.random.choice(
[0, 1, 2, 4, 9, 18], p=[0.05, 0.1, 0.1, 0.1, 0.1, 0.55])
cd = np.random.choice(["INDEPENDENT", "COMMON"])
if cd == "INDEPENDENT":
RDADDRCHANGE_choices = ["FALSE"]
else:
RDADDRCHANGE_choices = ["TRUE", "FALSE"]
WRITE_MODE_A = np.random.choice(
["NO_CHANGE", "READ_FIRST", "WRITE_FIRST"])
CASCADE_ORDER_A = np.random.choice(["NONE", "FIRST", "MIDDLE", "LAST"])
if read_width_a == 36 or write_width_b == 36:
WRITE_MODE_B = WRITE_MODE_A
CASCADE_ORDER_B = CASCADE_ORDER_A
else:
WRITE_MODE_B = np.random.choice(
["NO_CHANGE", "READ_FIRST", "WRITE_FIRST"])
CASCADE_ORDER_B = np.random.choice(
["NONE", "FIRST", "MIDDLE", "LAST"])
print(" RAMB18E2 #(")
print(" .CLOCK_DOMAINS(\"%s\")," % cd)
print(" .READ_WIDTH_A(%d)," % read_width_a)
print(" .READ_WIDTH_B(%d)," % read_width_b)
print(" .WRITE_WIDTH_A(%d)," % write_width_a)
print(" .WRITE_WIDTH_B(%d)," % write_width_b)
print(" .WRITE_MODE_A(\"%s\")," % WRITE_MODE_A)
print(" .WRITE_MODE_B(\"%s\")," % WRITE_MODE_B)
print(" .CASCADE_ORDER_A(\"%s\")," % CASCADE_ORDER_A)
print(" .CASCADE_ORDER_B(\"%s\")," % CASCADE_ORDER_B)
print(" .DOA_REG(%d)," %
(0 if (write_width_b == 36 or read_width_a == 36) else
np.random.randint(2)))
print(" .DOB_REG(%d)," %
(0 if (write_width_b == 36 or read_width_a == 36) else
np.random.randint(2)))
print(" .ENADDRENA(\"%s\")," % np.random.choice(
["FALSE", "TRUE"]))
print(" .ENADDRENB(\"%s\")," % np.random.choice(
["FALSE", "TRUE"]))
print(" .RDADDRCHANGEA(\"%s\")," %
np.random.choice(RDADDRCHANGE_choices))
print(" .RDADDRCHANGEB(\"%s\")," %
np.random.choice(RDADDRCHANGE_choices))
print(" .RSTREG_PRIORITY_A(\"%s\")," % np.random.choice(
["RSTREG", "REGCE"]))
print(" .RSTREG_PRIORITY_B(\"%s\")," % np.random.choice(
["RSTREG", "REGCE"]))
print(" .SLEEP_ASYNC(\"%s\")," % np.random.choice(
["FALSE", "TRUE"]))
for pin in ("CLKARDCLK", "CLKBWRCLK", "ENARDEN", "ENBWREN",
"RSTRAMARSTRAM", "RSTRAMB", "RSTREGARSTREG", "RSTREGB"):
print(" .IS_%s_INVERTED(%d)," % (pin, np.random.randint(2)))
print(" .INIT_A(18'd%d)," % np.random.randint(2**18))
print(" .INIT_B(18'd%d)," % np.random.randint(2**18))
print(" .SRVAL_A(18'd%d)," % np.random.randint(2**18))
print(" .SRVAL_B(18'd%d)" % np.random.randint(2**18))
print(" ) ram%d (" % i)
print(" .DINADIN(wdata[15:0]),")
print(" .DINPADINP(wdata[17:16]),")
print(" .DOUTADOUT(int_d[%d][15:0])," % i)
print(" .DOUTPADOUTP(int_d[%d][17:16])," % i)
print(" .ADDRARDADDR(ra),")
print(" .CLKARDCLK(clk1),")
print(" .ADDRENA(ena),")
print(" .ENARDEN(ena),")
print(" .REGCEAREGCE(cea),")
print(" .RSTRAMARSTRAM(rst),")
print(" .RSTREGARSTREG(rst),")
print(" .WEA(%s)," %
("2'b00" if write_width_a == 0 else "we[1:0]"))
print(" .DINBDIN(wdata[15:0]),")
print(" .DINPBDINP(wdata[17:16]),")
print(" .DOUTBDOUT(int_d[%d][33:18])," % i)
print(" .DOUTPBDOUTP(int_d[%d][35:34])," % i)
print(" .ADDRBWRADDR(wa),")
print(" .CLKBWRCLK(%s)," %
("clk1b" if cd == "INDEPENDENT" else "clk1"))
print(" .ENBWREN(enb),")
print(" .ADDRENB(enb),")
print(" .REGCEB(ceb),")
print(" .RSTRAMB(rst),")
print(" .RSTREGB(rst),")
print(" .WEBWE(%s)" %
("2'b00" if write_width_b == 0 else
("we[3:0]" if write_width_b == 36 else "we[3:2]")))
print(" );")
print()
print("endmodule")
def print_top(seed):
np.random.seed(seed)
DCLK_N = 10
DIN_N = (16 * 1 + 1)
DOUT_N = 1
top_harness_clk(DCLK_N, DIN_N, DOUT_N)
N = 5000
bufgces = list(gen_bufgs())
print(
"module layer_1(input [31:0] clk, input [71:0] cen, input d, output q);"
)
print(" wire [%d:0] r;" % N)
print(" assign r[0] = d;")
print(" assign q = r[%d];" % N)
print()
for i in range(N):
print(
" FDCE ff_%d (.C(clk[%d]), .CLR(1'b0), .CE(cen[%d]), .D(r[%d]), .Q(r[%d]));"
% (i, (i * 32) // N, np.random.randint(72), i, i + 1))
print()
print("endmodule")
M = 16
print("""
module roi(input [{DCLK_N}-1:0] clk, input [{DIN_N}-1:0] din, output [{DOUT_N}:0] dout);
wire [15:0] cen;
wire d;
wire q;
assign cen = din[0+:16];
assign d = din[16+:1];
assign dout = q;
""".format(DCLK_N=DCLK_N, DIN_N=DIN_N, DOUT_N=DOUT_N))
print(" wire [511:0] clk_int;")
print(" wire [71:0] cen_int;")
print(" assign clk_int[9:0] = clk;")
print(" assign clk_int[15:10] = clk;")
print(" assign cen_int[15:0] = cen;")
print(" assign cen_int[71:64] = 8'hFF;")
for i in range(16, 512):
a = np.random.randint(16)
b = None
while b is None or b == a:
b = np.random.randint(16)
c = None
while c is None or c == a or c == b:
c = np.random.randint(16)
bg = None
if len(bufgces) > 0:
bg = bufgces.pop()
if bg is not None and np.random.randint(3) > 0:
if "DIV" in bg:
print(
" BUFGCE_DIV #(.BUFGCE_DIVIDE(3)) bufg_%d (.I(clk[%d] ^ clk[%d] ^ clk[%d]), .CLR(0), .CE(1'b1), .O(clk_int[%d]));"
% (i, a, b, c, i))
else:
print(
" BUFGCE bufg_%d (.I(clk[%d] ^ clk[%d] ^ clk[%d]), .CE(1'b1), .O(clk_int[%d]));"
% (i, a, b, c, i))
else:
print(" assign clk_int[%d] = clk[%d] ^ clk[%d] ^ clk[%d];" %
(i, a, b, c))
if i < 64:
print(" assign cen_int[%d] = cen[%d] ^ cen[%d];" % (i, a, b))
print()
print(" wire [%d:0] r;" % M)
print(" assign r[0] = d;")
print(" assign q = r[%d];" % M)
for i in range(M):
print(
" layer_1 submod_%d(.clk(clk_int[%d +: 32]), .cen(cen_int), .d(r[%d]), .q(r[%d]));"
% (i, 32 * i, i, i + 1))
print("endmodule")