def execute_stm1(s, inst): if condition_passed(s, inst.cond): orig_Rn = s.rf[inst.rn] addr, end_addr = addressing_mode_4(s, inst) register_mask = inst.register_list # TODO: support multiple memory accessing modes? # MemoryAccess( s.B, s.E ) for i in range(16): if register_mask & 0b1: # Note from ISA document page A4-190: # If <Rn> is specified in <registers> and base register write-back # is specified: # - If <Rn> is the lowest-numbered register specified in # <registers>, the original value of <Rn> is stored. # - Otherwise, the stored value of <Rn> is UNPREDICTABLE. # # We check if i is Rn, and if so, we use the original value if i == inst.rn: s.mem.write(addr, 4, orig_Rn) else: s.mem.write(addr, 4, s.rf[i]) addr += 4 register_mask >>= 1 assert end_addr == addr - 4 s.rf[PC] = s.fetch_pc() + 4
def execute_stm1( s, inst ): if condition_passed( s, inst.cond ): orig_Rn = s.rf[ inst.rn ] addr, end_addr = addressing_mode_4( s, inst ) register_mask = inst.register_list # TODO: support multiple memory accessing modes? # MemoryAccess( s.B, s.E ) for i in range(16): if register_mask & 0b1: # Note from ISA document page A4-190: # If <Rn> is specified in <registers> and base register write-back # is specified: # - If <Rn> is the lowest-numbered register specified in # <registers>, the original value of <Rn> is stored. # - Otherwise, the stored value of <Rn> is UNPREDICTABLE. # # We check if i is Rn, and if so, we use the original value if i == inst.rn: s.mem.write( addr, 4, orig_Rn ) else: s.mem.write( addr, 4, s.rf[i] ) addr += 4 register_mask >>= 1 assert end_addr == addr - 4 s.rf[PC] = s.fetch_pc() + 4
def execute_stm1(s, inst): if condition_passed(s, inst.cond()): addr, end_addr = addressing_mode_4(s, inst) register_mask = inst.register_list() # TODO: support multiple memory accessing modes? # MemoryAccess( s.B, s.E ) for i in range(16): if register_mask & 0b1: s.mem.write(addr, 4, s.rf[i]) addr += 4 register_mask >>= 1 assert end_addr == addr - 4 s.rf[PC] = s.fetch_pc() + 4
def execute_ldm1(s, inst): if condition_passed(s, inst.cond()): addr, end_addr = addressing_mode_4(s, inst) register_mask = inst.register_list() # TODO: support multiple memory accessing modes? # MemoryAccess( s.B, s.E ) for i in range(15): if register_mask & 0b1: s.rf[i] = s.mem.read(addr, 4) addr += 4 register_mask >>= 1 if register_mask & 0b1: # reg 15 s.rf[PC] = s.mem.read(addr, 4) & 0xFFFFFFFE s.T = s.rf[PC] & 0b1 if s.T: raise FatalError("Entering THUMB mode! Unsupported!") assert end_addr == addr return assert end_addr == addr - 4 s.rf[PC] = s.fetch_pc() + 4
def execute_ldm1( s, inst ): if condition_passed( s, inst.cond ): addr, end_addr = addressing_mode_4( s, inst ) register_mask = inst.register_list # TODO: support multiple memory accessing modes? # MemoryAccess( s.B, s.E ) for i in range(15): if register_mask & 0b1: s.rf[ i ] = s.mem.read( addr, 4 ) addr += 4 register_mask >>= 1 if register_mask & 0b1: # reg 15 s.rf[PC] = s.mem.read( addr, 4 ) & 0xFFFFFFFE s.T = s.rf[PC] & 0b1 if s.T: raise FatalError( "Entering THUMB mode! Unsupported!") assert end_addr == addr return assert end_addr == addr - 4 s.rf[PC] = s.fetch_pc() + 4