def build_phase(self, phase): super().build_phase(phase) self.sqr = ram_sequencer.type_id.create("sqr", self) self.drv = ram_driver.type_id.create("drv", self) self.mon = ram_monitor.type_id.create("mon", self) arr = [] if UVMConfigDb.get(self, "", "vif", arr): self.vif = arr[0] if self.vif is None: uvm_fatal("RAM/AGT/NOVIF", "No virtual interface speficied") UVMConfigDb.set(self, "", "master_id", self.master_id)
def build_phase(self, phase): UVMTest.build_phase(self, phase) self.env = tb_env.type_id.create("env", self) UVMConfigDb.set(self.env, "bus", "dut", self.dut)