def test_const(const_value):
a = pe.const(const_value)
tests = complete(a, 4, 16)
compile(f'test_const_complete', 'test_pe_comp_unq1', a.opcode, tests)
run_verilator_test('test_pe_comp_unq1', f'sim_test_const_complete', 'test_pe_comp_unq1')
def test_irq(strategy, irq_en_0, irq_en_1, debug_trig, debug_trig_p, signed, worker_id):
op = "add"
flag_sel = 0x0 # Z
lut_code = 0x0
acc_en = 0
_op = getattr(pe, op)().flag(flag_sel).lut(lut_code).irq_en(irq_en_0, irq_en_1).signed(signed)
cfg_d = _op.instruction
if strategy is complete:
width = 4
N = 1 << width
tests = complete(_op, OrderedDict([
("data0", range(-1, 1)), # For now we'll verify that data0/data1
("data1", range(-1, 1)), # don't affect the output
("bit0", range(0, 2)),
("bit1", range(0, 2)),
("bit2", range(0, 2)),
]), lambda result: (test_output("res", result[0]),
test_output("res_p", result[1]),
test_output("irq", 1 if result[2] else 0)))
elif strategy is random:
return # We just test the LUT completely
body = bodysource(tests)
test = testsource(tests)
build_directory = "build_{}".format(worker_id)
if not os.path.exists(build_directory):
os.makedirs(build_directory)
compile_harness(f'{build_directory}/harness.cpp', test, body, lut_code, cfg_d, debug_trig, debug_trig_p)
run_verilator_test('test_pe_unq1', 'harness', 'test_pe_unq1', build_directory)
def test_signed_op(signed_op, signed):
a = getattr(pe, signed_op)(signed)
tests = complete(a, 4, 16)
compile(f'test_{signed_op}_complete', 'test_pe_comp_unq1', a.opcode, tests)
run_verilator_test('test_pe_comp_unq1', f'sim_test_{signed_op}_complete', 'test_pe_comp_unq1')
def test_signed_op(signed_op, signed, strategy):
a = getattr(pe, signed_op)(signed)
tests = get_tests(a, strategy, signed)
compile('harness', 'test_pe_comp_unq1', a.instruction, tests)
run_verilator_test('test_pe_comp_unq1', 'harness', 'test_pe_comp_unq1')
run_ncsim_test(signed_op, a.instruction, tests, strategy)
def test_op(strategy, op, flag_sel, signed, worker_id):
if flag_sel == 0xE:
return # Skip lut, tested separately
if flag_sel in [0x4, 0x5, 0x6, 0x7, 0xA, 0xB, 0xC, 0xD] and not signed: # Flag modes with N, V are signed only
return
if op == "abs" and not signed:
return # abs only defined in signed mode
lut_code = 0x00
args = [signed] if op in signed_ops else []
_op = getattr(pe, op)(*args).flag(flag_sel).lut(lut_code).signed(signed)
cfg_d = _op.instruction
if strategy is complete:
width = 4
N = 1 << width
tests = complete(_op, OrderedDict([
("data0", range(0, N) if not signed else range(- N // 2, N // 2)),
("data1", range(0, N) if not signed else range(- N // 2, N // 2)),
("bit0", range(0, 2)),
("bit1", range(0, 2)),
("bit2", range(0, 2)),
]), lambda result: (test_output("res", result[0]),
test_output("res_p", result[1]),
test_output("irq", 1 if result[2] else 0)))
elif strategy is random:
n = 16
width = 16
N = 1 << width
tests = random(_op, n, OrderedDict([
("data0", lambda : randint(0, N - 1) if not signed else randint(- N // 2, N // 2 - 1)),
("data1", lambda : randint(0, N - 1) if not signed else randint(- N // 2, N // 2 - 1)),
("bit0", lambda : randint(0, 1)),
("bit1", lambda : randint(0, 1)),
("bit2", lambda : randint(0, 1))
]), lambda result: (test_output("res", result[0]),
test_output("res_p", result[1]),
test_output("irq", 1 if result[2] else 0)))
body = bodysource(tests)
test = testsource(tests)
build_directory = "build_{}".format(worker_id)
if not os.path.exists(build_directory):
os.makedirs(build_directory)
compile_harness(f'{build_directory}/harness.cpp', test, body, lut_code, cfg_d)
run_verilator_test('test_pe_unq1', 'harness', 'test_pe_unq1', build_directory)
def test_op(op):
a = getattr(pe, op)()
tests = complete(a, 4, 16)
compile(f'test_{op}_complete', 'test_pe_comp_unq1', a.opcode, tests)
run_verilator_test('test_pe_comp_unq1', f'sim_test_{op}_complete', 'test_pe_comp_unq1')
if os.environ.get("TRAVIS", True):
# Skip on Travis because cadence tools not available
# FIXME: Should check for cadence tools available instead
return
ncsim.compile(f'test_{op}_complete', a.opcode, tests)
RTL_FOLDER = "../../hardware/generator_z/top/genesis_verif"
result = delegator.run(f"""
irun -top test_pe_comp_unq1_tb -timescale 1ns/1ps -l irun.log -access +rwc -notimingchecks -input ../../hardware/generator_z/impl/verif/cmd.tcl build/ncsim_test_{op}_complete_tb.v /nobackup/nikhil3/arm_mems/arm/tsmc/cln40g/sram_sp_hsc_rvt_hvt_rvt/r10p2/sram_512w_16b/sram_512w_16b.v {RTL_FOLDER}/cb_unq1.v {RTL_FOLDER}/cb_unq2.v {RTL_FOLDER}/cb_unq3.v {RTL_FOLDER}/global_signal_tile_unq1.v {RTL_FOLDER}/io1bit_unq1.v {RTL_FOLDER}/io1bit_unq2.v {RTL_FOLDER}/io1bit_unq3.v {RTL_FOLDER}/io1bit_unq4.v {RTL_FOLDER}/jtag_unq1.sv {RTL_FOLDER}/memory_core_unq1.v {RTL_FOLDER}/memory_tile_unq1.v {RTL_FOLDER}/mem_unq1.v {RTL_FOLDER}/pe_tile_new_unq1.v {RTL_FOLDER}/sb_unq1.v {RTL_FOLDER}/sb_unq2.v {RTL_FOLDER}/sb_unq3.v {RTL_FOLDER}/test_cmpr.sv {RTL_FOLDER}/test_full_add.sv {RTL_FOLDER}/test_lut.sv {RTL_FOLDER}/test_mult_add.sv {RTL_FOLDER}/test_opt_reg.sv {RTL_FOLDER}/test_pe_comp_unq1.sv {RTL_FOLDER}/test_pe_unq1.sv {RTL_FOLDER}/test_shifter_unq1.sv {RTL_FOLDER}/top.v
""")
assert not result.return_code, result.out + "\n" + result.err
assert "Failed!" not in result.out, result.out + "\n" + result.err
def test_input_modes(signed, worker_id, input_modes):
op = "add"
lut_code = randint(0, 15)
flag_sel = randint(0, 15)
if not signed:
# Skip flags involving V for unsigned mode
while flag_sel in [0x6, 0x7, 0xA, 0xB, 0xC, 0xD]:
flag_sel = randint(0, 15)
print(f"flag_sel={flag_sel}")
data0_mode, data1_mode, bit0_mode, bit1_mode, bit2_mode = input_modes
irq_en = 0
acc_en = 0
_op = getattr(pe, op)().flag(flag_sel).lut(lut_code).signed(signed)
for reg, mode in zip(
(_op.rega, _op.regb, _op.regd, _op.rege, _op.regf),
input_modes
):
reg(mode)
cfg_d = _op.instruction
strategy = random
n = 16
width = 16
N = 1 << width
tests = random(_op, n, OrderedDict([
("data0", lambda : randint(0, N - 1) if not signed else randint(- N // 2, N // 2 - 1)),
("data1", lambda : randint(0, N - 1) if not signed else randint(- N // 2, N // 2 - 1)),
("bit0", lambda : randint(0, 1)),
("bit1", lambda : randint(0, 1)),
("bit2", lambda : randint(0, 1))
]), lambda result: (test_output("res", result[0]),
test_output("res_p", result[1]),
test_output("irq", 1 if result[2] else 0)),
with_clk=True)
body = bodysource(tests)
test = testsource(tests)
build_directory = "build_{}".format(worker_id)
if not os.path.exists(build_directory):
os.makedirs(build_directory)
compile_harness(f'{build_directory}/harness.cpp', test, body, lut_code, cfg_d)
run_verilator_test('test_pe_unq1', f'harness', 'test_pe_unq1', build_directory)
def test_lut(strategy, signed, lut_code, worker_id, random_op):
# NOTE: In the past, we have seen issues with this test randomly failing,
# see https://github.com/StanfordAHA/CGRAGenerator/issues/69 for more info
op = random_op
flag_sel = 0xE # Lut output
bit2_mode = 0x2 # BYPASS
bit1_mode = 0x2 # BYPASS
bit0_mode = 0x2 # BYPASS
data1_mode = 0x2 # BYPASS
data0_mode = 0x2 # BYPASS
irq_en = 0
acc_en = 0
args = [signed] if op in signed_ops else []
_op = getattr(pe, op)(*args).flag(flag_sel).lut(lut_code).signed(signed)
cfg_d = _op.instruction
if strategy is complete:
width = 4
N = 1 << width
tests = complete(_op, OrderedDict([
("data0", range(-1, 1)), # For now we'll verify that data0/data1
("data1", range(-1, 1)), # don't affect the output
("bit0", range(0, 2)),
("bit1", range(0, 2)),
("bit2", range(0, 2)),
]), lambda result: (test_output("res", result[0]),
test_output("res_p", result[1]),
test_output("irq", 1 if result[2] else 0)))
elif strategy is random:
return # We just test the LUT completely
body = bodysource(tests)
test = testsource(tests)
build_directory = "build_{}".format(worker_id)
if not os.path.exists(build_directory):
os.makedirs(build_directory)
compile_harness(f'{build_directory}/harness.cpp', test, body, lut_code, cfg_d)
run_verilator_test('test_pe_unq1', 'harness', 'test_pe_unq1', build_directory)
