def mkRAMDefinition(name,
datawidth=32,
addrwidth=10,
numports=2,
sync=True,
with_enable=False):
m = Module(name)
clk = m.Input('CLK')
interfaces = []
for i in range(numports):
interface = RAMSlaveInterface(m,
name + '_%d' % i,
datawidth,
addrwidth,
with_enable=with_enable)
if sync:
interface.delay_addr = m.Reg(name + '_%d_daddr' % i, addrwidth)
interfaces.append(interface)
mem = m.Reg('mem', datawidth, length=2**addrwidth)
for interface in interfaces:
body = [
vtypes.If(interface.wenable)(mem[interface.addr](interface.wdata))
]
if sync:
body.append(interface.delay_addr(interface.addr))
if with_enable:
body = vtypes.If(interface.enable)(*body)
m.Always(vtypes.Posedge(clk))(body)
if sync:
m.Assign(interface.rdata(mem[interface.delay_addr]))
else:
m.Assign(interface.rdata(mem[interface.addr]))
return m
def mkRAMCore(name, datawidth=32, addrwidth=10, numports=2):
m = Module(name)
clk = m.Input('CLK')
interfaces = []
for i in range(numports):
interface = RAMInterface(
m, name + '_%d' % i, datawidth, addrwidth)
interface.delay_addr = m.Reg(name + '_%d_daddr' % i, addrwidth)
interfaces.append(interface)
mem = m.Reg('mem', datawidth, length=2**addrwidth)
for interface in interfaces:
m.Always(vtypes.Posedge(clk))(
vtypes.If(interface.wenable)(
mem[interface.addr](interface.wdata)
),
interface.delay_addr(interface.addr)
)
m.Assign(interface.rdata(mem[interface.delay_addr]))
return m
def mkRAMDefinition(name,
datawidth=32,
addrwidth=10,
numports=2,
initvals=None,
sync=True,
with_enable=False,
nocheck_initvals=False,
ram_style=None):
m = Module(name)
clk = m.Input('CLK')
interfaces = []
for i in range(numports):
interface = RAMSlaveInterface(m,
name + '_%d' % i,
datawidth,
addrwidth,
with_enable=with_enable)
if sync:
interface.delay_addr = m.Reg(name + '_%d_daddr' % i, addrwidth)
interfaces.append(interface)
if ram_style is not None:
m.EmbeddedCode(ram_style)
mem = m.Reg('mem', datawidth, 2**addrwidth)
if initvals is not None:
if not isinstance(initvals, (tuple, list)):
raise TypeError("initvals must be tuple or list, not '%s" %
str(type(initvals)))
base = 16
if not nocheck_initvals:
new_initvals = []
for initval in initvals:
if isinstance(initval, int):
new_initvals.append(vtypes.Int(initval, datawidth,
base=16))
elif isinstance(initval, vtypes.Int) and isinstance(
initval.value, int):
v = copy.deepcopy(initval)
v.width = datawidth
v.base = base
new_initvals.append(v)
elif isinstance(initval, vtypes.Int) and isinstance(
initval.value, str):
v = copy.deepcopy(initval)
v.width = datawidth
if v.base != 2 and v.base != 16:
raise ValueError('base must be 2 or 16')
base = v.base
new_initvals.append(v)
else:
raise TypeError("values of initvals must be int, not '%s" %
str(type(initval)))
initvals = new_initvals
if 2**addrwidth > len(initvals):
initvals.extend([
vtypes.Int(0, datawidth, base=base)
for _ in range(2**addrwidth - len(initvals))
])
m.Initial(*[mem[i](initval) for i, initval in enumerate(initvals)])
for interface in interfaces:
body = [
vtypes.If(interface.wenable)(mem[interface.addr](interface.wdata))
]
if sync:
body.append(interface.delay_addr(interface.addr))
if with_enable:
body = vtypes.If(interface.enable)(*body)
m.Always(vtypes.Posedge(clk))(body)
if sync:
m.Assign(interface.rdata(mem[interface.delay_addr]))
else:
m.Assign(interface.rdata(mem[interface.addr]))
return m