def mkLed(word_datawidth=128):
m = Module('blinkled')
clk = m.Input('CLK')
rst = m.Input('RST')
datawidth = 32
addrwidth = 10
myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
myram = vthread.RAM(m,
'myram',
clk,
rst,
word_datawidth,
addrwidth,
numports=2)
axi_in = vthread.AXIStreamInFifo(m,
'axi_in',
clk,
rst,
datawidth,
with_last=True,
noio=True)
axi_out = vthread.AXIStreamOutFifo(m,
'axi_out',
clk,
rst,
datawidth,
with_last=True,
noio=True)
maxi_in = vthread.AXIM_for_AXIStreamIn(axi_in, 'maxi_in')
maxi_out = vthread.AXIM_for_AXIStreamOut(axi_out, 'maxi_out')
fifo_addrwidth = 8
fifo_in = vthread.FIFO(m, 'fifo_in', clk, rst, word_datawidth,
fifo_addrwidth)
fifo_out = vthread.FIFO(m, 'fifo_out', clk, rst, word_datawidth,
fifo_addrwidth)
all_ok = m.TmpReg(initval=0)
def blink(size):
all_ok.value = True
for i in range(4):
print('# iter %d start' % i)
# Test for 4KB boundary check
offset = i * 1024 * 16 + (myaxi.boundary_size -
(word_datawidth // 8))
body(size, offset)
print('# iter %d end' % i)
if all_ok:
print('# verify: PASSED')
else:
print('# verify: FAILED')
vthread.finish()
def body(size, offset):
# write a test vector
for i in range(size):
wdata = i + 100
myram.write(i, wdata)
laddr = 0
gaddr = offset
myaxi.dma_write(myram, laddr, gaddr, size, port=1)
# AXI-stream read -> FIFO -> FIFO -> AXI-stream write
maxi_in.dma_read_async(gaddr, size * (word_datawidth // datawidth))
axi_in.write_fifo(fifo_in, size)
for i in range(size):
va = fifo_in.deq()
fifo_out.enq(va)
out_gaddr = (size + size) * (word_datawidth // 8) + offset
maxi_out.dma_write_async(out_gaddr,
size * (word_datawidth // datawidth))
axi_out.read_fifo(fifo_out, size)
# check
myaxi.dma_read(myram, 0, gaddr, size, port=1)
myaxi.dma_read(myram, size, out_gaddr, size, port=1)
for i in range(size):
v0 = myram.read(i)
v1 = myram.read(i + size)
if vthread.verilog.NotEql(v0, v1):
all_ok.value = False
th = vthread.Thread(m, 'th_blink', clk, rst, blink)
fsm = th.start(17)
return m
def mkLed():
m = Module('blinkled')
clk = m.Input('CLK')
rst = m.Input('RST')
datawidth = 32
addrwidth = 10
maxi = vthread.AXIM(m, 'maxi', clk, rst, datawidth)
maxi.disable_write()
saxi = vthread.AXISLiteRegister(m,
'saxi',
clk,
rst,
datawidth=32,
length=8)
axi_in = vthread.AXIStreamInFifo(m,
'axi_in',
clk,
rst,
datawidth,
with_last=True)
axi_out = vthread.AXIStreamOutFifo(m,
'axi_out',
clk,
rst,
datawidth,
with_last=True)
fifo_addrwidth = 8
fifo_a = vthread.FIFO(m, 'fifo_a', clk, rst, datawidth, fifo_addrwidth)
fifo_b = vthread.FIFO(m, 'fifo_b', clk, rst, datawidth, fifo_addrwidth)
fifo_c = vthread.FIFO(m, 'fifo_c', clk, rst, datawidth, fifo_addrwidth)
ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
strm0 = vthread.Stream(m, 'mystream_reduce', clk, rst)
a = strm0.source('a')
reduce_size = strm0.parameter('reduce_size')
v = a * a
sum, sum_valid = strm0.ReduceAddValid(v, reduce_size)
strm0.sink(sum, 'sum', when=sum_valid, when_name='sum_valid')
strm1 = vthread.Stream(m, 'mystream_bias', clk, rst)
x = strm1.source('x')
y = strm1.source('y')
z = x + y
strm1.sink(z, 'z')
def comp():
while True:
saxi.wait_flag(0, value=1, resetvalue=0)
saxi.write(1, 1) # set busy
read_size = saxi.read(2)
write_size = saxi.read(3)
reduce_size = saxi.read(4)
bias_addr = saxi.read(5)
if read_size <= 0:
read_size = 1
if write_size <= 0:
write_size = 1
if reduce_size <= 0:
reduce_size = 1
maxi.dma_read(ram_b, 0, bias_addr, write_size)
axi_in.write_fifo(fifo_a, read_size)
axi_out.read_fifo(fifo_c, write_size)
strm0.set_source_fifo('a', fifo_a, read_size)
strm0.set_parameter('reduce_size', reduce_size)
strm0.set_sink_fifo('sum', fifo_b, write_size)
strm1.set_source_fifo('x', fifo_b, write_size)
strm1.set_source('y', ram_b, 0, write_size)
strm1.set_sink_fifo('z', fifo_c, write_size)
strm0.run()
strm1.run()
strm0.join()
strm1.join()
saxi.write(1, 0) # unset busy
th = vthread.Thread(m, 'th_comp', clk, rst, comp)
fsm = th.start()
return m
def mkLed():
m = Module('blinkled')
clk = m.Input('CLK')
rst = m.Input('RST')
datawidth = 32
addrwidth = 10
myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
axi_in = vthread.AXIStreamInFifo(m, 'axi_in', clk, rst, datawidth,
with_last=True, noio=True)
maxi_in = vthread.AXIM_for_AXIStreamIn(axi_in, 'maxi_in')
axi_out = vthread.AXIStreamOutFifo(m, 'axi_out', clk, rst, datawidth,
with_last=True, noio=True)
maxi_out = vthread.AXIM_for_AXIStreamOut(axi_out, 'maxi_out')
fifo_addrwidth = 8
fifo_a = vthread.FIFO(m, 'fifo_a', clk, rst, datawidth, fifo_addrwidth)
ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
fifo_c = vthread.FIFO(m, 'fifo_c', clk, rst, datawidth, fifo_addrwidth)
# for comp_sequential
ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth)
strm = vthread.Stream(m, 'mystream', clk, rst,
dump=True, dump_base=10, dump_mode='all')
a = strm.source('a')
b = strm.source('b')
a = a * strm.Int(2)
b = b * strm.Int(3)
c = a + b
strm.sink(c, 'c')
def comp_stream(size, offset):
strm.set_source_fifo('a', fifo_a, size)
strm.set_source('b', ram_b, offset, size)
strm.set_sink_fifo('c', fifo_c, size)
strm.run()
# strm.join()
def comp_sequential(size, offset):
sum = 0
for i in range(size):
a = ram_a.read(i + offset)
b = ram_b.read(i + offset)
a = a * 2
b = b * 3
sum = a + b
ram_c.write(i + offset, sum)
def check(size, offset_stream, offset_seq):
all_ok = True
for i in range(size):
st = ram_c.read(i + offset_stream)
sq = ram_c.read(i + offset_seq)
if vthread.verilog.NotEql(st, sq):
all_ok = False
if all_ok:
print('# verify: PASSED')
else:
print('# verify: FAILED')
def comp(size):
# stream
offset = 0
# ram_b
myaxi.dma_read(ram_b, offset, 0, size)
# AXI-stream read -> FIFO -> Stream
# fifo_a
maxi_in.dma_read_async(512, size)
axi_in.write_fifo(fifo_a, size)
comp_stream(size, offset)
# Stream -> FIFO -> AXI-stream write
# fifo_c
maxi_out.dma_write_async(1024, size)
axi_out.read_fifo(fifo_c, size)
strm.join()
# sequential
offset = size
myaxi.dma_read(ram_a, offset, 512, size)
myaxi.dma_read(ram_b, offset, 0, size)
comp_sequential(size, offset)
myaxi.dma_write(ram_c, offset, 1024 * 2, size)
# verification
myaxi.dma_read(ram_c, 0, 1024, size)
myaxi.dma_read(ram_c, offset, 1024 * 2, size)
check(size, 0, offset)
vthread.finish()
th = vthread.Thread(m, 'comp', clk, rst, comp)
fsm = th.start(32)
return m
def mkLed():
m = Module('blinkled')
clk = m.Input('CLK')
rst = m.Input('RST')
datawidth = 32
addrwidth = 10
myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
axi_in = vthread.AXIStreamInFifo(m, 'axi_in', clk, rst, datawidth,
with_last=True, noio=True)
maxi_in = vthread.AXIM_for_AXIStreamIn(axi_in, 'maxi_in')
axi_out = vthread.AXIStreamOutFifo(m, 'axi_out', clk, rst, datawidth,
with_last=True, noio=True)
maxi_out = vthread.AXIM_for_AXIStreamOut(axi_out, 'maxi_out')
fifo_addrwidth = 8
fifo_a = vthread.FIFO(m, 'fifo_a', clk, rst, datawidth, fifo_addrwidth)
fifo_b = vthread.FIFO(m, 'fifo_b', clk, rst, datawidth, fifo_addrwidth)
fifo_c = vthread.FIFO(m, 'fifo_c', clk, rst, datawidth, fifo_addrwidth)
# for comp_sequential
ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth)
strm0 = vthread.Stream(m, 'mystream_reduce', clk, rst)
a = strm0.source('a') + 10
reduce_size = strm0.parameter('reduce_size')
sum, sum_valid = strm0.ReduceAddValid(a, reduce_size)
strm0.sink(sum, 'sum', when=sum_valid, when_name='sum_valid')
strm1 = vthread.Stream(m, 'mystream_bias', clk, rst)
x = strm1.source('x')
y = strm1.source('y')
z = x + y * 8 + 1
strm1.sink(z, 'z')
def comp_stream(size, reduce_size, offset):
strm0.set_source_fifo('a', fifo_a, size)
strm0.set_parameter('reduce_size', reduce_size)
strm0.set_sink_fifo('sum', fifo_b, size // reduce_size)
strm1.set_source_fifo('x', fifo_b, size // reduce_size)
strm1.set_source('y', ram_b, 0, size // reduce_size)
strm1.set_sink_fifo('z', fifo_c, size // reduce_size)
strm0.run()
strm1.run()
# strm0.join()
# strm1.join()
def comp_sequential(size, reduce_size, offset):
sum = 0
reduce_count = 0
write_addr = offset
for i in range(size):
a = ram_a.read(i + offset) + 10
sum += a
reduce_count += 1
if reduce_count == reduce_size:
y = ram_b.read(write_addr)
sum += y * 8 + 1
ram_c.write(write_addr, sum)
write_addr += 1
reduce_count = 0
sum = 0
def check(size, offset_stream, offset_seq):
all_ok = True
for i in range(size):
st = ram_c.read(i + offset_stream)
sq = ram_c.read(i + offset_seq)
if vthread.verilog.NotEql(st, sq):
all_ok = False
if all_ok:
print('# verify: PASSED')
else:
print('# verify: FAILED')
def comp(size):
# stream
offset = 0
reduce_size = 4
# AXI-stream read -> FIFO -> Stream
# fifo_a
myaxi.dma_read(ram_b, offset, 0, size)
maxi_in.dma_read_async(512, size)
axi_in.write_fifo(fifo_a, size)
comp_stream(size, reduce_size, offset)
# Stream -> FIFO -> AXI-stream write
# fifo_c
maxi_out.dma_write_async(1024, size // reduce_size)
axi_out.read_fifo(fifo_c, size // reduce_size)
strm0.join()
strm1.join()
# sequential
offset = size
myaxi.dma_read(ram_b, offset, 0, size)
myaxi.dma_read(ram_a, offset, 512, size)
comp_sequential(size, reduce_size, offset)
myaxi.dma_write(ram_c, offset, 1024 * 2, size // reduce_size)
# verification
myaxi.dma_read(ram_c, 0, 1024, size // reduce_size)
myaxi.dma_read(ram_c, offset, 1024 * 2, size // reduce_size)
check(size // reduce_size, 0, offset)
vthread.finish()
th = vthread.Thread(m, 'comp', clk, rst, comp)
fsm = th.start(32)
return m