def mkLed():
m = Module('blinkled')
clk = m.Input('CLK')
rst = m.Input('RST')
datawidth = 32
addrwidth = 10
myram = vthread.FixedRAM(m,
'myram',
clk,
rst,
datawidth,
addrwidth,
point=8)
def blink(times):
for i in range(times):
wdata = i
myram.write(i, wdata)
print('wdata = %d' % wdata)
sum = vthread.fixed.FixedConst(0, 8)
for i in range(times):
rdata = myram.read(i)
sum += rdata
print('rdata = %d' % rdata.int_part)
print('sum = %d' % sum.int_part)
th = vthread.Thread(m, 'th_blink', clk, rst, blink)
fsm = th.start(10)
return m
def mkLed():
m = Module('blinkled')
clk = m.Input('CLK')
rst = m.Input('RST')
datawidth = 32
addrwidth = 10
numports = 1
initvals = [i * 0.5 + 10 for i in range(2 ** addrwidth - 100)]
myram = vthread.FixedRAM(m, 'myram', clk, rst, datawidth, addrwidth,
point=8, numports=numports, initvals=initvals)
def blink(times):
all_ok = True
for i in range(times):
rdata = myram.read(i)
print('rdata = %f' % rdata)
expected = (vthread.fixed.cast_to_fixed(i, 8) * vthread.fixed.FixedConst(0.5, 8) +
vthread.fixed.FixedConst(10, 8))
if vthread.verilog.NotEql(rdata, expected):
all_ok = False
write_sum = vthread.fixed.FixedConst(0, 8)
for i in range(times):
rdata = myram.read(i)
b = vthread.fixed.FixedConst(0.25, 8)
wdata = rdata + b
myram.write(i, wdata)
write_sum += wdata
print('wdata = %f' % wdata)
print('write_sum = %d (%f)' % (write_sum.int_part, write_sum))
read_sum = vthread.fixed.FixedConst(0, 8)
for i in range(times):
rdata = myram.read(i)
print('rdata = %f' % rdata)
read_sum += rdata
expected = (vthread.fixed.cast_to_fixed(i, 8) * vthread.fixed.FixedConst(0.5, 8) +
vthread.fixed.FixedConst(10, 8) + vthread.fixed.FixedConst(0.25, 8))
if vthread.verilog.NotEql(rdata, expected):
all_ok = False
print('read_sum = %d (%f)' % (read_sum.int_part, read_sum))
if vthread.verilog.NotEql(read_sum, write_sum):
all_ok = False
if all_ok:
print('# verify: PASSED')
else:
print('# verify: FAILED')
th = vthread.Thread(m, 'th_blink', clk, rst, blink)
fsm = th.start(10)
return m
def mkLed():
m = Module('blinkled')
clk = m.Input('CLK')
rst = m.Input('RST')
datawidth = 32
addrwidth = 10
myram = vthread.FixedRAM(m,
'myram',
clk,
rst,
datawidth,
addrwidth,
point=8)
def blink(times):
all_ok = True
write_sum = 0
for i in range(times):
wdata = i
myram.write(i, wdata)
write_sum += wdata
print('wdata = %d' % wdata)
print('write_sum = %d' % write_sum)
read_sum = vthread.fixed.FixedConst(0, 8)
for i in range(times):
rdata = myram.read(i)
read_sum += rdata
print('rdata = %d (%f)' % (rdata.int_part, rdata))
if vthread.verilog.NotEql(rdata, vthread.fixed.cast_to_fixed(i,
8)):
all_ok = False
print('read_sum = %d (%f)' % (read_sum.int_part, read_sum))
if vthread.verilog.NotEql(read_sum,
vthread.fixed.cast_to_fixed(write_sum, 8)):
all_ok = False
if all_ok:
print('# verify: PASSED')
else:
print('# verify: FAILED')
th = vthread.Thread(m, 'th_blink', clk, rst, blink)
fsm = th.start(10)
return m
def mkLed():
m = Module('blinkled')
clk = m.Input('CLK')
rst = m.Input('RST')
datawidth = 32
addrwidth = 10
numports = 1
initvals = [i * 0.5 + 10 for i in range(2 ** addrwidth - 100)]
myram = vthread.FixedRAM(m, 'myram', clk, rst, datawidth, addrwidth,
point=8, numports=numports, initvals=initvals)
def blink(times):
for i in range(times):
rdata = myram.read(i)
print('rdata = %f' % rdata)
for i in range(times):
rdata = myram.read(i)
b = vthread.fixed.FixedConst(0.25, 8)
wdata = rdata + b
myram.write(i, wdata)
print('wdata = %f' % wdata)
sum = vthread.fixed.FixedConst(0, 8)
for i in range(times):
rdata = myram.read(i)
print('rdata = %f' % rdata)
sum += rdata
print('sum = %f' % sum)
th = vthread.Thread(m, 'th_blink', clk, rst, blink)
fsm = th.start(10)
return m
def mkLed():
m = Module('blinkled')
clk = m.Input('CLK')
rst = m.Input('RST')
datawidth = 32
addrwidth = 10
point = -4
myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
ram_a = vthread.FixedRAM(m,
'ram_a',
clk,
rst,
datawidth,
addrwidth,
point=point)
ram_b = vthread.FixedRAM(m,
'ram_b',
clk,
rst,
datawidth,
addrwidth,
point=point)
ram_c = vthread.FixedRAM(m,
'ram_c',
clk,
rst,
datawidth,
addrwidth,
point=point)
strm = vthread.Stream(m, 'mystream', clk, rst, dump=True)
a = strm.source('a', point=point)
b = strm.source('b', point=point)
const = strm.constant('const', point=point)
c = a * b + const
strm.sink(c, 'c')
def comp_stream(size, offset):
strm.set_source('a', ram_a, offset, size)
strm.set_source('b', ram_b, offset, size)
strm.set_sink('c', ram_c, offset, size)
const = vthread.fixed.FixedConst(32, point=point)
strm.set_constant('const', const)
strm.run()
strm.join()
def comp_sequential(size, offset):
for i in range(size):
a = ram_a.read(i + offset)
b = ram_b.read(i + offset)
const = vthread.fixed.FixedConst(32, point=point)
c = a * b + const
ram_c.write(i + offset, c)
print('a = %10g, b = %10g, const = %10g, c = %10g' %
(a, b, const, c))
def check(size, offset_stream, offset_seq):
all_ok = True
for i in range(size):
st = ram_c.read(i + offset_stream)
sq = ram_c.read(i + offset_seq)
if vthread.verilog.NotEql(st, sq):
all_ok = False
if all_ok:
print('# verify: PASSED')
else:
print('# verify: FAILED')
def comp(size):
# stream
offset = 0
myaxi.dma_read(ram_a, offset, 0, size)
myaxi.dma_read(ram_b, offset, 512, size)
comp_stream(size, offset)
myaxi.dma_write(ram_c, offset, 1024, size)
# sequential
offset = size
myaxi.dma_read(ram_a, offset, 0, size)
myaxi.dma_read(ram_b, offset, 512, size)
comp_sequential(size, offset)
myaxi.dma_write(ram_c, offset, 1024 * 2, size)
# verification
check(size, 0, offset)
vthread.finish()
th = vthread.Thread(m, 'th_comp', clk, rst, comp)
fsm = th.start(32)
return m
