def mkMain(n=128, datawidth=32, numports=2):
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
addrwidth = int(math.log(n, 2)) * 2
myram = RAM(m, 'myram', clk, rst, datawidth, addrwidth, 2)
myram.disable_write(1)
df = dataflow.DataflowManager(m, clk, rst)
fsm = FSM(m, 'fsm', clk, rst)
# dataflow
value = df.Counter()
# write dataflow (Dataflow -> RAM)
wport = 0
waddr = 0
wlen = 64
done = myram.write_dataflow(wport, waddr, value, wlen, cond=fsm)
fsm.goto_next()
fsm.If(done).goto_next()
fsm.goto_next()
# read dataflow (RAM -> Dataflow)
rport = 1
raddr = 0
rlen = 32
reuse_size = 4
rdata0, rdata1, rlast, done = myram.read_dataflow_reuse(
rport, raddr, rlen, num_outputs=2, reuse_size=reuse_size, cond=fsm)
fsm.goto_next()
fsm.If(done).goto_next()
# verify
rdata0_data, rdata0_valid = rdata0.read()
rdata1_data, rdata1_valid = rdata1.read()
rlast_data, rlast_valid = rlast.read()
sum0 = m.Reg('sum0', 32, initval=0)
sum1 = m.Reg('sum1', 32, initval=0)
expected_sum = ((raddr + raddr + rlen - 1) * rlen // 2) * reuse_size
seq = Seq(m, 'seq', clk, rst)
seq.If(rdata0_valid)(sum0.add(rdata0_data),
Systask('display', 'rdata0_data=%d', rdata0_data))
seq.If(rdata1_valid)(sum1.add(rdata1_data),
Systask('display', 'rdata1_data=%d', rdata1_data))
seq.Then().If(rlast_data == 1).Delay(1)(Systask('display',
'sum=%d expected_sum=%d',
sum0 + sum1, expected_sum))
return m
def mkMain(n=128, datawidth=32, numports=2):
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
addrwidth = int(math.log(n, 2)) * 2
myram = RAM(m, 'myram', clk, rst, datawidth, addrwidth, 2)
myram.disable_write(1)
df = dataflow.DataflowManager(m, clk, rst)
fsm = FSM(m, 'fsm', clk, rst)
# dataflow
value = df.Counter()
# write dataflow (Dataflow -> RAM)
wport = 0
waddr = 0
wlen = 64
done = myram.write_dataflow(wport, waddr, value, wlen, cond=fsm)
fsm.goto_next()
fsm.If(done).goto_next()
fsm.goto_next()
# read dataflow (RAM -> Dataflow)
rport = 1
raddr = 0
rlen = 32
rdata, rlast, done = myram.read_dataflow(rport, raddr, rlen, cond=fsm)
fsm.goto_next()
fsm.If(done).goto_next()
# verify
rdata_data, rdata_valid = rdata.read()
rlast_data, rlast_valid = rlast.read()
sum = m.Reg('sum', 32, initval=0)
expected_sum = (raddr + raddr + rlen - 1) * rlen // 2
seq = Seq(m, 'seq', clk, rst)
seq.If(rdata_valid)(
sum.add(rdata_data)
)
seq.Then().If(rlast_data == 1).Delay(1)(
Systask('display', 'sum=%d expected_sum=%d', sum, expected_sum)
)
return m
def mkMain(n=128, datawidth=32, numports=2):
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
addrwidth = int(math.log(n, 2)) * 2
myram = RAM(m, 'myram', clk, rst, datawidth, addrwidth, 2)
myram.disable_write(1)
df = dataflow.DataflowManager(m, clk, rst)
fsm = FSM(m, 'fsm', clk, rst)
# dataflow
value = df.Counter()
# write dataflow (Dataflow -> RAM)
wport = 0
waddr = 0
wlen = 64
done = myram.write_dataflow(wport, waddr, value, wlen, cond=fsm)
fsm.goto_next()
fsm.If(done).goto_next()
fsm.goto_next()
# read dataflow (RAM -> Dataflow)
rport = 1
raddr = 0
rlen = 32
rdata, rlast, done = myram.read_dataflow(rport, raddr, rlen, cond=fsm)
fsm.goto_next()
fsm.If(done).goto_next()
# verify
rdata_data, rdata_valid = rdata.read()
rlast_data, rlast_valid = rlast.read()
sum = m.Reg('sum', 32, initval=0)
expected_sum = (raddr + raddr + rlen - 1) * rlen // 2
seq = Seq(m, 'seq', clk, rst)
seq.If(rdata_valid)(sum.add(rdata_data))
seq.Then().If(rlast_data == 1).Delay(1)(
Systask('display', 'sum=%d expected_sum=%d', sum, expected_sum),
If(NotEql(sum, expected_sum))(Display('# verify: FAILED')).Else(
Display('# verify: PASSED')))
return m
def mkMain(n=128, datawidth=32, numports=2):
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
addrwidth = int(math.log(n, 2)) * 2
myram = RAM(m, 'myram', clk, rst, datawidth, addrwidth, 2)
myram.disable_write(1)
df = dataflow.DataflowManager(m, clk, rst)
fsm = FSM(m, 'fsm', clk, rst)
fsm.goto_next()
# dataflow
value = df.Counter(size=64)
value = value - 1
# write dataflow (Dataflow -> RAM)
wport = 0
waddr = 0
wlen = 64
done = myram.write_dataflow(wport, waddr, value, wlen, cond=fsm)
fsm.goto_next()
fsm.If(done).goto_next()
# verify
sum = m.Reg('sum', 32, initval=0)
expected_sum = (waddr + waddr + wlen - 1) * wlen // 2 - wlen
seq = Seq(m, 'seq', clk, rst)
seq.If(myram[0].wenable)(
sum.add(myram[0].wdata)
)
seq.Then().If(myram[0].addr == wlen - 1).Delay(2)(
Systask('display', 'sum=%d expected_sum=%d', sum, expected_sum)
)
return m